Solution - Ugrad.cs.ubc.ca

2 (10 marks) The Y86-Pipe-Minus CPU implementation is a pipelined version of the Y86 that does not detect or
eliminate hazards automatically.
Consider the following Y86 assembly code:
0x000: irmovl $10, %edx
0x006: irmovl $13, %eax
0x00c: subl %edx, %eax
0x00e: halt
2a What unexpected thing will happen if this code is run and why it will happen
Data harzard @ line 3.
values in register %eax and %edx haven’t been written back when ”subl” instuction is executed.
2b How can the developer fix it Write a modified version of the code that will behave as expected
irmovl $10, %edx
irmovl $13, %eax
nop
nop
nop
subl %edx, %eax
halt
2c Describe the two ways that the CPU designer could change the architecture to fix the problem that we discussed
in class, and explain why one is better than the other.
Stalling and Data forwarding (You need to simply explain what they are). Data forwarding is a better way
when taking throughput, consistency into consideration.
2d In the full, final, pipelined Y86 implementation (Y86-PIPE), there is a single type of data dependency that is
not completely eliminated using data forwarding. What is it, and why can’t it be fixed
use/load dependency cannot be fixed by using data forwarding since data is available only after memory stage
and it is needed at decode stage of the load instruction. One bubble is needed.
2