Solution - Ugrad.cs.ubc.ca

1 (10 marks)
CPSC 313, Winter 2010, Term 2 — Test 2 Solution
Date: February 25th, 2011; Instructor: Andrew Warfield
Untel Incorporated is in the process of designing a completely new processor. They have three designs available,
shown in the figure below: a sequential implementation (A) and two implementations based on three-stage pipelines
(B and C).
1a In the blanks provided on the right of the figure, specify the throughput and latency for each of these CPU
designs. Be sure to include the units that your numbers are measured in.
(A) Throughput: 1000//320 GIPS
Latency: 320 ps
(B) Throughput: 1000//120 GIPS
Latency: 360 ps
(C) Throughput: 1000//130 GIPS
Latency: 390 ps
Note that units are also subjects of marking.
1b The CPU is going to be used in a video game console. Assuming all properties of the three designs other than
the information provided in the figure are equal, which design should Untel choose Why
B is better since it has higher throughput
1c What is a superscalar CPU
A superscalar processor executes more than one instruction during a clock cycle by simultaneously dispatching
multiple instructions to redundant functional units on the processor. Each functional unit is not a separate CPU
core but an execution resource within a single CPU. It achieves higher parallelism and throughput.
1d Why has Symmetric Multi-Threading (SMT), also known as Hyperthreading, become popular in modern CPU
designs
Hyper-threading works by duplicating the state sections of the processor and thus appear as two ”logical”
processors to the host operating system, allowing the operating system to schedule two threads or processes
simultaneously. HTT makes better use of execution resources of the CPU, allows highter parallelism and
throughput.

2 (10 marks) The Y86-Pipe-Minus CPU implementation is a pipelined version of the Y86 that does not detect or
eliminate hazards automatically.
Consider the following Y86 assembly code:
0x000: irmovl $10, %edx
0x006: irmovl $13, %eax
0x00c: subl %edx, %eax
0x00e: halt
2a What unexpected thing will happen if this code is run and why it will happen
Data harzard @ line 3.
values in register %eax and %edx haven’t been written back when ”subl” instuction is executed.
2b How can the developer fix it Write a modified version of the code that will behave as expected
irmovl $10, %edx
irmovl $13, %eax
nop
nop
nop
subl %edx, %eax
halt
2c Describe the two ways that the CPU designer could change the architecture to fix the problem that we discussed
in class, and explain why one is better than the other.
Stalling and Data forwarding (You need to simply explain what they are). Data forwarding is a better way
when taking throughput, consistency into consideration.
2d In the full, final, pipelined Y86 implementation (Y86-PIPE), there is a single type of data dependency that is
not completely eliminated using data forwarding. What is it, and why can’t it be fixed
use/load dependency cannot be fixed by using data forwarding since data is available only after memory stage
and it is needed at decode stage of the load instruction. One bubble is needed.
2

3 (4 marks) The following program has two instructions that stall the Y86-Pipe pipeline. Identify these instructions,
list the number of cycles they stall, and explain the reason for the stall.
[A] irmovl $1, %eax # r[eax]

y86 Cheat Sheet!
Byte 0 1 2 3 4 5
halt 0 0
nop 1 0
rrmovl rA, rB
2 0 rA rB
irmovl V, rB 3 0 F rB V
rmmovl rA, D(rB) 4 0 rA rB
mrmovl D(rB), rA 5 0 rA rB
D
D
OPl rA, rB
6 fn rA rB
jXX Dest 7 fn Dest
cmovXX rA, rB
2 fn rA rB
call Dest 8 0 Dest
ret 9 0
pushl rA
popl rA
A 0 rA F
B 0 rA F
Operations
Branches
Moves
addl 6 0
jmp 7 0
jne 7 4
rrmovl 2 0
cmovne 2 4
subl 6 1
jle 7 1
jge 7 5
cmovle 2 1
cmovge 2 5
andl 6 2
jl 7 2
jg 7 6
cmovl 2 2
cmovg 2 6
xorl 6 3
je 7 3
cmove 2 3
4