The Vector Floating-Point Unit in a Synergistic Processor Element of ...
The Vector Floating-Point Unit in a Synergistic Processor Element of ...
The Vector Floating-Point Unit in a Synergistic Processor Element of ...
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<strong>Vector</strong> FPU <strong>of</strong> a <strong>Synergistic</strong> Process<strong>in</strong>g <strong>Element</strong> <strong>of</strong> a CELL <strong>Processor</strong><br />
Normalizer & Rounder<br />
Round<strong>in</strong>g modes<br />
• Graphics applications optimized for round towards zero /<br />
truncation round<strong>in</strong>g<br />
• Truncation is simplest <strong>of</strong> the 4 IEEE round<strong>in</strong>g modes<br />
• Allows for simpler and faster rounder hardware<br />
exp-lz<br />
lzaerr<br />
normalizer<br />
SPfpu supports only truncation round<strong>in</strong>g<br />
• Fraction rounder turns <strong>in</strong>to a result mux<br />
unf, ovf<br />
25b INC<br />
– Saves about 15fo4 on the fraction path<br />
• Exponent round<strong>in</strong>g becomes tim<strong>in</strong>g critical !<br />
– Full-blown rounder: latency hidden by normalizer & rounder<br />
– Truncation: normalizer faster than exponent round<strong>in</strong>g<br />
Speed up exponent round<strong>in</strong>g<br />
• SP operations with other round<strong>in</strong>g modes can be emulated by<br />
DPfpu: convert, DP op, convert<br />
Silvia M. Mueller | June 2005 | ARITH-17<br />
© 2005 IBM Corporation
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