The Vector Floating-Point Unit in a Synergistic Processor Element of ...
The Vector Floating-Point Unit in a Synergistic Processor Element of ...
The Vector Floating-Point Unit in a Synergistic Processor Element of ...
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<strong>Vector</strong> FPU <strong>of</strong> a <strong>Synergistic</strong> Process<strong>in</strong>g <strong>Element</strong> <strong>of</strong> a CELL <strong>Processor</strong><br />
Summary<br />
• SPfpu: high-frequency, low-latency, power & area efficient<br />
FPU design<br />
– 5.5 cycle FMA at an 11fo4 cycle time<br />
– About 450K transistors <strong>in</strong> 1.3mm 2 , fabricated with IBM 90nm SOI<br />
– Correct operation observed up to 5.6 GHz at 1.4V<br />
– Support<strong>in</strong>g a peak performance <strong>of</strong> 44.8 GFlops / SPE<br />
• Key enablers<br />
– Architecture & implementation optimized for target applications<br />
– Co-design <strong>of</strong> architecture, logic, circuit, and floorplan<br />
– Pipel<strong>in</strong>e stages are fully balanced: 3% max path delay difference<br />
– Intensive clock gat<strong>in</strong>g (wave, opcode & data dependent)<br />
Silvia M. Mueller | June 2005 | ARITH-17<br />
© 2005 IBM Corporation
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