P2003BDG NIKO-SEM

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003BDG
TO-252 (DPAK)
Lead-Free
PRODUCT SUMMARY
V (BR)DSS R DS(ON) I D
25 20m 35A G
D
S
1. GATE
2. DRAIN
3. SOURCE
ABSOLUTE MAXIMUM RATINGS (T C = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS SYMBOL LIMITS UNITS
Gate-Source Voltage V GS ±20 V
Continuous Drain Current
T C = 25 °C 35
T C = 100 °C
Pulsed Drain Current 1 I DM 120
Avalanche Current I AR 15
Avalanche Energy L = 0.133mH E AS 15
Repetitive Avalanche Energy 2 L = 0.05mH E AR 5.6
Power Dissipation
I D
25
T C = 25 °C 50
T C = 100 °C
Operating Junction & Storage Temperature Range T j , T stg -55 to 150
Lead Temperature ( 1 / 16 ” from case for 10 sec.) T L 275
THERMAL RESISTANCE RATINGS
THERMAL RESISTANCE SYMBOL TYPICAL MAXIMUM UNITS
Junction-to-Case R θJC 2.5
Junction-to-Ambient R θJA 75
°C / W
Case-to-Heatsink R θCS 0.7
1 Pulse width limited by maximum junction temperature.
2 Duty cycle ≤ 1
P D
35
A
mJ
W
°C
ELECTRICAL CHARACTERISTICS (T C = 25 °C, Unless Otherwise Noted)
PARAMETER SYMBOL TEST CONDITIONS
LIMITS
MIN TYP MAX UNIT
STATIC
Drain-Source Breakdown Voltage V (BR)DSS V GS = 0V, I D = 250µA 25
V
Gate Threshold Voltage V GS(th) V DS = V GS , I D = 250µA 1.0 1.5 3.0
Gate-Body Leakage I GSS V DS = 0V, V GS = ±20V ±250 nA
Zero Gate Voltage Drain Current
I DSS
V DS = 20V, V GS = 0V 25
µA
V DS = 20V, V GS = 0V, T J = 125 °C 250
1
DEC-23-2004

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003BDG
TO-252 (DPAK)
Lead-Free
On-State Drain Current 1 I D(ON) V DS = 10V, V GS = 10V 35 A
Drain-Source On-State
Resistance 1
R DS(ON)
V GS = 4.5V, I D = 15A 23 31
V GS = 10V, I D = 15A 15.5 20
Forward Transconductance 1 g fs V DS = 15V, I D = 30A 14 28 S
DYNAMIC
m
Input Capacitance C iss 530 700
Output Capacitance C oss V GS = 0V, V DS = 25V, f = 1MHz 200 275
Reverse Transfer Capacitance
C rss
60 90
Total Gate Charge 2 Q g 8.4 11
Gate-Source Charge 2 Q gs
V DS = 0.5V (BR)DSS , V GS = 10V,
2.5 3.1
Gate-Drain Charge 2
Q gd
I D = 15A 6.4 9.6
Turn-On Delay Time 2 t d(on) 6.2 9.3
Rise Time 2 t r V DD = 15V 11 17
Turn-Off Delay Time 2 t d(off) I D ≅ 15A, V GS = 10V, R GS = 12.7 23 34
pF
nC
nS
Fall Time 2 t f 18 27
SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (T C = 25 °C)
Continuous Current I S 35
Pulsed Current 3 I SM 120
Forward Voltage 1 V SD I F = I S , V GS = 0V 1.1 1.4 V
Reverse Recovery Time t rr 15 18 nS
Reverse Recovery Charge Q rr 2 3 nC
1 Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2.
2 Independent of operating temperature.
3 Pulse width limited by maximum junction temperature.
A
REMARK: THE PRODUCT MARKED WITH “P2003BDG”, DATE CODE or LOT #
Orders for parts with Lead-Free plating can be placed using the PXXXXXXG parts name.
2
DEC-23-2004

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003BDG
TO-252 (DPAK)
Lead-Free
TYPICAL CHARACTERISTICS
I ,DRAIN - SOURCE CURRENT( A )
D
60
55
50
45
40
35
30
25
20
15
10
5
0
ON-REGION CHARACTERISTIC
10.0V
7.0V 6.0V
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
V ,DRAIN- SOURCE VOLTAGE ( V )
DS
5.0V
4.5V
4.0V
3.5V
V GS =3.0V
ON- RESISTANCE VARIATION WITH DRAIN CURRENT AND GATE VOLTAGE
R DS(ON) ,NORMALIZED
DRAIN - SOURCE ON - RESISTANCE
3.0
2.5
2.0
1.5
1.0
0.5
V GS = 4.0V
0
0 10 20 30 40 50 60
I ,DRAIN CURRENT( A )
D
4.5V
5.0V
6.0V
7.0V
10V
R DS(ON) ,NORMALIZED
DRAIN - SOURCE ON - RESISTANCE
1.8
1.6
1.4
1.2
1.0
0.8
ON- RESISTANCE VARIATION WITH TEMPERATURE
I = 15A
D
V GS= 10V
R DS(ON) ,ON-RESISTANCE(OHM)
ON-RESISTANCE VARIATION WITH GATE-TO-SOURCE VOLTAGE
0.06
I = 15A
0.05
0.04
0.03
0.02
D
T = 125°C
A
T A = 25°C
0.6 -50
-25 0 25 50 75 100 125 150 175
T j ,JUNCTION TEMPERATURE( °C )
0.01
2
4
6
V GS,GATE TO SOURCE VOLTAGE
8 10
I ,DRAIN CURRENT( A )
D
60
50
40
30
20
10
V =10V
DS
TRANSFER CHARACTERISTICS
T A= -55°C 25°C
125°C
I ,REVERSE DRAIN CURRENT( A )
S
60
10
1
0.1
0.01
0.001
BODY DIODE FORWARD VOLTAGE VARIATION WITH
SOURCE CURRENT AND TEMPERATURE
V GS= 0V
T = 125°C
A
25°C -55°C
0 1
2
3 4 5
V GS,GATE TO SOURCE VOLTAGE
0.0001
0
0.2 0.4 0.6 0.8 1.0 1.2
V ,BODY DIODE FORWARD VOLTAGE( V )
SD
1.4
3
DEC-23-2004

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003BDG
TO-252 (DPAK)
Lead-Free
V GS ,GATE - SOURCE VOLTAGE ( V )
10
8
6
4
2
I = 15A D
GATE CHARGE CHARACTERISTICS
V DS = 5V
10V
15V
0
0 4 8 12 16
Q g ,GATE CHARGE ( nC )
2400
2000
SINGLEPULSE MAXIMUM POWER DISSIPATION
SINGLE PULSE
R JC = 2 .5°C/W
T C = 25°C
CAPACITANCE( pF )
10000
1000
3
10
100
CAPACITANCE CHARACTERISTICS
f = 1MHZ
V GS= 0V
10 1 5 10
V ,DRAIN TO SOURCE VOLTAGE ( V )
DS
Ciss
Coss
Crss
15 20 25 30
MAXIMUM SAFE OPERATING AREA
POWER( W )
1600
1200
800
I ,DRAIN CURRENT( A )
D
2
10
1
10
R Limit
ds(on)
10ms
DC
1ms
100µS
35.0µS
400
0
0.01
1
10
V GS= 10V
SINGLE PULSE
R JC= 2.5 °C/W
0 Tc = 25 °C
10
-1 0
1
0.1 1 10 100 1000
10
10
10
SINGLE PULSE TIME( SEC )
V DS,DRAIN - SOURCE VOLTAGE
TRANSIENT THERMAL RESPONSE CURVE
2
10
r ,NORMALIZED EFFECTIVE
( t )
TRANSIENT THERMAL RESISTANCE
0
10
-1
10
-2
10
10 -3
10
-4
D=0.5
0.20
0.10
0.05
0.02
0.01
-7 -6
10 10
Single pulse
-5
10
-4
10 10
t1 , TIME( ms )
-3
P(pk)
t1
-2
10
t2
1.R (t)=r(t)*R
JC
2.R JC = 2.5° C/W
3.T j + T C = P * R (t)
4.Duty Cycle,D =
JC
t1
t2
-1
10
0
10
4
DEC-23-2004

NIKO-SEM
N-Channel Logic Level Enhancement
Mode Field Effect Transistor
P2003BDG
TO-252 (DPAK)
Lead-Free
TO-252 (DPAK) MECHANICAL DATA
Dimension
mm
Min. Typ. Max.
Dimension
mm
Min. Typ. Max.
A 9.35 10.4 H 0.89 2.03
B 2.2 2.4 I 6.35 6.80
C 0.45 0.6 J 5.2 5.5
D 0.89 1.5 K 0.6 1
E 0.45 0.69 L 0.5 0.9
F 0.03 0.23 M 3.96 4.57 5.18
G 5.2 6.2 N
A
I B
C
J
H
G
1 2 3
F
L
E
M
D
K
5
DEC-23-2004