TCAD Overview
TCAD Overview
TCAD Overview
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<strong>TCAD</strong> Sentaurus Общий обзор<br />
Радченко Дмитрий<br />
Alternative Solutions Alt-S<br />
Технический директор<br />
Predictable Success
CONFIDENTIAL INFORMATION<br />
The Following Material Is Being Disclosed To You Pursuant To A<br />
Non-disclosure Agreement Between You Or Your Employer And<br />
Synopsys. Some Information Disclosed In This Presentation Is<br />
Pending Patent Application. Information Disclosed In This<br />
Presentation Shall Be Used Only As Permitted Under Such An<br />
Agreement.<br />
LEGAL NOTICE<br />
Information Contained In This Presentation Reflects Synopsys<br />
Plans As Of The Date Of This Presentation. Such Plans Are Subject<br />
To Completion And Are Subject To Change. Products Shall Be<br />
Offered And Purchased Only Pursuant To An Authorized quote And<br />
Purchase Order.<br />
© 2008 Synopsys, Inc. (2)<br />
Predictable Success
Predictable Success<br />
© 2008 Synopsys, Inc. (3)<br />
Predictable Success
© 2005 Synopsys, Inc. (13) CONFIDENTIAL<br />
Recent <strong>TCAD</strong> Milestones<br />
PA-DFM Launch<br />
SIGMA-C Integration<br />
Sentaurus Lithography<br />
Launch<br />
10/06<br />
02/08<br />
TFM Introduction<br />
ISE Integration<br />
Sentaurus Launch<br />
5/05<br />
10/05<br />
8/06<br />
New Generation Standard for <strong>TCAD</strong> Simultaion<br />
Advanced,<br />
calibrated<br />
physical<br />
models<br />
Robust<br />
numerics &<br />
software<br />
implement-<br />
ations<br />
Accurate &<br />
predictive results<br />
Synopsys<br />
Sentaurus<br />
Self-consistent<br />
2D & 3D<br />
modeling<br />
capabilities<br />
ISE<br />
+<br />
Many New<br />
Features<br />
11/04<br />
© 2008 Synopsys, Inc. (4)<br />
Predictable Success
Extending <strong>TCAD</strong> into Manufacturing & Design<br />
Device<br />
Research<br />
Core <strong>TCAD</strong><br />
Process<br />
Module<br />
Development<br />
Technology Life Cycle<br />
Process<br />
Integration<br />
New<br />
Product<br />
Introduction<br />
Analyze<br />
• Process variability<br />
• Design for Manufacturing<br />
Process-Aware<br />
DFM<br />
Production<br />
Ramp<br />
<strong>TCAD</strong> for<br />
Manufacturing<br />
Explore Optimize Control<br />
Volume<br />
Manufacturing<br />
Explore<br />
• New processes<br />
• Virtual devices<br />
Optimize<br />
• Performance<br />
• Manufacturability<br />
Control<br />
• Yield analysis<br />
• Statistical process control<br />
• Advanced process control<br />
• Manufacturing for Design (MFD)<br />
© 2008 Synopsys, Inc. (5)<br />
Predictable Success
Synopsys <strong>TCAD</strong> Product Portfolio<br />
Lithography<br />
Sentaurus Litho.<br />
EUV (8/08)<br />
Sentaurus<br />
Lithography<br />
Sentaurus Litho.<br />
E-Beam (12/08)<br />
Raphael<br />
Example Library<br />
Sentaurus Topography<br />
Sentaurus<br />
Structure<br />
Editor<br />
Sentaurus Workbench<br />
Sentaurus Process<br />
Sentaurus Device<br />
Raphael NXT<br />
Interconnect<br />
Technology Development<br />
Calibration<br />
Manufacturing<br />
PCM Studio<br />
Fammos<br />
Seismos<br />
Paramos<br />
Process-Aware Design For Manufacturing<br />
© 2008 Synopsys, Inc. (6)<br />
Predictable Success
Core <strong>TCAD</strong><br />
© 2008 Synopsys, Inc. (7)<br />
Predictable Success
Sentaurus Process<br />
Sentaurus Process<br />
Mechanical Stress<br />
Kinetic Monte Carlo<br />
Multidimensional 2D/3D<br />
• General Purpose Process Simulator<br />
• Multidimensional 1D/2D/3D<br />
• Advanced Models for:<br />
• Implantation<br />
• Diffusion<br />
• Laser/Flash Annealing<br />
• Oxidation<br />
• Deposition and Etching<br />
• Adaptive Meshing<br />
• User-Defined Model Interface<br />
Flash/Laser Annealing<br />
© 2008 Synopsys, Inc. (8)<br />
Predictable Success
Sentaurus Device<br />
Optoelectronics<br />
Quantum Effects<br />
Device Monte Carlo<br />
Multidimensional 2D/3D<br />
Sentaurus Device<br />
Heterostructure Capabilities<br />
• General Purpose Device Simulator<br />
• Silicon and Compound Semiconductors<br />
• Advanced Transport Models<br />
• State-of-the-Art Linear Solvers<br />
• Efficient, full 3D Meshing<br />
• Full-Wave Electromagnetic Solver<br />
• User-Defined Model Interface<br />
Mixed-Mode Simulation<br />
© 2008 Synopsys, Inc. (9)<br />
Predictable Success
Sentaurus Topography<br />
RIE<br />
Tench Filling with Void Formation<br />
Sentaurus Topography<br />
CMP<br />
Ion Milling<br />
• Robust Level-Set Numerical Models<br />
• Deposition Models<br />
• LPCVD, PECVD, HDP-CVD, APCVD<br />
• Spin-on-Glass<br />
• Reflow<br />
• Etching Models<br />
• Wet etching<br />
• High-density plasma<br />
• Reactive ion etching<br />
• Ion milling<br />
• Chemical Mechanical Polishing<br />
• External ion angular/energy distributions<br />
• Interface to Sentaurus Process<br />
Topography simulation of<br />
NAND flash cell<br />
© 2008 Synopsys, Inc. (10)<br />
Predictable Success
Sentaurus Structure Editor<br />
• Easy to use GUI<br />
• Scripting Language<br />
• Advanced Geometric Modeling<br />
• Process Emulation Capability<br />
• Analytic Doping Definitions<br />
• Direct Interface to Meshing Engines<br />
Process Emulation Mode<br />
Sentaurus<br />
Structure<br />
Editor<br />
Sweeping of 2D Structures<br />
Advanced Geometric Operations: Swadowing, etc<br />
Complex 3D Device Structures<br />
© 2008 Synopsys, Inc. (11)<br />
Predictable Success
Sentaurus Workbench<br />
Sentaurus Workbench<br />
• <strong>TCAD</strong> framework environment<br />
• Project management<br />
• Design-of-Experiments<br />
• Job Farming<br />
• Advanced Visualization<br />
Advanced Visualization<br />
X-Y Data Plotting<br />
<strong>TCAD</strong> Project Management<br />
© 2008 Synopsys, Inc. (12)<br />
Predictable Success
Sentaurus Lithography<br />
SENTAURUS LITHOGRAPHY<br />
Rigorous EM Simulation of<br />
Wafer Topography<br />
• Lithography simulator for process development<br />
Simulation of Topography<br />
• Accounts for optical aberrations<br />
on Wafer<br />
•3D topographic mask simulation<br />
•Rigorous calculations of electromagnetic field on wafer<br />
• Full range of resist systems, including chemically amplified resists<br />
• Models exposure, reaction, amplification and diffusion during post-exposure bak<br />
• Rigorous models for image formation and resist development<br />
•Cell size imaging simulations and hot spot detection at resist level<br />
Efficient algorithms enable<br />
large cell simulation<br />
Imaging contours with<br />
hot spot detection<br />
Rigorous Simulation of 3D Masks<br />
© 2008 Synopsys, Inc. (13)<br />
Predictable Success
Raphael<br />
Process Effects<br />
Raphael<br />
Flexible Structure Generation with<br />
Sentaurus Structure Editor<br />
Capacitance Extraction<br />
• Gold standard interconnect field solver<br />
• Capacitance<br />
• Resistance<br />
• Inductance<br />
• Automatic generation of Parasitic Database<br />
• Calibration of LPE rule decks<br />
• Sentaurus Structure Editor interface<br />
Advanced Visualization<br />
L and R Extraction<br />
© 2008 Synopsys, Inc. (14)<br />
Predictable Success
Time (min)<br />
Raphael NXT<br />
4500<br />
4000<br />
3500<br />
3000<br />
2500<br />
2000<br />
1500<br />
1000<br />
500<br />
Periodic Boundary Conditions<br />
Lithography Based Extraction<br />
Layout<br />
0<br />
1 2 4 6 8<br />
Processors (#)<br />
Distributed Processing<br />
Star-RCXT<br />
Raphael NXT<br />
StarXtract<br />
RANXT DB<br />
Star-RCXT DB<br />
RA NXT<br />
• Chip-level critical net capacitance extractor<br />
• Seamless integration with Star-RCXT<br />
• Highly accurate full 3D capacitance extraction<br />
• Efficient Floating Random Walk Algorithm<br />
• High capacity: handles layouts with millions of polygons<br />
• Distributed processing with excellent scaling<br />
xTractor<br />
Critical Nets<br />
Parasitic Netlist<br />
Comparison Report<br />
Final Parasitic Netlist<br />
© 2008 Synopsys, Inc. (15)<br />
Predictable Success
<strong>TCAD</strong> for Manufacturing<br />
© 2008 Synopsys, Inc. (16)<br />
Predictable Success
Vth5[V]<br />
Ion5[ A/um]<br />
Calibration<br />
Wafer Processing<br />
Initial Lots<br />
Integration<br />
Optimization<br />
Manufacturability<br />
Next Generation<br />
Technology<br />
Baseline Technology<br />
800<br />
600<br />
400<br />
200<br />
0<br />
0.01 0.1 1 10<br />
Lact[um]<br />
Initial Scaling<br />
Process/Device Modeling<br />
Performance Optimization<br />
<strong>TCAD</strong><br />
Process compact model<br />
Calibration<br />
0.34<br />
0.3<br />
0.26<br />
0.22<br />
0.18<br />
0.01 0.1 1 10<br />
Lact[um]<br />
Electrical Data<br />
• Saves technology development time<br />
• Reduces number of development wafers<br />
• Optimizes technology performance<br />
• Improves manufacturability and yield<br />
SIMS Profiles<br />
© 2008 Synopsys, Inc. (17)<br />
Predictable Success
Sentaurus TFM<br />
Parallel Coordinate Plots<br />
Correlation Studies<br />
Process<br />
Parameters<br />
r i = f(f i )<br />
Device<br />
Characteristics<br />
Sentaurus TFM<br />
Process Compact Models<br />
• Process window optimization<br />
• Manufacturing control<br />
• Process variation to device performance correlation<br />
• Process Compact Models derived from <strong>TCAD</strong> simulations<br />
© 2008 Synopsys, Inc. (18)<br />
Predictable Success
Frequency<br />
Number of Parts<br />
Frequency<br />
<strong>TCAD</strong>-Driven Process Control<br />
Uncontrolled<br />
Controlled<br />
Good<br />
Parts<br />
Slow<br />
Parts<br />
High<br />
Leakage<br />
Parts<br />
Uncontrolled<br />
Controlled<br />
Good<br />
Parts<br />
Slow<br />
Parts<br />
High<br />
Leakage<br />
Parts<br />
Power<br />
slow good leaking<br />
Power<br />
Gate<br />
oxide<br />
Gate CD<br />
Halo<br />
implant<br />
S/D XT<br />
implant<br />
RTA temp<br />
I off I on Spec<br />
limit<br />
Nominal<br />
Nominal<br />
Measure<br />
Control<br />
Spec<br />
limit<br />
© 2008 Synopsys, Inc. (19)<br />
Predictable Success
Process-Aware DFM<br />
© 2008 Synopsys, Inc. (20)<br />
Predictable Success
Delay Variation<br />
-100%<br />
-50%<br />
0%<br />
50%<br />
100%<br />
Paramos<br />
Manufacturing<br />
Calibration<br />
<strong>TCAD</strong><br />
T ox<br />
L g<br />
N channel<br />
I-V, C-V database<br />
SPICE Extraction<br />
Process-Aware Compact<br />
SPICE Model<br />
Paramos<br />
Process Parameters<br />
SPICE<br />
Simulation<br />
Some Variability Sources in CMOS<br />
30%<br />
Gate oxidation temperature (P ox )<br />
20%<br />
n-Halo implant (P hn )<br />
10%<br />
L (P lg )<br />
0%<br />
Model Extraction Flow using Paramos<br />
• Extracts process-aware SPICE parameters for detailed<br />
analysis of the impact of global variations at the circuit level<br />
• Based on rigorous <strong>TCAD</strong> simulations<br />
• Provides bi-directional link between process information and<br />
circuit behavior<br />
-10%<br />
-20%<br />
Normalized process variation<br />
Correlating Delay Variation to Process<br />
Paramos<br />
© 2008 Synopsys, Inc. (21)<br />
Predictable Success
Seismos LX and Seismos CX<br />
<strong>TCAD</strong> for<br />
Manufacturing<br />
Gate<br />
Cap layer<br />
Spacer<br />
Layout<br />
Schematic<br />
Runset<br />
STI<br />
SiGe S/D<br />
Z<br />
Drawn GDSII<br />
Hercules LVS<br />
X<br />
Y<br />
Star-RCXT<br />
PrimeYield LCC<br />
Netlist (RC, xy)<br />
Contour GDSII<br />
Seismos LX + CX<br />
Annotated Spice Netlist<br />
Baseline BSIM<br />
HSPICE / HSIM / Nanosim<br />
• Simulates and analyses changes to transistor characteristics<br />
due to proximity variations arising from layout-induced<br />
stress, well proximity and Lithography effects<br />
• Annotates compact models to reflect impact on Vt and mobility<br />
• Integrates into existing design flows<br />
Seismos<br />
© 2008 Synopsys, Inc. (22)<br />
Predictable Success
Fammos<br />
Visualization of Stress Components<br />
Stresses in Metal 2 and Metal 3 Cu Lines<br />
• Simulates mechanical stress in BEOL process flows<br />
• Accounts for all major stress sources, including external stresses<br />
• Design specifically for semiconductor applications<br />
• Models key problems affecting process design and reliability<br />
of Cu/low k interconnect structures<br />
Fammos<br />
Stress Gradient at Bottom of Via<br />
© 2008 Synopsys, Inc. (23)<br />
Predictable Success
<strong>TCAD</strong> Applications<br />
CMOS<br />
Opto<br />
•LEDs, LASERs<br />
•Image sensors<br />
•Photodetectors<br />
•Deep submicron transistors<br />
•Sophisticated models<br />
•Atomistic modeling<br />
RF<br />
•High-speed devices<br />
Base Al<br />
•Compound semiconductors<br />
0.3 Ga 0.7 As<br />
GaAs<br />
Emitter<br />
Synopsys<br />
<strong>TCAD</strong><br />
Products<br />
Power<br />
Memory<br />
•Flash<br />
•DRAM<br />
Collector<br />
•Complex structures & processes<br />
•Mixed mode simulation<br />
© 2008 Synopsys, Inc. (24)<br />
Predictable Success
Synopsys <strong>TCAD</strong><br />
Used by 19 out of 20 top semiconductor<br />
companies worldwide<br />
Synopsys<br />
<strong>TCAD</strong><br />
Today<br />
Technical and market leadership across all<br />
technologies: DSM, Power, Memory,<br />
Analog and Optoelectronics<br />
Strong R&D program with research &<br />
academia<br />
Dedicated support organization focusing<br />
on customer success<br />
Complementary Consulting and<br />
Engineering Service Offerings<br />
© 2008 Synopsys, Inc. (25)<br />
Predictable Success
Predictable Success<br />
© 2008 Synopsys, Inc. (26)<br />
Predictable Success
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