Simulation of Self-Heating and Temperature Effect in GaN-based ...

Mater. Res. Soc. Symp. Proc. Vol. 892 © 2006 Materials Research Society0892-FF13-05.1Simulation of Self-Heating and Temperature Effect in GaN-basedMetal-Semiconductor Field-Effect TransistorValentin O. Turin 1 and Alexander A. BalandinNano-Device Laboratory, Department of Electrical EngineeringUniversity of California at RiversideRiverside, CA 92521, U.S.A.ABSTRACTTwo-dimensional electro-thermal simulations of GaN-based metal-semiconductor fieldeffecttransistor are performed in the framework of the drift-diffusion model. The dependenceof the hot spot temperature in transistors with many gates on the gate-to-gate pitch is studied.The case of SiC substrate is compared to the case of sapphire substrate. The ambienttemperature effect on transistor performance is simulated. The specific of a thermal breakdownin GaN-based devices is discussed. The results obtained can be useful for the optimization ofthe thermal design for field-effect transistors.INTRODUCTIONUnderstanding the self-heating and the temperature effect in GaN-based field-effecttransistors (FETs) [1] is an important problem because these devices are promising candidatesfor ultra-high-power microwave systems, power electronics and high temperature applications[2-4]. In this paper, two-dimensional (2D) electro-thermal simulations for the GaN metalsemiconductorfield-effect transistor (MESFET) are performed in the framework of the driftdiffusionmodel (DDM). These simulations are executed with the DESSIS software. As isusual, the devices under consideration have a top passivation coating with good thermalinsulation properties. Therefore, we will ignore the heat sink from the top of the device as wellas heat loss by radiation and convection.HEAT TRANSFER IN SUBSTRATELet us consider heat diffusion from the point and linear heat sources under thermoinsulatingpassivation coating in simplified transistor structure with lateral boundaries extendedto infinity. The heat source is deposited on the top of a thick substrate with thickness L andwith thermal conductivity k 1 placed on a half-space heat sink material with thermalconductivity k 2 . The approach based on a method of images [5] can be employed to writeexplicit form expressions for temperature distribution from the point (q) and linear (σ) heatsources in the substrate.Due to the symmetry of a schematic two-layer transistor structure, we can consider thedoubled heat source (x=L) centered in the layer with thermal conductivity k 1 surrounded by the1 Corresponding author: voturin@ee.ucr.edu

0892-FF13-05.2Figure 1. The dependence of the size of a heat flow through the substrate bottom (measured in the substratethickness units) on parameter K = k 2 /k 1 from the point heat source (a) and from the linear heat source (b). Figureon each curve shows respective fraction of the whole heat flow.ambient with thermal conductivity k 2 . For this case, following the method of images, we havetemperature distribution in the central layer from the set of heat sources:qNN2= α q , x N= L( 1 + 2N),N = 0, ± 1, ± 2...(1)Now we can find a temperature distribution in the central layer for the case of the pointheat source by superimpose temperature distributions from all point heat sources (r is atransversal coordinate, T 0 is temperature on infinite distance):T( x,r)= T02q+4πkα∑ +∞= 21 N −∞+N( x − L( 2N+ 1))r2. (2)Note that for the case of linear heat source, temperature is determined with precision upto an additive constant. This constant makes no sense in consideration of a heat flow. Hence,for the case of a linear heat source, we can write equation for the temperature distribution inthe center layer as:T2σ= − ∑ ∞, α4πk( x r)+ 1 N=−∞Nln( x − L( 2N+ 1))r202+ r2+ const . (3)The dependence of the size of different fractions of a whole heat flow (WHF) throughthe substrate bottom on parameter K = k 2 /k 1 is presented in Fig. 1(a) for a point heat source andin Fig. 1(b) for a linear heat source. Saturated parts of curves for large K correspond to the caseof a perfect heat sink (k 2 →∞) that is the isothermal boundary condition on the substrate bottomsurface. From these graphs, we can see that, even for the case of a perfect heat sink, dimensionof the heat spreading in the substrate is larger than the substrate thickness. For example, for thecase of 0.9 WHF the size of the heat spreading in the substrate is 3 to 5 times larger thansubstrate thickness.

0892-FF13-05.3Figure 2. GaN MESFET current-voltage (a) and maximum temperature-voltage (b) characteristics obtained byelectro-thermal simulations for transistor with substrate lengths 50 µm, 100µm, 200 µm and 3 mm for theisothermal boundary condition of 300 K on the substrate bottom. Dash curve on (a) is for the case of theisothermal simulation. For all curves the source - gate bias is zero. Arrow shows the increase of substrate length.On inset to figure (a) you can see schematic cross-section of the considered GaN MESFET. Inset to figure (b)shows the elementary cell of transistor with many gate fingers with marked simulation domain.The dimension of the heat spreading in a substrate increases rapidly as the thermalconductivity of the heat sink becomes equal or less than the thermal conductivity of thesubstrate. In the characteristic case of K = 1 (k 1 = k 2 ) calculations for the case of a point heatsource gives the diameter of the 0.9 WHF through the substrate bottom equal to 19.9L. For thelinear heat source, we have a size of 0.9 WHF through the substrate bottom equal to 12.6L.Hence, for the case of the same thermal conductivities of two layers, the dimension of the heatspreading at substrate bottom is about 10 to 20 times larger than the substrate thickness.A typical field effect transistor have a finite width of the active channel, so thedistribution of the temperature and the heat flow in the real devices would be somethingbetween two considered cases of point and linear heat sources. Hence, we can conclude thatfor simulations without significant distortion of a heat flow in the transistor substrate with aperfect heat sink from the substrate bottom surface (isothermal boundary condition), we need asimulation domain with a substrate length more than substrate thickness.SIMULATION DETAILSAll simulations are performed for the following parameters of the device based on theactual GaN MESFET described in [6]. The doping concentration in the active layer is 3⋅10 17cm -3 ; the thickness of the active layer is 200 nm; the source - drain separation 5 µm; and thegate length 1.5 µm. The n-type GaN active layer is deposited on the top of a 3 µm thick semiinsulating(SI) GaN buffer (a schematic picture of simulated GaN-based MESFET is shown oninset to Fig. 2(a)). Although the transistor described in [6] has a sapphire substrate, in thiswork, we consider the case of a 300 µm thick SiC substrate. SiC has a high thermalconductivity coefficient at room temperature k SiC = 3.3 Wcm -1 K -1 , hence it is a promisingmaterial for GaN transistors substrates. We take k GaN =1.6 Wcm -1 K -1 and k sapph =0.35 Wcm -1 K -1 .The T -0.5 temperature dependence for thermal conductivity of GaN and T -1 for SiC andsapphire has been taken into account in the presented simulations. Boundary conditions on

0892-FF13-05.4Figure 3. Dependence of the maximumtemperature on the substrate length for thecase of isothermal (R th = 0.0 K cm 2 /W) andconvective (R th = 0.1 K cm 2 /W) boundaryconditions on the substrate bottom. Ambienttemperature is 300 K. The source-drain biasis 50 V and the source-gate bias is zero.Figure 4. Electro-thermal simulations of theambient temperature effect on outputcharacteristics for GaN MESFET on SiCsubstrate with 3 mm length. Thermalresistance of 0.1 Kcm 2 /W lumped to substratebottom. Set of different substrate bottomtemperatures is from 0 o C to 500 o C with100 o C step. Dot curves correspond to thecase of 300 K. Source-gate bias is zero.Figure 5. Upper curve, marked AB, is forisothermal simulation (T = 300 K) for GaNMESFET with beginning of avalanchebreakdown at drain. Lower curve, markedTB, is for electro-thermal simulation withthermal resistance of 0.1 K cm 2 /W lumped tosubstrate bottom and for 1 mm SiC substratelength. Source-gate bias is zero for bothcases. Dot curve shows respective maximumtemperature-voltage characteristic for electrothermalsimulation.boundaries without contacts (particularly lateral boundaries) are of reflective type that givesthe zero normal components of electric field, electrons and holes current, and heat flow. That iswhy we can consider simulated one-gate domain as half of elementary cell of transistor withmany gate fingers (see inset to Fig. 2b). Other details about used boundary conditions aredescribed elsewhere (see TCAD DESSIS manual and [7]). We assume the Schottky barrierpotential height to be 1 eV. For the low-field mobility dependence on temperature and dopingconcentration, a model [8] specific for GaN has been used. The new modified transferred-

0892-FF13-05.5electron (MTE) model that is able to replicate the specific electric field dependence of the driftvelocity of electrons in GaN has been used [9]. Saturation velocity 1.91 x 10 7 cm/s for 300 Ktemperature was extracted from the Monte-Carlo simulation results [10]. The lineardependence of saturation velocity on temperature was considered with negative temperaturecoefficient -6.33 x 10 3 cm s -1 K -1 , that was obtained by fitting the data from the Monte Carlosimulations [11].DISCUSSIONSimulations for different substrate lengths in the case of an isothermal boundarycondition on substrate bottom surface are shown on Fig. 2. For the case of electro-thermalsimulations of transistor on SiC substrate with 50 µm substrate length, we can see significantdegradation of output characteristics with pronounced NDC region and with relatively hightemperature of the hot spot. Degradation of output characteristics in the case of 3 mm substratelength is less pronounced. Obtained results are in qualitative agreement with results publishedin Ref. [12,13]. Dash curve on Fig. 2a presents isothermal simulations without NDC.The top curve on Fig. 3 explains how a non-ideal heat sink influences hot spottemperature. In the case of a convective boundary condition on substrate bottom, with typicalvalue of package thermal resistance R th = 0.1 Kcm 2 /W the saturation value of a maximumtemperature of hot spot for zero source-gate bias and 50 volts source-drain bias is 190 o C,which is only 40 o C higher than one for the case of an ideal heat sink. Note that temperaturesaturation occurs at 3 mm substrate length that is order of magnitude larger than for the case ofan isothermal boundary condition.Simulations for the case of sapphire substrate show that the degradation of outputcharacteristics and temperature of the hot spot is significantly larger than for the case of SiCsubstrate. For example, for the case of zero source-gate bias and for 50 volts source-drain bias,the temperature of the hot spot in the case of sapphire substrate is 250 o C, which is 100 o C largerthan in the case of SiC substrate.On Fig. 4 simulation of temperature effect is presented. Simulations indicates ~ 40%degradation in the saturation current with temperature increase from room temperature to250 o C that is in good agreement with experimental data [7].In addition, we have studied breakdown in GaN-based field-effect transistors. In FETs,the most common type of breakdown is avalanche breakdown under the drain-side edge of thegate. However, in modern devices an advanced gate-design solutions, such as a recessed gate,passivation, and a gate with a field plate, are used to increase gate breakdown voltage. Inaddition, GaN-based metal-insulator-semiconductor field-effect transistor (MISFET) ispromising devices with significantly decreased gate leakage current. Hence, anybody cansuggest that the fundamental limit on field-effect transistor performance is the avalanchebreakdown at drain. Moreover, our simulations show that, this take place for Si and GaAsbasedFETs. However, in GaN, that is wide band gap semiconductor, breakdown electric fieldorder of magnitude higher than in Si and GaAs. Hence, avalanche drain breakdown in GaNFETs should occur at much more higher voltages in comparison with Si and GaAscounterparts. Here question arises: can thermal breakdown in GaN-based FETs occur beforedevelopment of avalanche at drain?Upper curve on Fig. 5 shows isothermal simulations with beginning of avalanchebreakdown (AB) at drain about 400 V source-drain bias. Lower curve shows electro-thermal

0892-FF13-05.6simulation with beginning of thermal breakdown (TB) at about 200 V source-drain bias. Inmore harsh thermal conditions, thermal breakdown voltage can be even less [14]. Hence, wecan conclude that the temperature of hot spot in active channel of GaN FETs can rise up tointrinsic GaN temperature estimated by Neudeck et al. [15]. At the same time, due to the highvalue of GaN breakdown field, the device can be far from the beginning of avalanche or Zenerbreakdown. We can suppose that in such conditions, thermal generation of carriers can lead tothermal instabilities or even to development of irreversible thermal breakdown. Note that oneof the most promising applications of GaN-based devices is high temperature electronics forambient temperatures beyond 300 o C [15]. In such harsh conditions of operation, thermalbreakdown can be the dominant fault mechanism for GaN-based FETs.CONCLUSIONSThe electro-thermal simulations performed for the GaN MESFET with many gates andwith thermo-insulating passivation show that the gate-to-gate pitch should be larger than thesubstrate thickness to obtain a minimum hot spot temperature. We conclude that the negativedifferential conductivity on output characteristics resulted from a degradation of electronmobility associated with an increase of the hot spot temperature in the transistor channel.Simulation of the ambient temperature effect indicates significant degradation in the saturationcurrent with temperature increase. We suppose that in GaN-based FETs thermal breakdowncan be dominant fault mechanism.ACKNOWLEDGMENTSThe work at UCR has been supported in part by the grants to AAB from the Office ofNaval Research (ONR), National Science Foundation (NSF) and US CRDF. The authorsacknowledge SYNOPSYS Company for donating a new release of DESSIS software (formerISE TCAD) to carry out the simulations described in this work.REFERENCES1. M.A. Khan et al., Appl. Phys. Lett. 62, 1786 (1993); 63, 1214 (1993).2. Y.-F. Wu, IEEE Electron Device Lett. 25, 117 (2004).3. A.A. Balandin et al., IEEE Electron Device Lett. 19, 475 (1998).4. S. Yoshida et al., Solid-State Electron 47, 589 (2003).5. N. Rinaldi, IEEE Trans. Electron Device 49, 679 (2002).6. S.C. Binari et al., Solid-State Electron 41, 1549 (1997).7. W.L. Liu et al., MRS Internet J. Nitride Semicond. Res. 9, 7 (2004).8. T.T. Mnatsakanov et al., Solid-State Electron. 47, 111 (2003).9. V.O. Turin, Solid-State Electron. 49, 1678 (2005).10. M. Farahmand et al., IEEE Trans. Electron Devices, 48, 535 (2001).11. U.V. Bhapkar and M.S. Shur, J. Appl. Phys. 82, 1649 (1997).12. M. Kuball et al., phys. stat. sol. (a) 202, 824 (2005).13. S. Nuttinck et al., IEEE Trans. Microwave Theory Tech. 51, 2445 (2003).14. V.O. Turin and A.A. Balandin, Electron. Lett. 40, 81 (2004).15. P.G. Neudeck, R.S. Okojie, and L.-Y. Chen, Proc. IEEE, 90, 1065 (2002).