Accurate Bit-Error-Rate Estimation for Efficient High Speed I/O Testing

Accurate Bit-Error-Rate Estimation for Efficient High
Speed I/O Testing
Dongwoo Hong and Kwang-Ting (Tim) Cheng
Department of Electrical and Computer Engineering
University of California,
Santa Barbara, CA 93106, USA
besthdw@ece.ucsb.edu, timcheng@ece.ucsb.edu
Abstract— We introduce a Bit-Error-Rate (BER) estimation
technique for high-speed serial links, which utilizes the jitter
spectral information extracted from the transmitted data and
some key characteristics of the clock and data recovery (CDR)
circuit in the receiver. In addition to offering insight into both
the behavior of the CDR loop and the contribution of the jitter
to the BER, the estimation technique can be used to accelerate
the jitter tolerance test by eliminating the conventional BER
measurement process. We will discuss two different versions of
the estimation technique: one for use with linear CDR circuits
and the other for non-linear CDR circuits. Experimental results
comparing the estimated BER and the measured BER
demonstrate the high accuracy of the proposed technique.
I. INTRODUCTION
Bit-Error-Rate (BER) and jitter have been widely used as
measurements to ensure the performance of high-speed
communication systems. With the increasing number of I/O
pins and greater data rates, testing high speed interfaces has
posed significant challenges in terms of test cost and quality.
Particularly, BER measurement down to the 10 -12 level, which
is required to ensure system reliability for most multi-gigabit
communication standards, is test-time prohibitive [1].
In this paper, we propose a method for estimating the BER
using the following two sets of parameters: (1) the jitter
spectral information, extracted from the signal at the input of
the receiver. The information includes the root-mean-square
(rms) value of the random jitter (RJ) and the deterministic
jitter (DJ) characteristics, such as frequencies and amplitudes
of the periodic jitter (PJ) components. (2) The jitter transfer
characteristics for both a linear CDR circuit and a non-linear
CDR circuit.
In the next section, we first summarize the jitter transfer
characteristics of the CDR circuits. Section Ⅲ describes the
BER estimation technique for the CDR circuits when both PJ
and RJ are present in the data. Section Ⅳ presents the
experimental results for the validation of the proposed
technique. Section Ⅴ concludes the paper.
θ i
Phase
Detector
Charge
Pump
Figure 1. Block diagram of a CDR circuit
II. JITTER TRANSFER CHARATERISTICS
A CDR circuit is commonly implemented using the
architecture of a Phase-Locked Loop (PLL). The basic block
diagram of the CDR circuit under such architecture is shown
in Fig. 1. It consists of a phase detector (PD), a charge pump,
a loop filter and a voltage-controlled oscillator (VCO). The
only difference between a linear and a non-linear CDR circuit
is the PD operation. The non-linear PD (a.k.a. bang-bang
(BB) PD) discards the magnitude information of the phase
error and only measures its polarity while a linear PD’s
output magnitude is proportional to the phase error.
I P, avg
I CP
-θ th
θ th Phase error
-I CP
Linear
Non-linear
(BB)
Figure 2. Average phase dectector gain curves
I P
R
C
K VCO /s
VCO
θ o

Fig. 2 shows the characteristics of both the linear PD and
the BB PD to the input jitter (i.e. phase error). The BB PD
operates in the linear region for a small phase error whereas
operates in the non-linear region for a large phase error. The
average gain for the BB PD is smoothed by the metastability
of flipflops in the PD and random jitter in the input data and
the VCO, and, thus, has a finite slope across a narrow range
of the phase error [2].
θ in
θ in,p
θ
t 0 t 1
At a low jitter frequency, both PDs can track the input
jitter closely, and thus no bit errors will occur. However, if
the input jitter varies rapidly, the CDR circuits may not track
the jitter, and some errors will occur. The responses to the
high frequency jitters may be different from one another.
θ out : Linear
Δθ max
θ out : Non-linear
A. Linear CDR Circuit
For the linear CDR circuit, if the jitter frequency is higher
than the bandwidth of the CDR circuit, the recovered clock
jitter has a certain delay and smaller amplitude compared to
the injected one as shown in Fig. 3 [3].
If we assume the input jitter as θ
in
= θin,p
⋅sin(
ωθt)
, the
recovered clock jitter can be represented as
θout
= θin,p
θ
⋅ H(jω)
⋅sin(
ω (t − τ(
ω)))
, where H( jω)
is the close loop transfer function of the linear
CDR circuit. The time-delay, τ, introduced into the recovered
clock jitter depends on the phase response of the CDR circuit,
and is represented as follows [4]:
d
τ ( ω)
= − { ∠H( jω)}
.
dω
Therefore, the phase error which is the difference between the
input jitter and the recovered clock jitter will be [3]:
Δθ=
θ
2
,p
in
2
⋅( 1+
H(jω)
) −2⋅
H(jω)
⋅θin,p
cos( ωθ
⋅τ(
ω))
⋅sin(
ωθt
+ θ1)
(1)
where tanθ
1
= H(jω)
⋅sin(
ωθ τ(
ω))/(1
− H(jω)
⋅cos(
ωθτ(
ω)))
.
B. Non-linear CDR Circuit
For the non-linear CDR circuit, large and fast variation of
the input jitter results in slewing because the available current
beyond the linear region (i.e. I CP ) is constant [2]. Fig. 3
illustrates an example of the slewing and the maximum phase
error (i.e. Δθ max ) occurring at t 1 . The phase error at t 0 is used to
approximate the maximum phase error because it is close
enough to Δθ max and much simpler to calculate. If θ out slews
for most of the period, t 0 is approximately equal to T θ /4 (T θ =
2π/ω θ ). Denoting the input jitter as θin,p
⋅sin(
ωθ t + δ)
, the
maximum phase error could be approximated as:
2 2 2 2
4ωθθin , p
− π K
Δθ
max
≈ Δθ(t
0
) ==
2ωθ
The details of the derivation can be found in [2].
2
I
2
VCO P
R
2
(2)
Figure 3. Relationship between input jitter and recovered clock jitter
III. BER ESTIMATION
In the last section, we have shown the jitter transfer
characteristics of the CDR loops with respect to the PJ. In the
following, we discuss the BER estimation technique when
both PJ and RJ components are present in the data.
A. Linear CDR Circuit
Since the CDR circuit can track only the low frequency
components of the jitter, the rapidly varying RJ cannot be
tracked. Fig. 4 shows the jitter in the transmitted data (i.e. total
jitter = PJ + RJ), and the recovered clock jitter produced by
the CDR circuit (from simulation). As expected, only PJ is
tracked with a certain time delay and attenuated amplitude.
Therefore, the overall phase error becomes the summation of
the phase error due to PJ (i.e. Equation (1)) and the RJ. Errors
occur when the phase error exceeds plus or minus half of a
Unit Interval T/2 (where T is denoted as one Unit Interval
(UI)). That is, errors occur when
θ
in
2
,p
2
2
T
⋅( 1+
H(jω)
) −2⋅
H(jω)
⋅θin,p
cos( ωθ
⋅τ(
ω))
⋅sin(
ωθt
+θ1)
+ n(t) ≥
2
where n(t) is the RJ.
One popular approach to the BER estimation is the use of
the double-delta model [5]. The model approximates the DJ as
two Dirac delta functions and convolves them with the RJ. If
we assume that the peak-to-peak magnitude of DJ as 2*A DJ
and the rms value of RJ as σ
RJ
, the BER can be estimated as:
T/ 2−
ADJ
BER = 2⋅ρT
⋅Q(
) . (3)
σRJ
The Q-function is used to calculate the probability that the
Gaussian distribution is larger than any given value x, and is
defined as:
1 1 2
−x
/ 2
Q (x) = [
] e
2
( 1− a)x + a x + b 2π
where a=1/π and b=2π [6]. In addition, the BER is linearly
proportional to the transition density ( ρ ) of the data [5].
T

Jitter (seconds)
Recovered clock jitter
– only PJ
Recovered clock jitter
– PJ+RJ
Figure 4. Input jitter and recovered clock jitter for linear CDR circuit
In our case, PJ and RJ are considered for the BER
estimation. Since the PJ distribution cannot be properly
modeled as two Dirac delta functions, we make some
modifications to Equation (3). We use two new variables, the
effective mean shifting (A eff ) and the effective rms value
( σ eff ), to replace A DJ and σ RJ . Then, A eff and σ eff , to be
applied to (3), will be:
A
2
2
2
eff
= θin,p
⋅(1
+ H(jω)
) − 2⋅
H(jω)
⋅θin,p
cos( ωθ
⋅τ(
ω))
−0.9
⋅ 2
2
eff = 1+
0.84 )
2
RJ
σ ( ⋅ σ .
Number of samples
⋅σ
The details of the derivation of these two new variables, which
are based on the ratio of the amount of RJ to the amount of PJ,
can be found in [3].
B. Non-linear CDR Circuit
If the RJ is injected with PJ for the non-linear CDR
circuit, the recovered clock jitter is affected by the RJ. When
only PJ is present in the data, the recovered clock jitter
increases monotonically during the first half of the jitter
period as illustrated in Fig. 3. The peak-to-peak magnitude of
the recovered clock jitter decreases linearly as the frequency
of the PJ increases, which results in a -20dB/dec slope in the
slewing region of the CDR’s jitter transfer function. However,
in the presence of both PJ and RJ, the recovered clock jitter
no longer increases monotonically. The peak-to-peak
magnitude of the recovered clock jitter is less than that of the
case in which only PJ is present, as shown in Fig. 5.
Therefore, the magnitude of the recovered clock jitter no
longer decreases linearly in proportion to the increase in the
jitter frequency. This results in a different slope in the
slewing region for different PJ to RJ ratios. Because it is very
difficult, if not impossible, to derive an analytical relationship
between the slope variation and the jitter magnitude, we
empirically derive their relationship from the simulation
results as follows [7]:
σ PJ 0.
1
−14.
5 ⋅ ( ) − 5.
5 + 0.
5 ⋅ log2
( )
σ PJ + σ RJ
σ RJ
Slope =
, if Slope > -18.5
− 18.
5
, otherwise
RJ
Figure 5. Input jitter and recovered clock jitter for non-linear CDR circuit
When only PJ is present in the data, the phase error
distribution can be approximated using a Uniform distribution
with a peak-to-peak value of 2*Δθ max (Δθ max can be
calculated from Equation (2)). This approximation correctly
reflects the bounded property of the phase error distribution
and is analytically convenient for BER estimation. When both
RJ and PJ are present, the phase error distribution can be
approximated by the convolution of a Uniform and a
Gaussian distribution because most of RJ components are not
tracked by the CDR circuit. However, since the addition of
the RJ changes the jitter transfer function of the CDR circuit,
we need to modify Equation (2) for calculating the magnitude
of the Uniform distribution. To incorporate an increase in
jitter magnitude due to the RJ, we simply substitute θ in,p in
Equation (2) by θ in,TJ (θ in,TJ = θ in,p + σ RJ ). The total jitter
magnitude is important for the non-linear CDR circuit
because the jitter transfer function highly depends on the jitter
magnitude. For the slope variation, we introduce a gain
compensating factor that takes into account the gain
difference in the slewing region, which is introduced by the
addition of the RJ:
Slope + 20
⎛ w ⎞ 20
⎜
θ
K slope (w θ ) = ⎟
⎝ w −3dB
⎠
As a result, the maximum phase error becomes
Δθ
max_ TJ
=
4w
2
θ
θ
2
in,TJ
2w
θ
− π
K
2
slope
K
2 2
VCO
(w
I PR
)
Knowing the magnitude of the Uniform distribution (i.e.
Δθ max_TJ ) and the rms value of the Gaussian distribution (i.e.
σ RJ ), the probability density function (PDF) of the phase error
can be calculated by the convolution of these two
distributions. In turn, the BER, which represents the
probability that the phase error exceeds half of the UI, would
be [7]:
BER=1−
1
2A
TJ
1
⋅
2πσ
RJ
⎡ 05+ . A 2 2
−t
/ 2σ
( 05+ . ATJ)
+
⎢⎣ ∫ e dt σ
−∞
0. 5−A
2 2
2 2
TJ −t
/ 2σRJ 2 −(
05− . ATJ)
/ 2σRJ
−( 0.
5−A
−
⎤
TJ)
∫ e dt σ
−∞
RJe
(5)
⎥⎦
, where A TJ is the maximum phase error in UI (i.e. A TJ =
Δθ max_TJ /(2π))
θ
2 2
TJ RJ 2 −(
05+ . ATJ)
/ 2σRJ
RJe
2
(4)

1.0E-07
1.0E-08
Mea. BER
Est. BER
1.0E-03
1.0E-04
BER
1.0E-09
1.0E-10
1.0E-11
BER
1.0E-05
1.0E-06
1.0E-12
0.01 0.1 1 10 100
PJ Freq (MHz)
1.0E-07
4MHz 10MHz 15MHz 20MHz
PJ Freq.
Figure 6. BER measurement results for linear CDR circuit
IV. EXPERIMENTAL RESULTS
To validate the proposed estimation techniques, we
conducted hardware measurements for the linear CDR circuit
and simulations for the non-linear CDR circuit.
A. Linear CDR circuit
We conducted the experiments using the MAXIM 3873A
CDR circuit, which operates at 2.488Gbps with 2MHz
bandwidth and less than 0.1 dB jitter peaking [8]. We used
Synthesys Research’s BERTScope for jitter injection and for
BER measurement. We injected PJ at 8 different frequencies,
ranging from 50KHz to 80MHz with amplitude of 0.45UI.
We fixed the rms value of RJ at 0.036UI, and swept the PJ’s
frequency. In the low frequency range, the expected BER is
too low to be measured (i.e. less than 10 -12 ) within a
reasonable amount of time due to the CDR circuit’s tracking
ability. Thus, if no error is captured within a time limit (in our
experiment, the limit was set to 7 minutes≈ 10 12 b/(2.5Gb/s)),
the BER is represented as 10 -12 as in Fig. 6. For these cases,
the estimated BER is indeed much lower than 10 -12 . The
results clearly show that the measured BER and the estimated
BER match very well in almost all cases. When the measured
BER level is around 10 -12 , the difference is larger than those
of other cases. We suspect that this is because the injected RJ
does not have the unbounded tails in real applications – thus
the Gaussian model for the RJ may not accurate in the very
low probability region.
B. Non-inear CDR circuit
We conducted MATLAB simulations to validate the BER
estimation technique for the non-linear CDR circuit. The
behavioral model of the CDR circuit operating at 10 Gb/s was
used for the validation. Due to the limited simulation time,
we could only afford to conduct simulations down to the 10 -7
BER level. For each case, we conducted the simulation to the
point at which 1,000 errors were captured. The rms value of
RJ was chosen at 0.1UI and the peak-to-peak PJ magnitude
was chosen at 0.4UI. We injected four different PJ
frequencies for the simulation. Fig. 7 shows the simulation
results.
Est. BER w/o comp. Est. BER w/ comp. Sim. BER
Figure 7. BER simulation results for non-linear CDR circuit
The graph contains the simulated BER and two estimated
BERs: one is the estimated BER without compensating the
jitter transfer variations due to the RJ (i.e. Substituting
Equation (2) into Equation (5)) and the other is the estimated
BER with compensation of these effects (i.e. Substituting
Equation (4) into Equation (5)). The simulation results
indicate that the simulated BER and the estimated BER, after
compensating the jitter transfer variations, match pretty well.
V. CONCLUSION
High performance serial communication systems often
require the BER to be at levels of 10 -12 or below. The
excessive testing time for measuring such a low BER is a
major hindrance for cost effective testing. Thus, the industry
demands new testing methods that are both efficient and
accurate to guarantee that products meet the BER specification
at a low test cost. In this paper, we show how the PJ and RJ
affect the recovered clock jitter and the dependency of the
BER on the characteristics of the CDR circuit. We further
propose an analytical technique to estimate the BER. The
experimental results demonstrate the validity of our analysis
and the roles of these parameters in determining the BER.
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