Testing 1 - UCSB SoC Design and Test Lab

© K.-T. Cheng, component.ppt, v1.0 

1 

Outline - Overview 

Overview of IC Testing 

• Types of Testing at IC level 

• IC Production Test Process 

• Burn-in 

• Board, System and Field Testing 

• Costs of Testing 

• The Testing Problems 


2

VLSI Realization Process 

Customer’s need 

Determine requirements 

Write specifications 

Design synthesis and Verification 

Test development 

Fabrication 

Manufacturing test 

*from M. Bushnell/V. Agrawal 

Chips to customer 


3 

Verification vs. Test 

! Verifies correctness of design. 

! Performed by simulation, 

hardware emulation, or formal 

methods. 

! Performed once prior to 

manufacturing. 

! Responsible for quality of 

design. 

! Verifies correctness of manufactured 

hardware. 

! Two-part process: 

– 1. Test generation: software process 

executed once during design 

– 2. Test application: electrical tests applied 

to hardware 

! Test application performed on every 

manufactured device. 

! Responsible for quality of devices. 



4

Errors And Faults 

! Design errors 

– violations of design rules 

– incorrect mapping between different levels of design 

– incomplete or inconsistent specification 

! Fabrication errors - caused by human errors 

– incorrect wiring 

– shorts caused by improper soldering 

! Fabrication defects - caused by imperfect 

manufacturing process 

– mask alignment errors 

– improper doping profiles 


5 

! Physical failures - due to component wear-out 

and/or environmental factors 

– connectors may break due to electronmigration 

or corrosion 

– temperature, humidity and vibrations 

accelerate the aging of components 

– infancy failures 


6

Problems of Ideal Tests 

! Ideal tests detect all defects produced in the 

manufacturing process. 

! Ideal tests pass all functionally good devices. 

! Very large numbers and varieties of possible defects 

need to be tested. 

! Difficult to generate tests for some real defects. Defectoriented 

testing is an open problem. 



7 

Real Tests 

! Based on analyzable fault models, which may 

not map on real defects. 

! Incomplete coverage of modeled faults due to 

high complexity. 

! Some good chips are rejected. The fraction (or 

percentage) of such chips is called the yield loss. 

! Some bad chips pass tests. The fraction (or 

percentage) of bad chips among all passing 

chips is called the defect level. 


8

Testing as Filter Process 

Good chips 

Prob(pass test) = high 

Prob(good) = y 

Fabricated 

chips 

Defective chips 

Prob(bad) = 1- y 

Prob(fail test) = high 

Prob(fail 

test) = low 

Prob(pass test) = low 

Mostly 

good 

chips 

Mostly 

bad 

chips 


9 

Types of Testing - IC Level 

! Characterization - determine the device’s characteristics 

– AC and DC characteristics 

– data will be used for final spec. 

– data can be used to identify area in which processing can 

be helped for increased yield 

– test time is not important 

! Production testing 

– Contact test 

– Burn-in testing 

– Functional testing 

– Parametric testing 


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Production Testing for ICs 

ContactTest 

Burn-In Test 

To screen out assembly related failures. 

To insure that the tester interface is in 

contact with the device. 

To screen out infant mortalities 

Functional Test 

DC Parametric Test 

Steady state tests 

AC Parametric Test 

To ensure that state changes 

occurattherighttime 


11 

DC Parametric Testing 

! Tests are done by Parametric 

Measurement Unit (PMU) 

– Leakage test 

– Threshold V iL &V iH test 

– Output drive current test 

– Power consumption test 

– Output short current test 


12

AC Parametric Testing 

! To ensure that value/state changes occur at the 

right time 

! Some of AC parametric tests are mainly for 

characterization and may not be necessary for 

production test. 

– Test for rise and fall times of an output signal 

– Tests for setup and hold times 

– Tests for time to tri-state 

– Tests for measuring delay times 

» E.g. tests for memory access time 

– Functional at-speed tests (speed sorting) 


13 

Functional Testing for Digital Circuits 

Test 

Vectors 

…. 01 

…. 00 

…. 

…. 01 

True 

Response 

Digital 

Circuit 

Comparator 

…. 

Circuit 

Response 

11…. 10…. 

… 

. 

01…. 


Result 


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Failure rate 

Typical Bathtub Curve of IC’s 

Failure Rate 

Earlyfailure 

period 

Useful-life period 

Wearout 

period 

Cumulative operating time 

~1,000 hours >10years 


15 

Burn-in Testing 

! Correlations have been made between life span at room 

temperature & life span at elevated temperature. 

! Charts of these correlations have been made for each 

technology 

! Put the device in a furnace for a certain length of time at 

an elevated temperature and voltage 

– By applying high voltage to the IC’s pins, burn-in 

accelerates the time-to-failure of oxide defects (weak 

oxide, pin holes, uneven layer growth, etc) typically 

found in MOS devices 

– High temperature accelerates these and other defects, 

such as ionic contamination and silicon defects 


16

High-Voltage Stress Tests 

! Mainly for memory chips 

! Cycling through all addresses using selected memory 

data patterns for several seconds, both logic high and 

logic low, with 7.5V forcing function being applied 

(for a 5V rated part) 

! IC memory suppliers have used this test in lieu of 

dynamic burn-in as a means to uncover oxide defects 

in MOS IC’s 

! Some use it in conjunction with either dynamic burnin 

or TDBI 


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Test During Burn-In 

! The most comprehensive burn-in technique 

! Procedure: 

– Devices are operated at 125 ° C and elevated voltage (7-7.5V) for 

an extended period of time, while all DUT’s are subjected to 

functional testing using a complex test 

– The DUT’s are operated for a short duration at a lower temp. 

70 ° C and voltage (5.5V) during which parametric testing is 

performed 

– Repeat the above two steps for 4-8 hours or longer 

! Used primarily for DRAM 

– But not for large memories due to the long electrical test times 

– Not appropriate for EPROM, microprocessors and other VLSI 

devices 


18

Board Level Testing 

! Shorts testing 

! In-circuit testing 

– Check devices already mounted on a board 

– An external tester applies patterns directly to the 

inputs of the device & observe the outputs 

– The tester must be capable of electronically isolating 

the IC under test from the board environment 

! Functional Board Testing 


19 

System Testing 

! Final test in the manufacturing 

process 

! Checking the right assembly of 

components such as boards, 

backplanes, cables and 

peripherals 

! It also involves checking of 

component interactions and 

HW/SW functionality 

! Very long test times required 


20

Field Testing 

! Necessary for commissioning and faultfinding 

the system as a whole in a fieldservice 

environment 

! Both analog and digital test equipment is 

needed, issues of 

– Portability 

– Ease of use 

– Range of functions 


21 

Testing Costs are Composed of: 

! Test equipment costs 

– Analog & digital signal and measuring instrumentation 

– Test head (pin electronics, drivers and cables) 

– Test controller (computer & storage) 

! Test development costs 

– Test planning, test program development and 

debugging 

! Testing-time costs 

– time using the equipment to support testing 

! Test personnel costs 

– training 

– working time 


22

Cost Of Testing - The Rule of Tens 

1000 

Cost 

Per 

Fault 

(Dollars) 

100 

10 

1 

5.0 

50 

500 

0.5 

IC 


Board 


System 


Warranty 

Repair 


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Testing 1 - UCSB SoC Design and Test Lab

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