Challenges for Future Interconnection Networks ... - Hot Interconnects

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Introduction • Focus: Challenges facing architects in designing interconnects for chip multiprocessors over next decade • Chip Multiprocessors ‣ 10s to 100s of low power processors, specialized engines ‣ High Throughput processing ‣ Tiled organization: Tile is processor, cache, specialized engine, … GP/SP: General (Special) Purpose compute engines R: Router GP GP GP GP SP R R R GP GP GP SP R R R R GP GP GP GP SP R R R R R GP GP GP GP R R R R 2 August 24, 2006 Hot Interconnects 2006 Panel
On-chip Interconnects How different compared to off-chip counterpart ? SOLUTIONS SAME DIFFERENT 3 August 24, 2006 SAME Routing algos, Flow control, Partitioning, Steal … Latency Challenging reduction, … PROBLEMS DIFFERENT Identify and Variation Steal tolerant interconnects, … More 2D Challenging embedding, Wiring, Power, New metrics Hot Interconnects 2006 Panel
Page 1: Challenges for Future Interconnecti
Page 5 and 6: 2D Embedding: Topological Adjacency
Page 7 and 8: Parametric Variation Tolerance* Wit
Page 9: On Chip Networks Takeaways • Arch

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