Challenges for Future Interconnection Networks - Hot Interconnects
Challenges for Future Interconnection Networks - Hot Interconnects
Challenges for Future Interconnection Networks - Hot Interconnects
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<strong>Challenges</strong> <strong>for</strong> <strong>Future</strong> <strong>Interconnection</strong><br />
<strong>Networks</strong><br />
William J. Dally<br />
Computer Systems Laboratory<br />
Stan<strong>for</strong>d University<br />
<strong>Hot</strong> <strong>Interconnects</strong> Panel<br />
August 24, 2006<br />
<strong>Hot</strong>-I: 1 Aug 24, 2006
<strong>Interconnection</strong> <strong>Networks</strong> are Critical<br />
• <strong>Interconnection</strong> networks are becoming the<br />
dominant component of future systems<br />
– Bulk of power is in data movement<br />
– Latency of critical paths dominated by interconnect<br />
– Bandwidth limited by interconnect<br />
– Arithmetic is (almost) free – data/instruction movement<br />
is what matters<br />
• But today most interconnects are ad-hoc<br />
– Small number of terminals (2-8)<br />
– Connected with bus, crossbar, ring<br />
– Little analysis or optimization – until bottleneck<br />
discovered<br />
<strong>Hot</strong>-I: 2 Aug 24, 2006
Technology Trends…<br />
bandwidth per router node (Gb/s)<br />
10000<br />
BlackWidow<br />
1000<br />
100<br />
10<br />
1<br />
0.1<br />
1985 1990 1995 2000 2005 2010<br />
Torus Routing Chip<br />
Intel iPSC/2<br />
J-Machine<br />
CM-5<br />
Intel Paragon XP<br />
Cray T3D<br />
MIT Alewife<br />
IBM Vulcan<br />
Cray T3E<br />
SGI Origin 2000<br />
AlphaServer GS320<br />
IBM SP Switch2<br />
Quadrics QsNet<br />
Cray X1<br />
Velio 3003<br />
IBM HPS<br />
SGI Altix 3000<br />
Cray XT3<br />
YARC<br />
year<br />
<strong>Hot</strong>-I: 3 Aug 24, 2006
Today – We can build very capable systemwide<br />
networks<br />
<strong>Hot</strong>-I: 4 Aug 24, 2006
Many Recent Advances<br />
• High-radix networks<br />
• Global adaptive routing<br />
• Tools <strong>for</strong> topology optimization<br />
<strong>Hot</strong>-I: 5 Aug 24, 2006
To find out more about networks, read<br />
<strong>Hot</strong>-I: 6 Aug 24, 2006
But much of the future is on-chip<br />
(CMP, SoC, Operand)<br />
2006 2007.5 2009<br />
2010.5 2012<br />
<strong>Hot</strong>-I: 7 2013.5<br />
Aug<br />
2015<br />
24, 2006
On-Chip <strong>Networks</strong> are Fundamentally Different<br />
• Different cost model<br />
– Wires plentiful, no pin constraints<br />
– Buffers expensive (consume die area)<br />
– Slow signal propagation<br />
• Different usage patterns<br />
– Particularly <strong>for</strong> SoCs<br />
• Significant isochronous traffic<br />
• Hard RT constraints<br />
• Different design problems<br />
– Floorplans<br />
– Energy-efficient transmission circuits<br />
<strong>Hot</strong>-I: 8 Aug 24, 2006
Large room <strong>for</strong> improvement over ‘obvious’<br />
approaches<br />
1.5<br />
Network Energy × Completion Time<br />
(normalized to Torus network)<br />
1.0<br />
0.5<br />
0.0<br />
Concentrated<br />
Mesh<br />
(Replicated)<br />
Source: Balfour et al. ICS-06<br />
Torus Fat-Tree Fat-Tree with<br />
Taper<br />
Mesh<br />
(Replicated)<br />
<strong>Hot</strong>-I: 9 Aug 24, 2006
<strong>Challenges</strong> and Directions<br />
• Prototype to get real data on NoC cost and per<strong>for</strong>mance<br />
• Topology and flow-control to exploit plentiful bandwidth to<br />
save buffers and to support real-time and isochronous<br />
traffic<br />
• System-level design of distributed processor/storage<br />
hierarchy/network (NIC overhead often dominates)<br />
• Power and reliability not overwhelming issues – but we need<br />
to think of a network as a communication system E b /N 0<br />
• Get people to treat interconnect design as a first-class<br />
endeavor (not an afterthought)<br />
<strong>Hot</strong>-I: 10 Aug 24, 2006
Summary/Rebuttal<br />
• DK – Software needed to manage multi-core<br />
systems (data placement)<br />
• DA – High radix is good<br />
• JJ – Learn to live in “flatland” where network<br />
provides fault tolerance<br />
• DJ – Link-level retry is good (RR).<br />
Strong scaling = fine granularity<br />
• SK – Real on-chip networks<br />
• BD – On chip networks are a new frontier – we need<br />
to get our hands dirty with them<br />
<strong>Hot</strong>-I: 11 Aug 24, 2006
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