Verilog 2 - Brown University

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Level sensitive latch (D-Latch) • The <strong>Verilog</strong> implementation of a D-latch is an always block that makes a nonblocking assignment (“
Edge-triggered storage element (D-FF) • The @ symbol is used to specify an event control. • Statements can be executed on changes in signal value or at a positive (posedge) or negative (negedge) transition of the signal. • In general, edge-triggered storage elements are preferred to levelsensitive storage elements because of simpler timing requirements • The 1-bit edge-triggered storage elements provided by FPGA vendors are DFFs because of their simplicity and speed. [Thornton & Reese] S. Reda EN164 Sp ‘11 19
Page 1 and 2: EN164: Design of Computing Systems
Page 3 and 4: Operator types in dataflow expressi
Page 5 and 6: Difference between HLL and Verilog
Page 7 and 8: Example of a dataflow 4-bit adder [
Page 9 and 10: Data types • A reg is a Verilog v
Page 11 and 12: initial statements • An initial
Page 13 and 14: Sensitivity list of events • An e
Page 15 and 16: always statements • Because of t
Page 17: Example: Mux4x1 module mux4x1(out,

Verilog 2 - Brown University

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