Pin Assignment & Analysis Using the Quartus II Software

Pin Assignment & Analysis Using the Quartus II Software Altera Corporation
Design Flow without Design Files
During the early stages of development of an FPGA device, board layout engineers may
request preliminary or final pin-outs. With the Assignment Editor, tool command
langauge (Tcl) scripting, or by directly editing the the complier settings file (.csf),
designers can create pin related assignments like locations and I/O standards for the
FPGA design. The Start I/O Assignment Analysis command checks on the legality of
these assignments.
Figure 1. Assigning & Analyzing Pin-outs without Design Files
2
Quartus II project (.quartus)
Create pin-related assignments
.csf, .esf
Start I/O assignment analysis
Report file generated
Modify and correct illegal
assignments found in report file
To assign and analyze pin-outs using the I/O Assignment Analysis command without
design files:
1. Create a Quartus II project and select the target device.
2. Make pin assignments. Because there are no design files, pin-related assignments
(I/O standards, toggle rate, current strength, etc.) can be made to reserved pins
using the Assignment Editor or with the Tcl scripting interface. See the Creating
I/O Assignments section of this document.
3. Run the Start I/O Assignment Analysis command and view the report file.
4. Correct any errors reported by the I/O assignment analysis and re-run the
analysis.