Pin Assignment & Analysis Using the Quartus II Software

Pin Assignment & Analysis Using the Quartus II Software Altera Corporation
Figure 3. Assigning & Analyzing Pin-outs with Design Files
4
Quartus II project (.quartus)
Create pin-related assignments
.csf, .esf
Analysis and synthesis
Mapped netlist
Start I/O assignment analysis
Report file generated
Back annotate I/O assignment
analysis pin placements
Design files .edf, .vqm, .v, .vhd, .bdf
Modify and correct illegal
assignments found in report file
To assign and analyze pin-outs using the Start I/O Assignment Analysis command with
design files:
1. Create a Quartus II project and design files.
2. Create pin-related assignments with the Assignment Editor or the Tcl interface. Pin
related assignments include I/O standards, toggle rate, current strength, termination
type, etc. Pin location assignments can also be created by dragging and dropping pins
from the node finder to the floorplan editor.
3. Analyze and synthesize the design to generate the internal mapped netlist.