Advanced hardware fundamentals - Nuno Alves

System example• Our design has a micro-processor, aROM and a RAM• All three components have eightdata signals, D0 through D7.• The microprocessor has 16 addresslines, A0 through A15, so it canaddress 64k of memory (2 16 > 64k).• The ROM and the RAM each have32 K and thus have 15 address lineseach, A0 through A14.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

System must be clocked• Some kind of clock circuit isattached to the clock signals on themicroprocessor.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Memory space division• From the microprocessor's point ofview, there are no ROM and RAMchips.• There is just a 64 K address space.• We can perform the followingdivision:ROMRAMLow Address0x00000000-0000-0000-00000x80001000-0000-0000-0000High Address0x7fff0111-1111-1111-11110xffff1111-1111-1111-1111CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Memory space divisionROMRAMLow Address0x00000000-0000-0000-00000x80001000-0000-0000-0000High Address0x7fff0111-1111-1111-11110xffff1111-1111-1111-1111• In the ROM, the highest-order addresssignal (A15) is 0; whereas RAM A15 is 1.• We can use the A15 signal to decidewhich of the two chips (ROM or RAM)• A15 is attached to the chip enable (CE/)signal on the ROM, enabling it wheneverA15 is 0.• A15 signal is inverted and then attachedto the chip enable signal on the RAMCPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Memory mapping• Some additional devices must be connected to themicroprocessor data can be exchanged between them.• The microprocessor and these devices are connected using theaddress and data bus.• These devices use an address range that is not used by any of thememory parts.• For example, the microprocessor may use the bus address(0x80000 to 0x800ff) to access the network chip.• This is known as memory mapping, and its up the hardwareengineer to design the proper assertions.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Additional devices on themicroprocessor bus• Some microprocessors allow two address spaces: a memoryaddress space and an I/O address space.• A microprocessor that supports I/O address space will havesome extra pins, which specifies which address space is currentlybeing addressed.• The most common implementation requires a single pin: LOWfor the memory address space and HIGH for the I/O addressspace.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Microprocessors with I/O addressspace• Microprocessors that support an I/O memory space have extraassembly language instructions for doing that.• The MOVE instruction reads from or writes to memory;• The IN and OUT instructions, access devices in the I/O addressspace.• C contain functions to read to and write from devices in the I/Oaddress space• For example inport, outport, inp, outp, inbyte, inword, inpw.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Code sample calls an I/O addressspace#define NETWORK_CHIP_STATUS (0x80000)#define NETWORK_CHIP_CONTROL (0x80001)(...)void vFunction (){BYTE byStatus;(...)This memoryaddress containsthe network chipstatus.// Read the status from the network chip.byStatus = inp (NETWORK_CHIP_STATUS);(...)// Write a control byte to the network chip.outp (NETWORK_CHIP_CONTROL, 0x23);(...)}CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of EngineeringThis C instruction(inp) will collectinformation from aparticular addressin the I/O addressspace.

Example of a system with I/O addressspace• DV1 is a device in the I/Oaddress space• DV2 is a device in the memoryaddress space• DV1 is enabled when A19 andI/O are both high• DV2 is enabled when A19 ishigh and I/O is low.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of EngineeringBus handshaking

Bus handshaking• Both RAM and ROM have different timing requirements.• The data is valid on the bus if:1.The address lines are stable for a certain period of time.2.The read enable and chip enable lines are asserted forsome period of time.• This period of signal stability is called a bus cycle.• Microprocessor must conform to timing requirements of othercomponents too. The various mechanisms are called bushandshaking.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Handshaking method #1: nohandshake• With no bus handshaking, the microprocessor just drives thesignals at whatever speed it can.• It is up to the other parts of the circuit to keep up.• The hardware engineer will buy ROMs and RAMs that run at thedesired speeds (e.g. 120, 90, or 70 ns).CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Handshaking method #2: wait signals• Some microprocessors have aWAIT input signal that thememory can use to extend thebus cycle as needed.• If a device cannot respond asquickly as that diagramrequires, it can assert the WAITsignal to make themicroprocessor extend the buscycle.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Wait signal can put a device on holdindefinitely• READ/ means themicroprocessor wants data!• As long as the WAIT signal isasserted, the microprocessorwill wait indefinitely for thedevice to put the data on thebus.• Unfortunately, standard ROMsand RAMs don't come with await signal, so engineers needto build some externalcircuitry to drive the waitsignal correctly.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Handshaking method #3: wait states• The microprocessor has aclock input, which is used totime all activities.• Each of the signal changeshappens at a certain time inrelation the themicroprocessor input clocksignal.• The bus cycles are calledT1, T2, T3 and so on...CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

How a micro-processor worksThe microprocessor behaves as follows:• @ rising edge of T1 itoutputs the address• @ falling edge of T1, assertsthe READ/ line.• @ rising edge of T3 it takesthe data in (since it shouldbe valid).• @ falling edge of T3, it deassertsthe READ/ line.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Using wait states• If the microprocessor is able touse wait states, then it can insertclock cycles between T2 and T3.• The microprocessor will waitanother clock cycle (TW) forthe data to be ready.•Wait state generator is thepiece of hardware that insertswait states.•In software we can specify thenumber of desired wait states.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Direct Memory Access (DMA)CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

What is direct memory access(DMA)?DMA is a piece of circuitry that, without software assistance, can:• Read data from an I/O device, such as a serial port or anetwork, and then write it into memoryor• Read from memory and write its contents into an I/O deviceCaution: memory only has one set of address and data signals.The DMA must make sure that it is not driving those signalswhile the microprocessor is also driving them.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Using DMA: we want to transfer thedata from the I/O into RAM1.DMAREQ signal is asserted.2.DMA circuit asserts BUSREQto the microprocessor.3.When microprocessor is readyto give up the bus, it assertsBUSACK.4.DMA circuit puts address in theaddress bus.5.DMAACK and WRITE/ areasserted.6. I/O places data in the data bus.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

What’s next?Now that data has been writtento RAM, the DMA circuitreleases:• DMAACK• Address bus• BUSREQThe microprocessor releasesBUSACK and microprocessorexecution resumes.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of EngineeringInterrupts

What is an interrupt?•Micro-controllers can be ordered, or interrupted, to stopwhatever they are doing, and execute another piece of code•This other piece of code is the interrupt routine.•The signal that tells the microprocessor to run the interruptroutine is the interrupt request (or IRQ).•Interrupt request signals are typically LOW.•It is typical for interrupt request pins on I/O devices to beopen collectors, so they can share an interrupt request pin onthe microprocessor.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

Interrupt example•I/O device A caninterrupt theprocessor byasserting IRQ0/•I/O device B caninterrupt theprocessor byasserting IRQ1/•I/O device C andD can interrupt theprocessor by IRQ2/CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of EngineeringWatchdog timer

Watchdog timer•A watchdog timer contains a timer thatexpires after a certain interval unless itis restarted.•The watchdog timer has an output thatpulses should the timer ever expire, butthe idea is that the timer will neverexpire.•If the timer expires, (because it wasnever restarted), then the software hascrashed.CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering

How is a watchdog timer connectedto a circuit?•The output of a watchdog timer isconnected to the RESET/ signal ofthe microprocessor.•If the timer expires, the pulse on itsoutput signal resets themicroprocessor and starts the softwarefrom the beginning.•Different watchdog timer circuitsrequire different bit patterns to restartthem (ergo the glue circuit).CPE 355 - Real Time Embedded Kernels - Spring ‘12Nuno Alves (nalves@wne.edu), College of Engineering