Design of a Novel Economic Multiplier in VLSI using Reversible ...

International Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-2, December 2012Fig 9: Proposed circuit for Multi-Operand AdditionFig. 7: Proposed Partial Product Generation Circuitusing Peres GateThe proposed design of an 8*8 multiplier circuit inreversible logic requires 8 copies of each operand bit. In theexisting literature on multiplier operand bits are copied using24 Feynman gates. But in the proposed multiplier designfan-out is achieved using only 12 reversible gates. The fan-outcircuit is as shown in fig.8. It uses 4*4 BVF gates with twoconstant inputs.IV. RESULTS AND DISCUSSIONSComparison of different designs is done separately for boththe parts of each multiplier. The quantum cost of a PFAG [14]is shown as 8.The quantum costs of HNG, MKG and TSG isdeclared as „unknown‟ in [14] but it is equal to 6, 10 and 10respectively [16].Quantum cost of a gate and circuit is defined as the numberof quantum operations in a gate or circuit. In our proposedarchitecture the gates are quantum but the interconnection ofgates are classical, so the quantum cost of the circuit will besimply the addition of quantum cost of each gate.Table-II gives the comparative study of partial productgeneration of the circuit and table-III gives the comparativestudy of Partial Product Generation of different designs.PartialProductGenerationTable-II: Partial product generationNo. ofGatesNo. ofConstantInputsNo. ofGarbageOutputQuantumCostMKG[4] 40 40 32 88PFAG[5] 40 40 32 88TSG[6] 40 40 32 88HNG 40 46 80 104Fig 8: Fan-out circuit to duplicate the operand bits2. PARTIAL PRODUCT ADDITION:As proposed in [12], to implement an n-operand additioncircuit part a carry save adder [18] (CSA) is used. The CSAtree reduces the four operands to two [19]. Thereafter, a CarryPropagating Adder (CPA) adds these two operands andproduces the final 8-bit product. The proposed four operandadder is shown in Fig 9 using BVF gate.FG+PG 40 40 32 84(24+16)BVF+PG(Proposed)28 40 32 88In the proposed design, the no of gates required for thepartial product generation is only 28 whereas in other existingdesign it is equal to 40.Table-III gives the comparative study of multi-operandaddition of the proposed design with other existing designsassuming minimum quantum cost for HNG, MKG and TSGas 6, 10 and 10 respectively [16].319