Design of a Novel Economic Multiplier in VLSI using Reversible ...

International Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-2, December 2012Design of a Novel Economic Multiplier in VLSIusing Reversible Logic GatesKoushik Majumder, Malay Kumar Pandit, Asim Kumar JanaAbstract— In this paper, we present a new architecture formultiplication in VLSI (Very Large Scale Integration) with theadvantage of less quantum cost as well as less transistor count as aresult of reduction in number of gates to improve powerconsumption. Classical Logic Gates such as AND, OR, NAND(Except NOT) gates are not reversible that is inputs cannot berecovered from the output. On the other hand, in Reversible LogicGates inputs can be recovered completely from the output that isthere is one to one mapping between inputs and outputs.Reversible logic gates use less power compared to classical gatesand under ideal condition, they consume zero power. So we havedesigned a new architecture for multiplication using somereversible logic gates - BVF gate and Peres Gate. This helped us toachieve 24% less quantum cost, 15% less garbage output, and23% less no. of gates, which effectively reduces no. of transistors,and hence power consumption is minimum.Index Terms— Adder, Garbage Output, Multiplier, QuantumCost, Reversible Logic, VLSI.I. INTRODUCTIONOne of the major goals in VLSI (Very Large ScaleIntegration) circuit design is reduction of power dissipation.As demonstrated by R. Landauer in the early 1960s,irreversible hardware computation, regardless of itsrealization technique, results in energy dissipation due to theinformation loss [1]. It is proved that the loss of each one bitof information dissipates at least kTln2 joules of energy(heat), where k=1.3806505x10 -23 m 2 kg -2 K -1 (joules Kelvin -1 )is the Boltzmann‟s constant and T is the absolute temperatureat which operation is performed [2]. Reversible logic circuitshave theoretically zero internal power dissipation becausethey do not lose information. Hence, in 1973, Bennett showedthat in order to avoid kTln2 joules of energy dissipation in acircuit, it must be built using reversible logic gates [3].A circuit is said to be reversible if the input vector can beuniquely recovered from the output vector and there is aone-to-one correspondence between its inputs and outputs.Such gates or circuits allow the reproduction of the inputsfrom observed outputs and we can determine the inputs fromthe outputs [4-6], i.e. not only the outputs can be uniquelydetermined from the inputs, but also the inputs can berecovered from the outputs [5-7]. Thus, the number of inputsand outputs in reversible logic gates or circuits are equal.Reversible logic has received significant attention in recentyears. It has applications in various research areas such as lowpower CMOS design, optical computing, quantumcomputing, bioinformatics, thermodynamic technology, DNAcomputing and nanotechnology. It is not possible to constructquantum circuits without reversible logic gates. Synthesis ofreversible logic circuits is significantly more complicatedthan traditional irreversible logic circuits because in areversible logic circuit, we are not allowed to use fan-out andfeedback [5].A reversible logic circuit should have the followingfeatures [6]:• Use of minimum number of reversible gates.• Use of minimum number of garbage outputs.• Minimized quantum cost.• Minimized transistor countIn this paper, an improved design of reversible multiplierwith respect to 24% less quantum cost, 15% less GarbageOutput and 23% less no. of gates is proposed. Multipliercircuits play an important role in computational operationusing computers. There are many arithmetic operations whichare performed, on a computer ALU [8], through the use ofmultipliers. Design and implementation of digital circuitsusing reversible logic has attracted popularity to gain entryinto the future computing technology.This paper is organized as follows: Section 2 gives the briefintroduction of reversible logic gates used in proposedarchitecture. Section 3 describes the design of multipliercircuit and the implementation of the proposed multipliercircuit using new reversible gates. Section 4 gives thecomparative study of various architectures against ourproposed architecture and shows the advantage of ourproposed architecture. Section 5 gives the prospect ofremaining work.A. Feynman Gate:II. REVERSIBLE LOGIC GATESFig.1 shows a 2*2 Feynman gate [9]. The input vector is I(A, B) and the output vector is O (P, Q). The outputs aredefined by P=A, Q=A B. Quantum cost of a Feynman gateis 1 [9].Manuscript received on December, 2012.Koushik Majumder, Electronics & Comm. Engg., Haldia Institute OfTechnology, Haldia, East Midnapore, IndiaProf.(Dr.) Malay K. Pandit, Electronics & Comm. Engg., Haldia InstituteOf Technology, Haldia, East Midnapore, IndiaAsim K. Jana, Electronics & Comm. Engg., Haldia Institute OfTechnology, Haldia, East Midnapore, IndiaFig. 1: Feynman Gate317

International Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-2, December 2012Fig 9: Proposed circuit for Multi-Operand AdditionFig. 7: Proposed Partial Product Generation Circuitusing Peres GateThe proposed design of an 8*8 multiplier circuit inreversible logic requires 8 copies of each operand bit. In theexisting literature on multiplier operand bits are copied using24 Feynman gates. But in the proposed multiplier designfan-out is achieved using only 12 reversible gates. The fan-outcircuit is as shown in fig.8. It uses 4*4 BVF gates with twoconstant inputs.IV. RESULTS AND DISCUSSIONSComparison of different designs is done separately for boththe parts of each multiplier. The quantum cost of a PFAG [14]is shown as 8.The quantum costs of HNG, MKG and TSG isdeclared as „unknown‟ in [14] but it is equal to 6, 10 and 10respectively [16].Quantum cost of a gate and circuit is defined as the numberof quantum operations in a gate or circuit. In our proposedarchitecture the gates are quantum but the interconnection ofgates are classical, so the quantum cost of the circuit will besimply the addition of quantum cost of each gate.Table-II gives the comparative study of partial productgeneration of the circuit and table-III gives the comparativestudy of Partial Product Generation of different designs.PartialProductGenerationTable-II: Partial product generationNo. ofGatesNo. ofConstantInputsNo. ofGarbageOutputQuantumCostMKG[4] 40 40 32 88PFAG[5] 40 40 32 88TSG[6] 40 40 32 88HNG 40 46 80 104Fig 8: Fan-out circuit to duplicate the operand bits2. PARTIAL PRODUCT ADDITION:As proposed in [12], to implement an n-operand additioncircuit part a carry save adder [18] (CSA) is used. The CSAtree reduces the four operands to two [19]. Thereafter, a CarryPropagating Adder (CPA) adds these two operands andproduces the final 8-bit product. The proposed four operandadder is shown in Fig 9 using BVF gate.FG+PG 40 40 32 84(24+16)BVF+PG(Proposed)28 40 32 88In the proposed design, the no of gates required for thepartial product generation is only 28 whereas in other existingdesign it is equal to 40.Table-III gives the comparative study of multi-operandaddition of the proposed design with other existing designsassuming minimum quantum cost for HNG, MKG and TSGas 6, 10 and 10 respectively [16].319

Malay Kumar Pandit received his B.E and M. E degreesin Electronics Engineering from Electronics and TelecomEngg Dept., Jadavpur University, India in 1989 and 1991,respectively. He received his PhD from UK‟s renownedCambridge University in 1996. He did his post-doc fromthe Optoelectronics Research Centre, City University ofHong Kong till 2002 where he pioneered the use of polymers for opticalwaveguide applications. .He then took a corporate career where he worked ina fiber optic company ―FONS (I) Ltd‖ in the domain of optical networking.Now he is a full Professor in the Electronics Engg Dept. and Dean of Schoolof Engineering of the reputed Haldia Institute of Technology where hefocuses on embedded systems and grid computing, including their usage inWDM optical networks. He currently leads a MODROBS project of theAICTE, Govt of India on embedded electronic systems. He has 45international publications in this area. Dr. Pandit was awarded the NationalScholarship of the Government of India in 1983 and the Nehru Scholarshipof the Government of India during his Ph.D. studies.Asim Kumar Jana received his bachelor‟s andmaster‟s degree in Electronics & Telecomm Engg andMBA, respectively, from Jadavpur University, Indiain 1988 and 1995, respectively. He has 10 years ofindustrial experience in the domain of embeddedsystems. Currently he is an associate professor oncomputer systems. He has 10 international researchpapers.International Journal of Engineering and Advanced Technology (IJEAT)ISSN: 2249 – 8958, Volume-2, Issue-2, December 2012321