Assertion Based Verification using PSL

Assertion Based Verification using PSLSylvain BoucherPhilips SemiconductorsCDN Live!26-06-2006

What is an assertion?AN4• Assertions (Properties) state behavior yourdesign should always obey–e.g. The highest priority request shouldalways be granted first• Assertions can also state forbidden behavior–e.g. Never assert grant without Request• Assertions may also be used for coverage:–e.g. All the states of my FSM have beentested or are reachablePhilips Semiconductors Sylvain Boucher 26-06-20062

Slide 2AN4Add one bullet:Ensure that forbidden behaviour do not occur (safety properties) for example: Never assert grant without a requestAnders Nordstrom, 10/28/2005

Where does Assertion Based Verification fit inthe flow?Design Phase:Formal to verifyimplementation versusAssertionsIP Level Verification:Possibly FormalNon-formally verifiedAssertions checked in SimulationPhilips Semiconductors Sylvain Boucher 26-06-2006System Verification:Possible reuse of assertions in:•Simulation•Emulation•FPGA3

AN5Property Specification Language (PSL)• PSL is IEEE 1850, it’s supported by EDA community• Supports Verilog, VHDL but also SystemVerilog andSystemC• Powerful in describing Assertions e.g:Request and fifo empty are never high at same timeassert never { req AND fifo_empty };Request is always acknowledged 1 to 3 cycles after assertedassert always { rose (req) } |-> { [*1:3]; ack};Request is acknowledged eventuallyassert always req -> eventually! ack;Philips Semiconductors Sylvain Boucher 26-06-20064

How to use Assertions?1) At module level:– White-box assertions to check implementationchoices– Black-box to check implementation againstspecification:• Assertions describe output behaviors• Constraintsdescribe validity domain for inputs2) For interfaces:– Library of assertions can be used & reused to verifydifferent IP protocol interfaces3) Automatically generated assertionsPhilips Semiconductors Sylvain Boucher 26-06-20065

Assertions for Enhancing Debug processPhilips Semiconductors Sylvain Boucher 26-06-20066

Slide 7AN6Formal improve controlabiltyAnders Nordstrom, 10/28/2005

Advantages of AssertionsAssertions:• Enhance observability, reducing debug time• Remove ambiguity from Specification natural language• Provide additional coverage• Travel with the IP RTL sourcesPhilips Semiconductors Sylvain Boucher 26-06-20068

Formal VerificationReachableState SpacexxxInitialStatexxSimulation Disadvantages• Depends on the quality of thetest bench• Limited controllabilityxBugs triggeredby SimulationPhilips Semiconductors Sylvain Boucher 26-06-2006xxxxxxxxxxFormal Analysis Advantages• No test bench required• Explores in all directions:unlimited controllability• Can reach full coverage ondesign state space9

Simulation-Based Verification• Use of Assertions in Simulation:–Allows implementation of additional checks⇒enhances observability–Gives control-oriented functional coverageinformation⇒enhances coverage measurement for Coverage-Driven VerificationPhilips Semiconductors Sylvain Boucher 26-06-200610

Example: Formal Verification of Memory CtrlLogical⇒Physical Address Translator13 PSL ConstraintsBlock SpecificationPhilips Semiconductors Sylvain Boucher 26-06-200611

Example: Formal Verification of Memory CtrlLogical⇒Physical Address Translator15 PSL AssertionsBlock SpecificationPhilips Semiconductors Sylvain Boucher 26-06-200612

Example: Formal Verification of Memory CtrlLogical⇒Physical Address TranslatorPSLConstraints13IncisiveFormalVerifier(IFV)•2 days of work•Full IFV runtakes ~20 minutes(CPU time)PSLAssertions15Philips Semiconductors Sylvain Boucher 26-06-200613

Example: Protocol CheckingRTL Monitor+PSL AssertionsBus (e.g. AHB, AXI, etc…)Philips Semiconductors Sylvain Boucher 26-06-200614

Example: Protocol Checking (2)RTL Monitor+PSL AssertionsAPBInterfaceRTLBlockPSL Bus Monitor used to set constraints & assertions for Formal VerificationPhilips Semiconductors Sylvain Boucher 26-06-200615

Example: Protocol Checking (3)RTL Monitor+PSL AssertionsAPB eVCor BFMAPB based IP(e.g. UART)UART eVCor BFMEnhances Error Checking/Debug & Functional Coverage of Test BenchPhilips Semiconductors Sylvain Boucher 26-06-200616

Example: Protocol Checking (4)……AHB2APBBridgeMonitor@ System Level, PSL Bus Monitor checks for Protocol violationsPhilips Semiconductors Sylvain Boucher 26-06-200617

Example: Protocol Checking (5)FPGA orEmulator orSiliconSynthesizedRTL Monitor+ PSL AssertionsHWStatic BreakpointsDebug EnvironmentPhilips Semiconductors Sylvain Boucher 26-06-200618

Conclusions• Assertion Based Verification helps closing theverification gap:Shorten Time-to-MarketReduce Cost of Non QualityPhilips Semiconductors Sylvain Boucher 26-06-200619