Test Coverage Analysis - Research

Test Coverage AnalysisMaster Degree ThesisDepartment of Computer Science and Electronics (IDE)Author: Francisco Páez Padilla

5.1.1.2.2 Device Property Weight Allocation...................................................................................... 515.1.1.2.3 Device Property Scoring....................................................................................................... 535.1.1.2.4 Board Device Score .............................................................................................................. 535.1.1.2.5 Maximum Achievable Device Score .................................................................................... 535.1.1.3 Connection Metrics.................................................................................................................... 545.1.1.3.1 Connection Property Weight Allocation............................................................................... 545.1.1.3.2 Board Connection Score ....................................................................................................... 555.1.1.3.3 Maximum Achievable Connection Score ............................................................................. 555.1.2 Component Analysis ............................................................................................................. 555.1.3 Tested Components............................................................................................................... 645.1.3.1 ICT Tested/Untested Components ............................................................................................. 645.1.3.2 FT Tested/Untested Components............................................................................................... 655.1.4 Test Coverage ....................................................................................................................... 775.1.4.1 ICT Coverage............................................................................................................................. 775.1.4.1.1 Board Device Score .............................................................................................................. 775.1.4.1.2 Board Connection Score ....................................................................................................... 785.1.4.2 FT Coverage .............................................................................................................................. 795.1.4.2.1 Board Device Score .............................................................................................................. 795.1.4.2.2 Board Connection Score ....................................................................................................... 795.1.4.3 Special Tests .............................................................................................................................. 805.1.4.3.1 Board Device Score .............................................................................................................. 805.1.4.3.2 Board Connection Score ....................................................................................................... 815.1.4.4 Combined Test Coverage........................................................................................................... 815.1.4.4.1 Combined Board Device Score............................................................................................. 825.1.4.4.2 Combined Board Connection Score...................................................................................... 835.2 FUNCTIONAL TEST COVERAGE ANALYSIS.................................................................................. 846 RESULTS AND IMPROVEMENTS .............................................................................................. 866.1 PCB’S STRUCTURE..................................................................................................................... 866.2 PCB’S FUNCTIONALITY ............................................................................................................. 877 REFERENCES: ................................................................................................................................ 89Appendix A

1 IntroductionIn a generalized meaning, quality has a pragmatic interpretation as the non-inferiority,superiority or usefulness of something. The quality of a product or service refers to theperception of the degree to which the product or service meets the customer'sexpectations. Quality has no specific meaning unless related to a specific function and/orobject. ISO 9000 states that quality is the degree to which a set of inherent characteristicfulfills requirements [1].In the Merriam-Webster dictionary it is defined as the degree of excellence or superiorityin kind, among other definitions [2]. For the isixsigma dictionary it is a reduction ofvariation around the “mean” [3].The American Society of Quality describes it, in technical usage, as the characteristics ofa product or service that bear on its ability to satisfy stated or implied needs. Also, itdefines quality as a product or service free of deficiencies [4].From the exposed definitions, it is clear that quality is not only a desirable feature withina product (in this case a printed circuit board -PCB-), but mandatory. Furthermore, thischaracteristic directly influences the circuit‘s behavior.The use of PCBs in the daily life is an irrefutable fact, although most of the people arenot aware of this; since the interaction is not directly with the circuit, but with thedevice’s interface (buttons, keyboards, screens, displays, etc.). Printed circuit boards areused in communications (cellular phones, computers, etc.), entertainment (televisions,DVD players, etc.), transport (cars, trains, airplanes, etc.), among several otherapplications.An electronic circuit whose quality is not ensured might present a malfunction in one ofits tasks, in the best case. In the worst case it might be completely useless or damaged. Inany of the depicted examples, it is clear that the product is not fulfilling the customer’srequirements.2

By taking as example the automotive industry, where the use of electronic is widelyspread (diagnostics of all the modules as well as the communication among them isperformed using electronic circuits), a defect on any of the mounted PCBs (such as theone in charge of the airbag deployment) might lead to an accident, under specificcircumstances. This sort of issues could be seen from two different perspectives:economical and humanist.From the economical point of view, a lawsuit will be filed; deriving thus in the paymentof high amounts of money. Other consequence is the repairs of the whole lot of PCBswhich present the problem or the complete replacement or removal of them from themarket.From the humanist point of view, the most important of these, lives might be saved if thequality of the circuit is ensured. In this example, a circuit that complies with therequirements of the customer and government (i.e. it has the highest quality) will avoidfalse deployments during normal conditions of driving or it will deploy to the correctstage in case of an accident.The same issues apply to the PCBs used in trains. These are the circuits whose testcoverage will be analyzed. Hence, in any of the exposed cases, quality assurancebecomes crucial.Quality Assurance (QA) is defined as all those planned or systematic actions, necessaryto provide adequate confidence that a product or service will satisfy given requirementsfor quality [5].For products, quality assurance is a part and consistent pair of quality managementoffering supposedly fact-based external confidence to customers and other stakeholdersthat a product meets needs, expectations, and other requirements. QA claims to assure theexistence and effectiveness of procedures that attempt to make sure that the expectedlevels of quality will be reached [5].3

The Merriam-Webster dictionary states quality assurance as a program for the systematicmonitoring and evaluation of the various aspects of a project, service or facility to ensurethat standards of quality are being met [6].Isixsigma dictionary defines quality assurance as a planned and systematic set ofactivities to ensure that variances in processes are clearly identified, assessed andimproving defined processes for fulfilling the requirements of customers and product orservice makers [7].Quality Assurance, as defined by the American Society of Quality is: all the planned andsystematic activities implemented within the quality system that can be demonstrated toprovide confidence that a product or service will fulfill requirements for quality [4].These planned and systematic activities normally are tests performed to the product.Focusing the definitions in the PCB, the mentioned tests are executed over the devicesplaced in the circuit. Also the PCB’s functionality is verified.The measurement of what devices are tested as well as which requirements are fulfilleddetermines the quality of the PCB. In this sense, if every component which comprises acircuit is verified and all the requirements are complied, the circuit’s quality is ensured.Therefore a method specifically developed for assessing the aforesaid measurement shallbe used. The figure yielded by this method will set the quality of the circuit. Based on it,improvements could be done.The purpose of this project is to do a research about the existent methods for analyzingtest coverage and to choose the suitable for determining this feature. Also, in case of benecessary; implement changes to increase the confidence on it. If none of the reviewedmethods provides a trustworthy result, a method shall be developed. In any of thesesituations, the design and development of mechanisms to facilitate the application of themethod, it is also part of the project.4

The task is not only to find or to develop a method, but also to apply it to a circuit inorder to prove that it is capable of generating a reliable result that could be used asevidence of the PCB’s quality.The chosen or developed method shall be able of establishing the confidence level ofeach test applied to the circuit. This is done by reviewing the attained test coverage. Also,shall give guidelines of where is necessary to put special effort in order to increase thequality assurance, by increasing the test coverage. This last statement, just if necessary,since a priori it is not possible to state that the test coverage is low.The method shall provide means to combine the achieved test coverage of each of the testtechnologies used to verify the PCB, in order to find the final value of this feature. Thisfigure will show the weaknesses regarding testing and hence will point out whereimprovements could be introduced.It shall be applicable to any circuit board, regardless of the PCB’s design, type or amountof components mounted on it. Obviously, there could be some adjustments which shall bedone with ease.The scope of the project is limited to research and/or develop a method for determiningthe test coverage achieved by the test performed during the production process of theprinted circuit boards. It is out of the project’s scope the assessment of test coverageattained during the development process.5

2 State of the ArtA product, such as a printed circuit board (PCB), could be tested either on its structure oron its functionality during the production process.Structural test makes no direct attempt to determine if the overall functionality of thecircuit is correct. Instead, it tries to make sure that the circuit has been assembledcorrectly from some low level building blocks as specified in the schematic and layout.For instance, it reviews if all the devices are mounted and connected correctly. Thestipulation is that if the schematic and layout is correct and structural testing hasconfirmed the correct assembly of the components, in theory the circuit should befunctioning correctly.Functional testing attempts to validate that the circuit under test performs properly thetasks for which it was designed. Assuming that the PCB was assembled in a propermanner, the functional test is intended to verify the right behavior of the devices mountedon the board.By taking into account these definitions, there are different standards for modeling ormodels used in order to evaluate the test coverage of a product. These are listed below. Structuralo IPCo MPSo PPVSo PCOLA/SOQ Functionalo DMPSFo PCOLA/SOQ/FAIMRegardless of the model, there is a major division on a PCB, when it is being tested:devices (such as resistors, integrated circuits (IC), etc.) and connections. Each of thesedivisions can have either a defect (fundamental) or a deviation (qualitative) from a norm6

[8, 9]. The difference between these terms is that the former affects directly the board’sperformance, while the latter might affect the behavior of the board in a short or longterm.All the models are based on properties of the PCB, which are seen as a probable cause offailure or the defect universe. Actually, the properties give the name to the model as isshown later by the bold letters. It is important to mention that even when the functionalmodels include properties of the structural models, the resulting test coverage is given byseparated (i.e. one structural test coverage and one functional test coverage).IPC is a model that focuses on Termination, Placement and Component as the propertiestaken into consideration for evaluating the test coverage done on a printed circuit board.These are subdivided into several different properties that depend on the analyzed PCB[10].MPS or DMPSF was developed by Philips Research and is based on the followingproperties: Material, Placement and Solder for the Structural test. This one adds Designand Function for the Functional test [8].PPVS is a model designed by ASTER Ingénierie, which evaluation of the test coverage isdone using the following properties: Presence, Polarity, Value and Solder [8].PCOLA/SOQ or PCOLA/SOQ/FAIM is the most used model to evaluate test coverage andwas developed by Agilent Technologies. This standard is based on Presence, Correct,Orientation, Live, Alignment, Short, Open, Quality properties regarding the structure’sverification. For the functional test it adds Feature, At-speed, In-parallel andMeasurement [8, 9, 11, 12].The analysis of the properties given for the different models leads to the conclusion thatin certain manner, these take into account the same features. For instance, in MPSplacement is related with Presence in PPVS and PCOLA/SOQ and Placement in IPC.7

Therefore, the suitable model to use in order to analyze the board test coverage isPCOLA/SOQ since it is the most detailed.8

3 TheoryThe scope of this project, as mentioned in the introduction, is to find or to develop amethod capable of generating a reliable result regarding test coverage. In order to achievethis goal, a complete comprehension of the theory behind tests is necessary.Basic concepts related with tests to circuits are defined for understanding what is checkedand what is not verified by a specific test method. Also, the defect classification isexplained.There are several tests that could be applied to the PCB in order to ensure that it isworking properly and complying with the requirements. The most commons, amongthese, are explained later in this section.Since the tests developed and executed for a specific product are based on requirements,a complete explanation of the theory behind them is given. The comprehension of what isa good requirement as well as its management and analysis is rather important to achievethe highest quality in the printed circuit board.3.1 ConceptsThe most important concepts about tests that will be used through this report areintroduced in the next paragraphs.Defect: is an unacceptable deviation from a norm [9]. Also it is defined as a specificcause of a failure. Examples of defects are: An open solder joint. A short caused by excess solder, bent pins. A dead device due to ESD or a cracked resistor. The placement of an incorrect device. A missing device. A polarized device rotated 180 degrees.9

A misaligned device (typically laterally displaced).Deviation: it is not a direct or immediate cause of malfunction of the device; rather itmight be the cause of improper behavior of the board in the short or long term [9].Examples are: A solder joint with insufficient, excess, or malformed solder. A misaligned device (displaced by a few degrees).Coverage: numeric indicator of the quality of the test [9] or the ability for detectingdefects. Also it is a measure of how much of the target product is actually verified by thetests applied to it.Device: any component placed on the board [9]. From resistors, ICs to heat sinks, RFIshields, etc.Connection: how a device is electrically connected to the board [9].Testing: is the process of systematically running a test method in order to find defects ordeviations.Requirement: a statement of essential product or system characteristics. A condition orcapability needed by a user to solve a problem or achieve an objective. A condition orcapability that must be met or possessed by a system for satisfying a contract, standard,specification, or other formally imposed document.Requirement Management: encompasses all aspects dealing with requirements fromgetting initial requirements until the verification that the product meets thoserequirements.Requirement Analysis: is the study of a problem and/or its requirements done in order todesign and develop adequately a product.10

3.2 Defect ClassificationA flaw could be present or introduced at different levels during the lifetime of the circuit.For the purpose of this project, the defect classes are: Design Production FunctionDefects related with design are found during the execution of functional tests. Flawsregarding function of the components are found during the verification of the circuit’sfunctionality. In the instance of production defects, these might be found when the PCB’sfunctionality is being tested, but these shall be found when the structure is verified.Important to emphasize is the fact that faults in design and functionality are pointed outbecause of non-fulfillment of a specific requirement. In the case of the production defect,it is found due to an inconsistency between the devices and connections in the circuit andwhat is indicated regarding these, in the schematic.3.3 Test MethodsThere are too many test technologies used to verify PCBs, as mentioned before. The mostcommon test methods are described in order to give a wide idea of what is possible to testand what is impossible to verify by a specific tester. This information is very importantfor qualifying correctly each property of the chosen method.In-Circuit Test (ICT): operates by measuring each component in turn to check that it is inplace and of the correct value. As most faults on a board arise out of the manufacturingprocess and usually consist of short circuits, open circuits or wrong components, thisform of testing catches most of the problems on a board [13].It is very easy to measure the value of a component when it is not in a circuit. Howeverwhen the component is in a circuit, the situation is somewhat different. To overcome this11

problem and gain a far more accurate indication of the value of the component the nodesaround the component under test are earthed and in this way any leakage paths areremoved and more accurate measurements made [13].In order to carry out the test it is necessary to gain access to each node on the board. Themost common way of achieving this is to generate a “bed of nails” fixture. The board isheld in a place accurately by the fixture and pulled onto spring laded pins that makecontact with connections on the board [13].With access to all the nodes on the board, manufacturers generally quote that it ispossible to find around 98% of faults using in circuit test. This is very much an idealfigure because there are always practical reasons why this may not be achieved. One ofthe major reasons is that it is not always possible to gain complete coverage of the board.Low value capacitors are particular problem as the spurious capacitance of the testsystem itself means that low values of capacitance cannot be measured accurately if at all.A similar problem exists for the inductors but at least it is possible to discriminate if acomponent is in place due to the fact that it exhibits a low resistance [13].Further problems are caused when it is not possible to gain access to all the nodes on theboard. This may result from the fact that the tester has insufficient capacity, or it mayresult from the fact that a point to which the tester needs access is shielded by a largecomponent, or anyone of a number of reasons [13].The advantage of an ICT is that most board faults arise from problems in manufacture.These might arise from the incorrect component inserted, a wrong value resistor and adiode in the wrong way, among other causes. These are very easily and quickly locatedusing ICT [13].The testers are also very easy to programme and no long diagnostic routines are requiredto locate any problems. Whilst the fixtures can be reasonably expensive the production ofthese as well can be automated to a large degree. However against this any changes to the12

oard layout as a result of up-issuing the board can result in changes to the fixture thatmay be difficult to implement [13].There are some other limitations. The first is that they obviously cannot provide a fullfunctional check of the specification of the board. As the board is not being exercised inits operational mode, its operational parameters cannot be checked [13].Another problem that is becoming more difficult to overcome is that access to the nodesis becoming more difficult. Also the size of component connections is becoming muchsmaller and this means that probing these points is far more difficult [13].Inherent limitations regarding the test of devices are the following: Large capacitance in parallel with low capacitance, due to the tolerances, it isimpossible to distinguish if the low-value capacitor is placed on the board. Large resistance in series with low resistance represents the same situation statedin the previous statement. Rated voltage of polarized capacitor is not verified. For example it is possible todiscriminate a capacitor of 1 μF as such, but not that rated voltage is 25 V. Power rating of resistor is not tested. ICT lacks of means to distinguish a resistorof 1 kΩ with a power rating of ½ watt from a resistor of the same value but with apower rating of ¼ watt. Any active device such as an IC or transistor can not be tested completely on itscorrect value. For instance, it could perform the test over an IC with exactly thesame features and similar pins than the expected IC, but different ID code. Any diode which matches the situation depicted in the last statement. Quality of component’s placement and solder is not checked. This test has nomeans to determine if a component is inclined or if there is excess solder, forexample.Automated Optical Inspection (AOI): is a powerful tool for assessing workmanshipcompliance in Prototype as well as Production PCB assembly environments. With13

advanced lighting, optics, and image processing capabilities, the machines greatlyenhance inspection repeatability, accuracy and throughput. AOI plays a vital role in teststrategies designed to ensure the highest possible quality throughout each phase of aproduct’s life cycle [14].This method performs an optical inspection process in which a printed circuit board isautomatically scanned for ensuring its quality. The generated image is compared to adesign-based or memorized standard that allows flaws, such as cracks, voids and bridgesto be detected. These defects can then be portrayed to an operator for rework or rejectionof the product.AOI eliminates the subjectivity and variability necessarily associated with manual visualinspection. Systems are integrated into the automatic assembly processes to provide100% visible component and solder-joint inspection [14].Due to the nature of this technology, it is possible to verify the correct value of acomponent with the ID code. Also, by identifying the notch of an IC or the line in a diodeor the indication in a polarized capacitor it can determine if the component is correctlyoriented.Quality regarding the placement and solder is fully tested by AOI. The image created bythe scanning process is verified against a well defined pattern of solder in order todetermine the quality. Related to the placement, the image is compared against an imagewhich contains the right alignment of the components.The inherent limitations of this test are: The adequate functionality of the component is not checked. Although it can findcracked components, it lacks of means to verify if a device is damaged by ESD,for example. Tolerance and power rating in resistors is not tested. Tolerance and voltage rating in capacitors is not verified.14

Due to the board’s design, there is other limitation that might be present. This one isregarding a component that is placed below another component. The scanning in most ofthe system is done with a camera placed over the PCB and hence in the exposed case, theplacement of the device could not be determined.Human Visual Inspection (HVI): is a test performed, as its name implies, by a human. Incertain way is the predecessor of AOI. Based on the layout of the circuit, the operatordetermines if the component is placed, also if the value and orientation is correct. In thiscase, the quality of the solder as well as the alignment is verified.This kind of test is quite useful when a specific component shall be verified. For instance,the polarity of capacitors is checked, before executing an ICT.In comparison with an AOI system, human vision has limited accuracy and is slow butvery flexible and easy to train. Also, under specific circumstances, it could overcome theproblem of a component mounted below another device. In this case, this componentcould be verified by HVI in order to maximize the test coverage. About the inherentlimitations, it has exactly the same than AOI.Automated X-Ray Inspection (AXI): is a technology based on the same principles as AOI.It uses x-rays as its source of light, instead of visible light, to automatically inspectfeatures, which are typically hidden from view.AXI is designed to find structural solder faults including solder opens, shorts, insufficientsolder, excessive solder, missing electrical parts, and mis-aligned components. Thisincludes non-visible joints such as area-array packages (BGA, CSP, Flip Chip), partsunder RF shielding, and some connector styles. Defects are rapidly detected and repairedwith almost no debug time [15].The limitations that are inherent to this technology are the same than the ones of AOI, butalso it lacks of means to verify completely the correct value of the active devices. Since it15

is scanning with x-ray instead of visible light, the image produced is not as defined as theone generated with AOI.Flying Probe: is a test technology relatively recent, in which test probes are moved to thevarious test pads. Flying probe testers require no test fixtures (as ICT does need), havefew restrictions on board access and can test boards with virtually unlimited number ofnets, allowing developers to turn test programs around in a short time [16].Due to this flexibility, they are particularly suited for the automatic testing of prototypes,in the product launch phase, in the production of relatively small numbers or a largenumber of many different assemblies, where the costs incurred for needle-bed adaptersdo not represent a feasible proposition [17].On the other hand, the time needed to perform a test increases dramatically. Due to thatfact it is not suitable for circuits whose production volume is rather large.Regarding the limitations inherent to this test technology, due to its nature, present thesame than the ICT.Boundary Scan Test (BST): is a method for testing interconnects (thin wire lines) onprinted circuit boards which is implemented at the integrated circuit level. Rather usefulwhen testing becomes difficult due to board trace widths and separations below 0.1 mm,package pin separations of 0.3 mm or less, surface-mount packages on both sides of theboard and multilayer boards [18].BST provides means to test interconnects between integrated circuits on a board withoutusing physical test probes. It adds a boundary-scan cell that includes a multiplexer andlatches, to each pin on the device, overriding its functionality. Boundary-scan cells in adevice can capture data from pin or core logic signals, or force data onto pins. Captureddata is serially shifted out and externally compared to the expected results. Forced testdata is serially shifted into the boundary-scan cells. All of this is controlled from a serial16

data path called the scan path or scan chain [18]. If the trace is shorted to another signalor if the trace has been cut, the correct signal value will not show up at the destination pin,and the board will be identified as faulty.The boundary-scan standard specifies a four wire test interface using the four followingsignals: test data in (TDI), test data out (TDO), test clock (TCK) and test mode select(TMS). These four signals are the test-access port (TAP) and are connected to the TAPcontroller inside the IC. This one is a state machine clocked on the rising edge of TCKand with state transitions controlled by the TMS signal. A fifth signal, test reset inputsignal (nTRST or TRST), is an optional interface pin for reseting the test-access portcontroller [19].From the given definition, this is a method not intended to test passive devices, such asresistors, capacitors, inductors, etc. Indirectly, this kind of components might be tested,but a thorough analysis shall be done in order to discriminate the devices verified by thistest technology.The inherent limitations of this test are: Only ICs and their interconnections are considered as checked. All othercomponents require a thorough analysis for determining whether they are testedor no. If one of the above mentioned devices is being verified (passive or active),tolerances, power rating and voltage rating (when these features apply) are nottested. Also, related with correct value, it could not be tested due to componentswhich features are similar to the expected component. An example of such asituation was described in the ICT definition. Some ICs which have no ID code are not verified in his correct value, since itcould be a device with the same pin assignment. Quality of component’s placement and solder is not checked. This test has nomeans to determine if a component is inclined or if there is excess solder, forexample.17

Functional Test (FT): is a method used to verify the functionality of the circuit, as itsname implies. Depending on the complexity of the system and the tasks it performs, FTcould be a set of several tests. Each one of these is intended to verify the correctexecution of a specific task of the circuit under test. The test environment is usuallydesigned to be similar or as close as possible to the environment in which the productunder verification will be used.The result of the test is Boolean, either pass or fail. In order to determine this value, aclear description of the task to be performed as well as the expected behavior from theside of the unit under test is necessary. If there is a correct match between them, the testis qualified as a pass, otherwise the grade is fail.The set of tests are developed and executed taken into account requirements that shall becomplied. Also, the criteria of acceptance or rejection are based on requirements.Important to emphasize is that all requirements specified for the unit under test shall befulfilled for considering the whole test as passed.Burn-In Test (BIT): is a test intended to stress the product under verification by varyingthe temperature conditions of the environment in which it is being checked. Normally thefunctional test is being performed when this method is applied to the PCB.In order to carry out the test, an environmental chamber is necessary for temperatureconditioning. This chamber will vary the test conditions from a low temperature to a hightemperature with a certain rate of change, specifically design for the circuit. For instance,it could pass from 5˚ to 90˚ in a couple of hours, then maintaining the temperature in 90˚for one hour. Once this time has elapsed, the opposite operation is executed; temperatureis decreased from 90˚ to 5˚ with the same rate of change and then keeping thetemperature for one hour at 5˚.A cycle like the described is run during a specific period of time in which the functionaltest is being executed in the circuit. The result is, as in the FT, a Boolean value.18

There are other tests that are performed to a PCB, such as: insulation Test, mechanicaltest (shock and vibration), validation test (extreme changes in temperature and humidity),EMC. Despite these are not described, are mentioned just to give an overview of thedifferent tests executed in order to comply with the government standards of quality.3.4 RequirementsAs previously mentioned, the tests are developed based on the requirements. Therefore,the requirements shall have certain characteristics and components in order to describeadequately the product.3.4.1 Requirement CharacteristicsNecessary: the stated requirement is an essential capability, physical characteristic, orquality factor of the product or process. If it is removed or deleted, a deficiency will exist,which cannot be fulfilled by other capabilities of the product or process.Unambiguous: each requirement must have one and only one interpretation.Implementation free: the requirement states what is required, not how it should be met.Complete: the stated requirement is complete and does not need further amplification.Completeness is dependent upon the author’s intent. Requirements should be statedsimply, using complete sentences. Each requirement paragraph should state everythingthat needs to be stated on the topic and the requirement should be capable of standingalone when separated from the other requirements.Notice that requirements with TBDs are not complete. Therefore requirements withTBDs should identify why the TBD exists, so the TBD can be resolved, identify whatmust be done to resolve the TBD.Verifiable: the stated requirement is verifiable if there exists some cost-effective processwith which a person or machine can check that the product meets it.19

Concise: the requirement statement includes only one requirement stating what must bedone and only what must be done, stated simply and clearly. It is easy to read andunderstand.Consistent: the stated requirement does not contradict other requirements. It is not aduplicate of another requirement. The same term is used for the same item in allrequirements.Maintainable: a requirement statement is maintainable if any changes to it can be madeeasily, completely, and consistently while retaining the structure and style of therequirement and document.Traced: the stated requirement is traced if its origin is clear.Traceable: the stated requirement is traceable if it is written in a manner that facilitatesthe referencing of each individual requirement.Feasibility: the stated requirement can be achieved by one or more developed systemconcepts at an acceptable cost, schedule, and technology.3.4.2 Requirement ComponentsAssumptions: authors do not have access to sufficient information or the informationneeded by the authors does not existConditions: the part of a requirement which identifies the qualifying conditions underwhich (and only under which) a requirement for a product’s performance is valid.Negotiated Value: a numeric expression that answers the question “how much”, “howwell”, or “when”. Negotiated values communicate an acceptable level of performance.Negotiated Values usually contain:20

A nominal value 13.8 A tolerance value + 0.5 Engineering units voltsTolerances can be expressed as: Single Limit Boundaries: 13.8 volts Range of Values: 10.0 to 18.0 volts Nominal Values with Tolerances:13.8 + 2.5 voltsIt is necessary always to specify the engineering units. Also, the nominal and tolerancevalue should contain the same significant figures.Graphs: are useful for conveniently depicting numerical data, showing trends, cycles,cumulative changes, relationships between variables, and distributions. However, graphsusually do not provide precise data, but readers are able to extract relatively accuratenumerical data easily.Graphs should not be used as requirements because they have fewer significant figuresthan discrete numbers, they are used more to interpret data than discrete numbers andmay have less precision and with difficulty they show boundary values because theresults may be difficult to interpret.Tables: are useful for compressing data, for organizing large amounts of data orcomparative figures, quick and accurate comparison of data values and for eliminatingredundant words from text descriptions.Tables can result in a loss of context and completeness. Also, these add more complexityto traceability and configuration management.External References: tags or document identifiers which identify other documents assources of additional requirements and/or information.21

External documents that may be referenced are documents which provide additionalrequirements (should be referenced in the requirements section) and tutorial orexplanatory information (should be referenced from the overview or explanatory section).Internal References: tags or section identifiers which identify other requirements withinthe same documents as sources of additional requirements and/or information. Internalcross referencing is made by title and/or description, but not by explicit paragraphnumber.3.4.3 Requirements ManagementRequirements Management is made up of several activities or elements. Each elementplays an important role in Requirements Management. These elements are presented inthe following paragraphs.Acquisition: is the method used for obtaining requirements from the customer or internalrequirements.Analysis: the study of requirements. Analysis is performed to ensure quality requirementdocuments.Documentation: the record of requirements. It ensures that the requirements areimplemented with the highest quality.Change Control: the mechanism by which requirements are allowed to change in acontrolled manner.Traceability: is the link or definable relationship between two things. Requirementstracing provides a mechanism to demonstrate:• That all needs are implemented and adequately tested.• That there are no “extra” implementation details that cannot be traced back torequirements.22

• An understanding of the impact of changing requirements.3.4.4 Requirements AnalysisThe purpose of requirements analysis is to provide the analyst with an understanding anda description of the problem and/or requirements that are complete, consistent andunambiguous.Requirements analysis can be performed in many different ways, among others by merelyreading the document and noting issues and concerns. Also can be performed usingformal structure analysis techniques, where a formal model is created of the requirements.In either case, the analysis is intended to allow the analyst to focus on individualrequirements one at a time. When this focus is attained a more productive analysis isachieved.Requirements analysis is important because it gives a better understanding of the problem,uncovers incomplete or ambiguous specifications early in the program, identifies areas ofthe problem sensitive to change, provides faster response to change requests, insight intoa design strategy, provides a mechanism to standardize documentation, promotes analysisreuse and promotes hardware and software design reuse (indirectly).23

4 Method DescriptionAs established in section 2, a board during the production process is tested on its structureand functionality. Therefore, the test coverage is assessed for each of these features. Inthis section is defined by separated, the method for calculating the structural andfunctional test coverage.4.1 Structural Test Coverage AnalysisIn this section, a complete description of how the method produces a test coverage figurerelated with the board’s structure is given. Also, the definition of the properties andmetrics taken into account in this project are introduced. The modifications made to themodel in order to achieve a reliable result are explained as well.There are two concepts added for increasing the confidence in the attained result. Theanalysis of the function of each component mounted on the PCB as a tool to determinewhich tester could verify the device is one of these.The second concept is related with the requirements that shall be fulfilled by the teststrategies applied. Also, an explanation of the procedure followed in order to determinethe components that are being tested during the performance of a functional test isprovided.4.1.1 PropertiesAs previously stated, the chosen model to analyze test coverage is PCOLA/SOQ. Thefollowing sections contain a description of the properties of this model, divided in deviceproperties and connection properties.4.1.1.1 Device PropertiesPresence: this property states if the device is placed on the board, regardless of its valueor any other feature that could be measured. In essence, the test will only determine24

whether the device is placed or not [9]. Obviously, if the component is misplaced, theverification of the other properties becomes worthless.Correct: this property defines if the value of the device is the expected. For instance, aresistor of 1kΩ is determined as such by the test performed over it, if its value is roughly1kΩ (taking into account the tolerance of the resistor). There are test methods in whichno means are provided to distinguish if the resistor is of ½ watt or ¼ watt, such as In-Circuit Test or Automated X-ray Inspection, therefore it can not qualify as completelytested [9].Orientation: determines if the component is correctly oriented. Issues could be present in90˚ multiples [9]. Examples of this property are a diode rotated 180˚ (set in the wrongdirection) or an IC rotated 90˚, 180˚ or 270˚.Live: (word used as synonym of alive) gives an estimation of the status of the device: if itis broken (damaged by ESD or mechanically damaged) or alive. Important to remark is ifthe device is alive, it does not mean necessarily that is fully functional, but widelyfunctional [9].If the device has a fault in any of the properties before mentioned, it will lead directly to amalfunction of the PCB creating a defect, while the next property, in case of fail willproduce a deviation [9].Alignment: states if there is a lateral displacement by a small distance or a rotation by afew degrees of the component [9]. By the given definition, the difference between thisproperty and orientation property becomes clear.4.1.1.2 Connection PropertiesFrom the connectivity point of view, there are two properties related with defects (shortand open) and one regarding deviations (quality) [9]. Their definitions are given in thefollowing paragraphs.25

Short: is present between two or more pins, whose impedance is roughly 0 Ω. There are acouple of considerations that shall be done over this property. The first of them is that bythe given definition, it is seen as one fault, even though it might be present in more thantwo pins. The second is related with the proximity between pins. There is no sense toperform a test for determining a short between two pins that are not adjacent. Figure 4.1depicts clearly this situation.Figure 4.1: Proximity of two or more pins [9].Open: a pin that is not connected to its board node pad, showing infinite impedancebetween the pin and the node pad [9].Joint Quality: this property is related with the solder between the pin and the node pad(i.e. excess solder, insufficient solder, poor wetting, voids, etc.) [9].The properties of the model have been explained, now is possible to describe how itgenerates the test coverage. In accordance with the authors of this standard for modeling,each device and connection property contributes to the coverage unless it is irrelevant26

(for instance, the orientation of a non-polarized device like a resistor fits in thisdescription).A device is considered as fully tested only when its presence, orientation, correctness,live and alignment are completely verified and only when for every pin, there is fullcoverage for shorts, opens and joint quality [9]. Some test methods lack of means toverify the properties which lead to deviations.4.1.2 MetricsMetrics are divided almost in the same way than the properties, except because there is athird division. This one is comprised for the metrics that apply to both, devices andconnections (metrics scale and board score).4.1.2.1 Metric ScaleBecause it is desirable a comparison between boards, the coverage’s figure should bescaled. Since nowadays the boards have hundred of devices and thousands of connections,each device and connection contributes with a small amount of coverage. A large numberRange (100,000 is proposed by the authors) is used for scaling the individualcontributions [9].4.1.2.2 Board Score (BS)This metric is given by a couple of numbers used in order to represent the devicecoverage and connection coverage BS (BDS, BCS). These numbers can be as high as thevalue assigned to Range. This figure means perfect board coverage, while untestedboards have a BS of 0 [9].4.1.2.3 Device MetricsThe next step is to define the device metrics. Important of emphasizing is that any of thedevice properties may be verified by more than one test method. In this sense if one testprovides a result of partially tested score while another gives a fully tested score, the27

procedure is to take the maximum value generated by the tests which in this case is fullytested [9].4.1.2.3.1 Device Property WeightsThere are two considerations that shall be taken regarding the weight allocation. The firstis that properties are not compelled to have the same weights; the only condition is thatthe sum of these shall be 1.0. The second is that the device properties weights (dpw) arenot necessarily the same for the different sorts of devices.For instance and as aforementioned, orientation property does not provide any valuableinformation for a resistor and therefore its weight allocation is 0.0. On the other hand,diode’s orientation is rather important and hence a weight to this property shall beassigned [9].An example of weights assignation is presented in table 4.1. It is important to mentionthat even though alignment is not possible to verify by ICT, 0.1 is allocated to thisproperty. Taking into account that the range’s upper limit is 100,000 for full coverage inthis study case, the maximum coverage that is possible to achieve by the ICT is 90,000[9].Device TypePresence Correct Orientation Live Alignmentdpw(P) dpw(C) dpw(O) dpw(L) dpw(A)Resistor 0,3 0,3 0 0,3 0,1Capacitor (non-polarized) 0,3 0,3 0 0,3 0,1Capacitor (polarized) 0,225 0,225 0,225 0,225 0,1Diode 0,225 0,225 0,225 0,225 0,1Digital IC 0,225 0,225 0,225 0,225 0,1Table 4.1: Example of weight allocation.Therefore it is necessary to combine the ICT with another test method such as AutomaticOptical Inspection (AOI) in order to attain the desired 100% test coverage. This methodprovides a mean to cover the last 10,000 points, as well as presence, correct andorientation properties, but not live property. Therefore the test coverage of AOI in thisexample is 70,000.28

4.1.2.3.2 Device Property ScoreThe grades proposed by the authors are untested, partially tested and fully tested. Theirrespective values are 0, 0.5 and 1.0. Then, the device property score for a component typet (where t could be a resistor, capacitor, etc.) is written as dps(P), dps(C), dps(O), dps(L),dps(A) respectively [9], where the capital letter inside the parenthesis represents theproperty being evaluated.A concept that shall be introduced is Raw Device Score (RDS) which is the scoreproduced by each component of the device type t (i.e. score of each resistor, capacitor,etc.) and shall be always equal or less than 1. The RDS is calculated with the followingequation:RDS( t)dps(P)*dpw(P) dps(C)*dpw(C) dps(O)*dpw(O) dps(L)*dpw(L) dps(A)*dpw(A) (4.1)In order to increase the reliability in the assessment of test coverage is important toallocate the adequate weight to each type of device. For instance, if the board has 1,000resistors which have a failure rate of 100 part per million (PPM) and 100 digitalcomponents (average pin count 500) with 5,000 PPM failures it is imperative to weightheavily the ICs rather than the resistors [9].There are two algorithms that could be followed for assigning the weights to thecomponents. One is to normalize the device type failure Pareto diagram onto a unit (1.0)of weight. Another approach would be to use a uniform distribution when no failurehistory is available [9].4.1.2.3.3 Population Adjusted Device Type WeightsOnce a strategy has been developed for a given board, it is desirable to use this one foranalyzing test coverage in other boards (even if these have a completely different design).Thus, it is necessary to adjust the device weight in case of absence of a component (i.e.based on table 4.1, let establish the case were there are no diodes, but all other devices arepresent). This redistribution is done following these steps:29

N is the total number of components. n(t) is the population of device type t. dw(t) is the device type weight of the device type t. Notice that the sum of alldw(t) shall be 1.0. Then the device weight adjuster A for all t, is sum[n(t)*dw(t)/N] [9].4.1.2.3.4 Board Device ScoreThe device score DS(t) of a given device t is obtained from the raw device score, thechosen range and the device weight adjuster A as follows:RDS(d) * Range*dw(t)DS(d) (4.2)A*n(t)In order to obtain the contribution generated by the devices of type t tested, it is necessaryto sum the individual contribution of each of them. Thus, the board device score BDS issimply calculated as the sum of the device scores:BDSnt1DS( t)(4.3)Where n is the total amount of components of type t verified by a given test method. Thevalue of the total BDS will vary from 0 (no devices have any property scores) to Range(all devices have perfect property scores) [9].4.1.2.3.5 Maximum Achievable Device ScoreIt is possible to evaluate the maximum device property score for any device t that can beachieved theoretically; this value is the maximum achievable device score. Examples ofthis metric are shown in tables 4.2 and 4.3.As seen in the tables, the estimation of what can be covered by a specific tester is easilydone by filling these with full, partial, untested and not apply (NA), depending onwhether the test can verify the property or not and regardless considerations such as the30

testability of a low-valued capacitor in parallel with a large-valued capacitor or if a givenIC label is being obstructed by another component such as a heat sink mounted over it [9].Test Type P C O L AICT Full Partial (NA) Full Not TestedAOI Full Full (NA) Not Tested FullAXI Full Not Tested (NA) Not Tested FullTable 4.2: Maximum theoretical dps versus test method for a resistor.Test Type P C O L AICT Full Partial Full Full Not TestedAOI Full Full Full Not Tested FullAXI Full Not Tested Full Not Tested FullTable 4.3: Maximum theoretical dps versus test method for a digital component.This theoretical information becomes useful when analyzing how good a test method isand where is profitable put an effort to improve coverage. It is also possible to use theboard device score equation with this theoretical value for finding out what is the highestcoverage that might be achieved by a specific tester [9].4.1.2.4 Connection MetricsThis section follows the same strategy used in section 4.1.2.3. Therefore, a connectionproperty could be verified by different test methods and the highest grade obtainedamong the testers is the one that will be used for test coverage analysis purposes.4.1.2.4.1 Connection Property WeightsThe properties of a connection as mentioned before are Short (either to ground/battery orto adjacent pins), Open and Joint Quality. Taking into consideration the importance ofeach of these properties, a weight is allocated to these.An important statement is that zero or more shorts may exist in any connection.Therefore, it is important to adjust the weight given to this property based on the totalamount of shorted connections. The adjustment is done by taking the weight assigned to asingle short (0.4 in this instance) and in case of no shorts, adding this one to the open31

property. Otherwise, the assigned weight is redistributed among the number of shortedconnections s. This is exemplified in table 4.4 [9].PropertyShortcpw(S)Opencpw(O)Qualitycpw(Q)Weight(s=0) 0 0,9 0,1Weight(s>0) 0,4/s 0,5 0,1Table 3.4: Example of weight allocation.Retrieved from table 4.4 is that the sum of the cpw shall be always 1.0 and the propertyquality has a weight of 0.1. In this case, the maximum score that could be produced by anICT is 90% of the total, because this sort of test lacks of means to determine joint quality[9].4.1.2.4.2 Connection Property ScoreAs in device property score, the connection properties could be qualified as untested,partially tested and fully tested. The respective value assigned to these scores is 0, 0.5 and1.0. Hence, a connection property score for connection c is written as cps(JS), cps(JO)and cps(JQ) respectively.A connection score for a given connection c CS(c) is found by using the followingequation [9]:CS( s) cps(JS) * cpw(JS) cps(JO) * cpw(JO) cps(JQ) * cpw(JQ)(4.4)4.1.2.4.3 Board Connection ScoreOnce the connection scores are calculated, it is possible to assess the board connectionscore as:BCSnc0CS( c)(4.5)Where n is the total amount of connections verified by a given test method [9].32

4.1.2.4.4 Maximum Achievable Connection ScoreAn important figure to have in mind is the maximum theoretical connection test coveragethat could be achieved by the different test technologies. This information is shown intable 4.5. It is necessary to mention that it does not take into account practical limitationssuch as parallel power connections on ICs, undetectable by ICT or joints hidden underBGAs that are not seen by AOI [9].Test TypeShortcpw(S)Opencpw(O)Qualitycpw(Q)ICT Full Full Not TestedAOI Full Full FullAXI Full Full FullTable 4.5: Maximum theoretical cps versus test method.4.1.2.5 Method’s ModificationsSome adjustments and modifications to the standard of modeling were implemented inorder to achieve a reliable result. These are explained in the next subsections.4.1.2.5.1 Device WeightThis is a metric that is mentioned but not defined during the method explanation and isvery important to generate a result. It is defined as the contribution that each type ofdevice mounted on the PCB will afford to the test coverage.In order to assess this figure, three parameters are taken into consideration. The failurerate (FR), the part per million (PPM) failures and the quantity of components of thedevice type t placed over the board.4.1.2.5.1.1 Failure RateThe failure rate is the frequency with which an electronic component fails, expressed infailures per hour [20]. This number is obtained directly from the company that suppliesthe device and in most of the cases is given in FIT (failure in time) with units in: expectedfailures per one billion hours.33

The device type t could be provided by several companies and therefore several failuresrates are obtained. Examples of this statement are the resistors, since not all of them arenecessarily provided by the same supplier.Other instance is the devices of type t supplied by the same company that have differentcharacteristics. For example, if there are capacitors which belong to the X7R family andcapacitors of the C0G family, two different failure rates are provided.In both cases, a weighted failure rate shall be calculated. This one is found by using thefollowing equation:c1d( t)c2d(t)cnd(t)FR( t) * FR1( t) * FR2( t) ... * FRn( t)(4.6)D(t)D(t)D(t)Where c x d(t) is the amount of devices supplied by the company in the sub index, FR x (t) isthe failure rate provided by the company in the sub index and D(t) is the total amount ofcomponents of the device type t. Notice that the sum of all c x d(t) shall be equal to D(t).This equation is also used in the case where only one company supplies the devices oftype t.4.1.2.5.1.2 Part per Million (PPM) FailuresIn the case where data from previous tests performed to the PCB under analysis isavailable, the calculation of this number becomes possible. It is the amount of faultycomponents found after testing the circuit.4.1.2.5.1.3 Quantity of ComponentsIt is the total amount of components of the device type t mounted on the board (i.e.quantity of resistors, capacitors, ICs, etc.).4.1.2.5.1.4 Device Weight AllocationThe following equation is used for assessing the device weight:34

dw t) ( FR(t) * w ) ( PPM ( t) * w ) ( Q(t) * ) (4.7)(1 2w3Where FR(t) is the failure rate, PPM(t) is the part per million failures, Q(t) is the amountof components of the device type t and w x is an assigned weight to each one of theparameter and whose sum is 1. Also, it is important to verify that the sum of the deviceweights is 1.4.1.2.5.2 Device Property Weight AllocationIn order to assign the weights of the different properties, there are two parameters whichcould be taken into account: defects found during previous round tests (when thisinformation is available) and a device fixed weight for each property.The information regarding failures found during previous tests is classified in thedifferent properties and based on this classification; a failure ratio related with eachproperty is generated. For instance, a fault such as component missing is classified in thedomain of the presence property. This failure ratio is given by the following equation:dF(x)dfr( x) (4.8)dTFWhere x is the property whose failure ratio is being determined, dF(X) is the quantity ofdevice’s defects related with the property and dTF is the total amount of device’s defects.Also, this last term is the sum of the quantity of fails related with each property. With thedevice failure ratio and the device fixed weight is possible to calculate the deviceproperty weight as the mean value of the mentioned parameters, as the followingequation states:dfr(x) dfw(x)dpw(x) (4.9)2In the case where previous data is not available, the dpw is simply the device fixedweight (dfw), as shown in equation 3.10.dpw( x) dfw(x)(4.10)35

4.1.2.5.3 Board Device ScoreSection 4..1.2.3.4, specifically equation 4.2, describes how to obtain the device score orindividual contribution to the test coverage of each component of the device type t (i.e.each resistor, each capacitor, etc.).In the indicated equation, the term A (device weight adjuster) is used just for introducingan adjustment. Therefore, for the final calculation in this project, the value of this term istaken as 1.4.1.2.5.4 Connection Property Weight AllocationAs well as in section 4.1.2.5.2, the assessment is done based on two parameters: previousdata (when it is available) and a fixed weight. Following the same methodology, thedefects are classified in the different properties (e.g. missing solder dot is classified in thedomain of the open property) and the connection failure ratio is found as stated inequation 4.11.cF(x)cfr( x) (4.11)cTFWhere x is the property whose failure ratio is being determined, cF(X) is the quantity ofconnection’s defects related with the property and cTF is the total amount of connection’sdefects.In order to find the connection property weight, the mean value of the connection failureratio and the connection fixed weight is used. Hence, the connection property weight isgiven as:cfr(x) cfw(x)cpw(x) (4.12)2If data from previous test rounds is not available, the connection property weight issimply the connection fixed weight.cpw( x) cfw(x)(3.13)36

4.1.3 Circuit AnalysisAs aforesaid, there is a major division at the structural level of a printed circuit board:devices and connections. The analysis of the functionality of each device that comprisesthe circuit under study is necessary in order to determine which components could beverified during the performance of the different tests.A printed circuit board is composed by active and passive components. This is the firstdivision done over the devices that are mounted on a PCB. Actually, the circuit analysisbegins with the classification of the components as active or passive.In most of the cases, a tester can find a misplaced, wrong oriented and even a damagedactive device, is not the same for the correct value of the component, because it could bea similar component (e.g. a transistor with almost the same features or the tolerance of aresistor or a capacitor).In the case of passive components, special emphasis on their verification shall be put,since some of them might not be checked during the performance of a functional test (orany other test). For instance, components used to protect integrated circuits from overvoltages.Both active and passive devices, for this study, are subdivided in two main categories:components whose presence is completely necessary for the correct function of the boardand components whose lack of presence could lead to a malfunction, but only underspecific circumstances (this sort of devices might not be detected by a functional test). Inthe former category is common to have most of the active devices, while the latter isusually comprised by passive devices.Since there are components that when missing, lead to the destruction of other devices orin certain cases even the destruction of the whole circuit, a final subdivision is necessaryto be defined. This one is done over the components that might lead to a malfunction ofthe PCB.37

In order to avoid the partial or complete destruction of the circuit, it is important to have afull coverage of these devices and to ensure not only that are being tested, but also thatare working properly.Figure 4.2 shows the different divisions of the devices which compose a PCB.ComponentsActivePassiveLeads tomalfunctionMight not lead tomalfunctionLeads tomalfunctionMight not lead tomalfunctionDestroys otherdevicesDoes not destroydevicesDestroys otherdevicesDoes not destroydevicesFigure 4.2: Components division.A list taking into consideration the divisions stated in figure 4.2 shall be generated inorder to provide a general view of the critical and uncritical devices.Previous paragraphs introduce concepts for classifying the devices that comprise a circuitin order to discriminate which test strategy will verify them. Analysis of the connectionsshall be done, with the same purpose than the device’s analysis.In general, it could be said that a short circuit will be found with ease, but is not the samefor an open circuit. The device’s analysis shows that an open circuit will not be found ifthe component could not be checked by a given test technology. For instance, thedecoupling or bypass capacitors are placed in parallel one regarding other. Consideringthat several ICs have this sort of capacitors, the measured capacitance will not varysubstantially if one of these is missing or in this case, if there is no connection at all,although the component is placed.38

Other typical circumstance is the verification to the connection of the ICs’ pins. Toexemplify this situation, an IC is determined as alive, but it does not mean that all theconnections are checked in order to conclude it.Regardless of the test method, the former case is easy to forecast whether the componentconnection is verified or not on its open property. The latter instance requires a deeperanalysis for discriminating which connections are checked and which are untested by thetests applied to it.The most critical situation that could be found is a connection in a microcontroller orFPGA in a pin whose functionality or live property is not being verified by any of thestructural or the functional tests. The mentioned analysis shall point out these cases.Nowadays, most of the components are surface mounted. However, there are somecomponents which use through-hole technology. Due to the complexity of the circuit’sdesign, these devices often present connections in both sides of the board. Theseconnections shall be taken into account in the allocation of the individual contribution tothe board connection score. Also, these shall be verified.4.1.4 Test Method RequirementsOnce the standard for modeling PCOLA/SOQ has been described as well as the strategyfollowed for allocating the weights to the properties and devices, the next step is todetermine the test coverage achieved by the different tests performed on the circuit. Asexplained before, only the combination of tests leads to the goal of 100% test coverage.ICT is the most common test applied to a PCB, although the complexity of the circuit’sdesign is increasing and hence the probe of some devices becomes difficult or evenimpossible. Actually, this one is performed for every produced circuit, early in theproduction process (after circuit manufacture) and is intended for finding most of thefaults. Due to its limitations (exposed when the method was explained) some devicesmight not be checked by this verification method.39

A complete list of the verified components shall be provided, including the upper andlower limit values used, when those apply. Also, an explanation of the devices notverified shall be given; even though the reason why some components are not tested isclear, there are some whose explanation is not obvious.Other common test applied to the PCB is the visual inspection (either HVI or AOI).When performed, as well as in the ICT, a list of the verified components shall beprovided. The same requirement applies for the BST and AXI, in the instance when theseare executed.Although the direct purpose of a functional test is not to verify the presence of acomponent (actually, its purpose is discussed later in this document) it is possible to findif a device is placed and correctly oriented (when applies) or not, thus contributing toincrease the structural test coverage.In most of the cases, a functional test can find a misplaced, wrong oriented or damagedactive device, obviously depending on the function that it has in the circuit. In the case ofpassive components, some of them might not be verified during the performance of afunctional test, due to their function. A good example of this are the decoupling or bypasscapacitors situated in most of the ICs. Therefore, the analysis of the functionality of eachdevice, explained in section 4.1.3 becomes useful.After completing the analysis, it is necessary to probe that the components whosepresence in the board can not be determined when performing a functional test, indeedare not found. This is done by removing each component (one at a time) and executingthe functional test.The list of devices that have not caused a malfunction after performing the functional testis very important, because those shall be checked by another test method in order toproduce the highest test coverage qualification.40

4.2 Functional Test Coverage AnalysisThe authors of the method defined for analyzing the test coverage done over the structureof the board, also created a method to analyze the functional test coverage. This one, asmentioned in section 2 is based on the following properties: Feature, At-speed, Inparalleland Measurement.Though the properties are mentioned, it was not possible to find an explanation of theseor how the method is applied, after an exhaustive research. However, the test coverage isdirectly related with the implementation of requirements.In order to understand how the test coverage is assessed, it is important to focus thedefinition of functional test to the production process. Functional test, in section 3.3, wasdefined in a general manner, regardless of the product’s stage.During the development process, a functional test is created for verifying the properfunctionality of the product. The test (or set of tests) is generated based on the documentwhich describes the tasks that the product shall perform. This product definitiondocument contains the requirements (either from the customer, internal or both) in whichthe product’s design is based. This sort of test is not executed over all the produced PCBs,but over a prototype and is intended to find any possible issue generated by the hardware,software or firmware design.On the other hand, during the production process, the functional test is intended to verifythe proper functionality of each of the devices mounted on the circuit board, having aspecial effort over the active components whose functionality is given by severalcharacteristics, besides its correct value, orientation, among others. This sort of test isapplied to all the produced circuits.The importance of such a test is explained by the inherent limitations of the ICT andother tests performed to the PCB. The property live, defined in section 4.1.1.1, statesclearly that the components are widely functional, but it does not mean that are fully41

functional. For instance, in the case of active components such as IC’s that often have tocomply with response in time, it is not possible to check this feature with an ICT or avisual inspection (either human or automated).Regarding the tests applied to the board in order to verify its structure, these cannotprovide a full functional check of the specification of the board. As the board is not beingexercised in its operational mode, its operational parameters cannot be checked.The tests performed over the board’s structure are developed based on the schematics,board’s layout and list of components. The latter document provides the values,tolerances, power and voltage ratings of the devices mounted on the PCB, while theformer documents state the placement and orientation of the components.The tests intended to verify the board’s functionality are developed based on functionalrequirements. This is an internal document which states how the devices shall behave.For instance the response in time that a comparator shall exhibit due to a specificstimulus. Other example is the output voltage from a voltage divider, this one is relatedwith passive components.The requirements contained in the mentioned document shall comply with thecharacteristics and components of a well-written requirement, defined in sections 3.4.1and 3.4.2, respectively.In order to keep traceability, a requirement traceability document is created. This onecontains all the requirements, the test performed to verify it and the result of the test(either pass or fail).As long as all the requirements contained in the document are verified by a test or set oftests, there is full test coverage. It is important to emphasize that each requirement has thesame weight and therefore it is easy to estimate the test coverage in case that one or morerequirements are not verified or implemented in the functional test.42

Due to the last statement’s implications, a couple of declarations are crucial for thereliability of the result. The first is related with the requirements, its accuracy in thedefinition of what the components shall do and how these shall behave is rather important.If the requirements are not written correctly under the rules given in sections 3.4.1 and3.4.2 there might be useless or unverifiable requirements, among other issues.The second declaration is regarding the functional test developed. This shall bethoroughly reviewed in order to ensure that it is actually testing the requirement orrequirements for which it was designed. Also, it shall describe clearly the pass/failcriteria.If both declarations stated in the previous paragraphs are taken into consideration, theachieved result is reliable. A product’s quality is as good as the document describing it.The same applies to the functional test quality.43

5 Method ApplicationA description of how to apply the method in order to calculate the test coverage attainedover both, structure and functionality of the board, is given in this section.5.1 Structural Test Coverage AnalysisThe Gate Drive Unit (GDU) DYTP 150A was chosen as the PCB in which the method isapplied. This circuit is comprised by 324 devices and 1271 connections. The list ofcomponents is shown in table 5.1.Component QuantityAnalog Circuit 16Capacitor 92Connector 7Digital Circuits 12Diode 44Filter 1Inductor 6Oscillator 1Resistor 129Transformer 1Transistor 15Table 5.1: GDU Components.5.1.1 MetricsThe allocation and assessment of the metrics used for evaluating the test coveragegenerated by the different test technologies is presented in the following subsections,including an explanation of the modifications done in order to achieve a reliable result.These are divided in general metrics, device metrics and connection metrics as explainedin section 4.1.2.5.1.1.1 Metric ScaleBased on the information given in section 5.1, a Range of 10000 is chosen. This figure islarge enough to give a good idea of the contribution that each component and connectionaffords to the board device score and board connection score, respectively. Perfect testcoverage for any of the board’s scores is 10000.44

5.1.1.2 Device MetricsThe device metrics are obtained from data provided by the suppliers of the differentcomponents (failure rate), information taken from previous test rounds (part per millionfailures and reason of the failures) and the circuit’s design (schematics, layouts andcomponents).5.1.1.2.1 Device WeightThe allocation of this metric was done based on the three parameters described in section4.1.2.5.1, since information from previous tests was available.5.1.1.2.1.1 Failure RateThe failure rate was provided by the suppliers of the components. In some cases, thisfigure is found in the web page of the company which provides the device, generally inthe link of reliability or quality. In most cases, the information is not of public access andit is necessary to request it directly to the company.In order to find the failure rate for the different components listed in table 5.1, the methodproposed in section 4.1.2.5.1.1 was followed. The list of the failure rate for analogcircuits and their weighted FIT is shown in table 5.2.Company Component Quantity FITAnalog Devices AD1582CRT 1 1Linear Technologies LT1376IS8 4 0,81Maxim MAX978EEE 3 6,793EST122-991 1 -Selmic3EST122-992 1 -3EST122-986 1 -STMicroelectronics TS3704IDT 2 7,4Texas InstrumentsUCC2808 1 13,3TPS6200XDGS 2 0,5Weighted FIT4,287Table 5.2: Failure Rate of Analog Circuits.In table 5.2, components provided by Selmic do not have a failure rate assigned. Thesedevices are produced specifically for the GDU and therefore no reliable figure related45

with the failure rate could be given, because of low production volume. In this instance,this value was calculated as the mean of the FITs of the analog circuits, which is 4.97.Table 5.3 contains information of the failure rate for the capacitors placed on the board.Due to the type of capacitor, Sanyo does not provide the FIT for X7R or C0G.Type of CapacitorCompany Quantity X7R FIT Quantity C0G FIT Quantity Other FITAVX/Kyocera 3 0,11 0 0,05 - -Epcos 27 0,07 0 0,05 - -Kemet Electronics 40 1 2 0 - -Murata 3 6 - - - -Yageo 2 1,21 1 1,05 - -Sanyo - - - - 14 19,2Weigthed FIT 3,614Table 5.3: Failure Rate of Capacitors.The failure rate of the connectors is given in PPM failures instead of FIT. Due to the sortof component, the defects that could be found are mechanicals; therefore, the FIT, is not anumber typically calculated. In the device weight's assessment, the failure rate used is 0,because the faults are mechanicals rather than electrics. Information is shown in table 5.4.Company Component Quantity PPMFCI 75869-101 1 25SAMTEC FTSH-105 3 500WAGO 231-538/101-000 3 -Table 5.4: Failure Rate of Connectors.The digital circuits’ failure rate is shown in table 5.5. The FIT presented for thecomponent HFBR-2528 as explained by the company which provides it, the figure isinflated toward the high side due to limited device hours. However, the supplier states aFIT lower than 100 which was used for the weighted FIT’s calculation.AlteraCompany Component Quantity FITEPM240T100I5 1 16,10EP1C3T144I7 1 29,50Avago Technologies HFBR-2528 1 14760,00Fairchild 74ACT245MTC 5 9,10Philips 74LVC244ABQ 3 4,40STMicroelectronics M25P20-VMN3T 1 0,13Weighted FIT16,952Table 5.5: Failure Rate of Digital Circuits.46

Diodes’ information related to the failure rate is presented in table 5.6. The FIT of theHFBR-1528 follows the same explanation given in the previous paragraph. In the case ofthe EL17-21, this is a light emitting diode (LED), the supplier of the component does notperform any test to determine the failure rate; instead the life expectancy was provided, afigure that was not taken into account for the weighted FIT calculation.Company Component Quantity FITAvago Technologies HFBR-1528 1 14760,00Everlight EL17-21 6 -BZX84C12 1 5,20FairchildBZX84C10 3 5,20BAV99 3 5,20On SemiconductorP6SMB27AT3 3 1,38MURS220T3 12 10,27BZX84-B12 1 3,29BZX84-B16 1 3,29PhilipsBAT54 1 6,00BAW56 2 5,60BAT54S 2 6,00LL4148GS08 4 3,00VishayP6SMB16CA 1 1,00ES07B 3 3,00Weighted FIT5,988Table 5.6: Failure Rate of DiodesThere is only one filter mounted over the board. Therefore, the failure rate is directly thenumber given by the supplier, in this instance 0.5 FIT.Although inductors on the PCB are 6, all of them are provided by the same company andhave the same value. Therefore the failure rate is the figure given by the company: 10FIT.The same situation explained for the filter applies to the oscillator, whose failure rate is104 FIT.The resistors are divided in several categories or families, depending on the company.The failures rates given in table 5.7 correspond to the different families of resistorsmounted on the board, rather than specific component’s number.47

Company Component Quantity FITSR733A 1 0,014Koa Speer Electronics RN732A 2 0,010RK73H1 7 0,001YageoRC1206 34 72,000RC0603 83 66,000Vishay MMA0204 2 0,050Weighted FIT65,443Table 5.7: Failure Rate of ResistorsThe failure rate calculated by the supplier for the transformer is 213 FIT, the largestfigure among the devices. The transformer represents a special case, this component isnot only manufactured specially for the GDU, but also the design is a patent ofBombardier Transportation. Due to these reasons, the production volume is rather low aswell as the tested hours of this component. These factors influence directly in theassessment of the FIT, explaining in this manner the rather high failure rate.Despite the high failure rate, the device’s quality is considered as the best among thetransformers. The materials used to build it have the highest quality and it is designed insuch a way that provides the best performance. Hence, the failure rate used for the deviceweight’s calculation was 0 FIT.The transistors’ failure rate is shown in table 5.8. Information provided by Philips wasuseless in most of the cases, since they reported the PPM failures instead of the FIT. Dueto this situation, information supplied by Fairchild was used for the calculation, exceptfor the PHT6N series and the PMGD280UN.Company Component Quantity FITInfineon BSP170P 1 6,825BCX70H 2 5,700BCX71H 2 4,060PhilipsPHT6N0 1 11,000PHT6NQ 3 11,000PMGD280UN 2 16,000Vishay ES07B 1 0,520Zetex FMMT720TA 3 0,863Weighted FIT7,030Table 5.8: Failure Rate of Transistors.48

5.1.1.2.1.2 Part per Million (PPM) FailuresThe data used for assessing this parameter was taken from the failure report lists providedby ENICS. The analyzed information belongs to 5 months of tests, because no furtherdata was available. During this period of time 1662 boards were verified, finding 36defects related to the functionality of the components. The devices that presented faultsare listed in table 5.9.In order to calculate the PPM failures is necessary to know the total amount of devicestype t that were tested. This information is presented in table 5.9, as well as the PPMfailures.Component Tested Failures PPMAnalog Circuit 26592 12 451,26Capacitor 152904 5 32,70Connector 11634 0 0,00Digital Circuits 19944 0 0,00Diode 73128 5 68,37Filter 1662 0 0,00Inductor 9972 4 401,12Oscillator 1662 4 2406,74Resistor 214398 2 9,33Transformer 1662 0 0,00Transistor 24930 4 160,45Table 5.9: PPM Failures by component.It is possible to observe in table 5.9 that oscillator’s PPM failures is the highest,something that was expected due to its high failure rate.5.1.1.2.1.3 Assigned Weight W xBefore calculating the device weight, a final consideration shall be mentioned. Theallocation of the weights to the different parameters is done based on the importance ofthe parameter and on the reliability of the data.Following the last statement, the amount of components is a constant number, atrustworthy figure. Therefore, the highest weight is assigned to this parameter: 0.5 from atotal of 1.49

The failure rate is provided by the supplier of the component, a number that is found aftertesting several units of the same sort of components, during a well defined period of time.Thus, this is a reliable parameter and therefore 0.4 was assigned to it.The last parameter (PPM failures) is a number obtained from the analysis of 5 months oftests, which might not represent a real tendency or pattern of defects. Due to this fact, theconfidence on this information is not as high as in the other parameters, assigning to it aweight of 0.1.5.1.1.2.1.4 Device Weight AllocationThe device weight is assessed with the information provided in sections 5.1.1.2.1.1,5.1.1.2.1.2 and 5.1.1.2.1.3 and data presented in table 5.1. For the calculation of thisfigure, equation 4.7 is used and the results are shown in table 5.10.Component FIT PPM Amount dwAnalog 4,29 451,26 16 0,0913Capacitor 3,61 32,70 92 0,0845Connector 0,00 0,00 7 0,0058Digital 16,95 0,00 12 0,0213Diode 5,99 68,37 44 0,0520Filter 0,50 0,00 1 0,0012Inductor 10,00 401,12 6 0,0785Oscillator 104,00 2406,74 1 0,4709Resistor 61,44 9,33 129 0,1499Transformer 0,00 0,00 1 0,0008Transistor 7,03 160,45 15 0,0439Table 5.10: Device Weight.Analyzing the data presented in table 5.10, it is easy to determine that almost the half ofthe device weight is assigned to the oscillator, due to its features (FIT and PPM). Theassignment of these weights will lead to error in calculations; hence an adequateallocation is important.The second proposal is to assign directly 0.05 of the device weights (always 1) and todistribute the remaining among the other components. Following this strategy and usingthe equation 4.7, the new device weights are shown in table 5.11.50

Component FIT PPM Amount dwAnalog 4,29 451,26 16 0,1640Capacitor 3,61 32,70 92 0,1516Connector 0,00 0,00 7 0,0105Digital 16,95 0,00 12 0,0382Diode 5,99 68,37 44 0,0934Filter 0,50 0,00 1 0,0021Inductor 10,00 401,12 6 0,1409Oscillator 104,00 2406,74 1 0,0500Resistor 61,44 9,33 129 0,2691Transformer 0,00 0,00 1 0,0015Transistor 7,03 160,45 15 0,0788Table 5.11: Adjusted Device Weight.5.1.1.2.2 Device Property Weight AllocationAs mentioned in section 4.1.2.5.2, the assignment of weights is done based on previousinformation regarding defects (when it is available) and a fixed weight. In this instance,data from previous tests was gathered, analyzed and classified. Table 5.12 shows thefaults found and to which property these belong, indicated by the capital letter in thecolumn property.Failure Property FailuresComponent fell down P 5Not observed P 4Fail looking for component P 10Component pin not throuh P 1Missing Component P 51Wrong Component C 538Other assemble C 6Wrong Orientation O 8Function failure L 26Function during Burn-in L 2Component pin bended L 2Component package damaged L 6Component pin damaged L 3Cracked component L 1Inclined Component A 10Table 5.12: Device fault reason.Once the failures have been classified in the different properties, the percentage of thesecould be determined. This information is shown in table 5.13 for the cases where theproperty orientation applies and does not apply.51

Property Failures Percentage Property Failures PercentagePresence 71 10,55% Presence 71 10,68%Correct 544 80,83% Correct 544 81,80%Orientation 8 1,19% Orientation 0 0,00%Live 40 5,94% Live 40 6,02%Aligment 10 1,49% Aligment 10 1,50%Table 5.13: Failure percentage by property.The fixed weight is assigned as follows: 0.2 for the presence property, 0.05 for thealignment property and the remaining 0.75 is divided equally among the other threeproperties (correct, orientation and live).For the components whose orientation is not a property to take into account (such asresistors and ceramic capacitors), the fixed weight is almost the same than the oneassigned when the orientation is a relevant property, except for the 0.75 which is dividedin two equal parts. Therefore the assignment is 0.375 between the remaining properties(correct and live).In both allocations of fixed weight, presence property is assigned 0.2 because when acomponent is missing, none of the other properties could be tested. In the case ofalignment property, this is a deviation more than a defect and hence, the weight is thelowest.Table 5.14 contains the data related with the device property weights for the depictedsituations, when the orientation is relevant (left table) and when this property is irrelevant(right table). These figures are assessed with the equation 4.9, based on the informationgiven in previous paragraphs.Property Percentage Property PercentagePresence 15,27% Presence 15,34%Correct 52,92% Correct 59,65%Orientation 13,09% Orientation 0,00%Live 15,47% Live 21,76%Alignment 3,24% Alignment 3,25%Table 5.14: Device Property Weights52

5.1.1.2.3 Device Property ScoringAn adjustment to the definition of this metric is necessary in order to increase theconfidence in the achieved test coverage. Due to the type of tests performed to the GDU(explained in next section) the property correct, whose weight is the highest, will neverqualify as fully tested for most of the components. Hence, the grades are the same, butthe value for partially tested changes from 0.5 to 0.755.1.1.2.4 Board Device ScorePreviously mentioned, the highest board device score is the metric Range, in this case10000. The individual contribution of each device placed over the board, actually thedevice score, will produce this metric.In order to calculate this figure, information from table 5.1 and table 5.14 is used as aninput for the equation 4.2. The device score as well as the individual contribution isshown in table 5.15.DeviceDeviceWeigthDeviceScoreAmount ofComponentIndividualContributionAnalog 0,1640 1639,63 16 102,48Capacitor 0,1516 1516,28 92 16,48Connector 0,0105 104,64 7 14,95Digital 0,0382 382,12 12 31,84Diode 0,0934 933,78 44 21,22Filter 0,0021 20,93 1 20,93Inductor 0,1409 1408,54 6 234,76Oscillator 0,0500 500,00 1 500,00Resistor 0,2691 2691,11 129 20,86Transformer 0,0015 14,95 1 14,95Transistor 0,0788 788,02 15 52,53Table 5.15: Board Device Score and Device Score.5.1.1.2.5 Maximum Achievable Device ScoreThe gate drive unit is being tested on its structure by two test methods: ICT and HVI.From the mentioned testers, only ICT is performed over all the produced boards,therefore the maximum achievable device score is calculated for this one but not for theHVI.53

Although Functional Test, as its name proposes, is a method to verify the functionality ofthe circuit, it is also useful to check the devices and connections of the PCB duringproduction and it is the only test that could be performed when the board is in field. Themaximum achievable device score is also estimated for this test method.The maximum achievable device score for the components whose orientation is irrelevant(i.e. non-polarized capacitors, inductors and resistors) is 0.84 from a total of 1 for both,ICT and FT, since Alignment is not verified by these methods and the correct property isnot fully verified.In the case of devices which orientation contributes to the coverage (i.e. ICs, diodes,transistors, oscillator and transformer), this metric is 0.82 for ICT and FT. Also alignmentis not covered, due to the lack of means to test it. Correct property is not fully tested.5.1.1.3 Connection MetricsThe following subsections explain the criteria used in order to determine the differentmetrics that apply to connections.5.1.1.3.1 Connection Property Weight AllocationThe assignment of the weight for the different properties which apply to the connectionsis done following the strategy described in section 4.1.2.5.4. Since information from pasttests is available, this parameter is taken in consideration. The failure reason and theamount of fails found in connections were classified and are listed in table 5.16.Failure Property FailuresShorted pins S 28Missing solder dot O 36Insufficient Solder Q 5Other soldering issues Q 2Table 5.16: Connection failure reason.Based on the information provided by table 5.16, the connection failure ratio is calculated,using the equation 4.11. Results are shown in table 5.17.54

Property Failures PercentageShort 28 39,44%Open 36 50,70%Joint Quality 7 9,86%Table 5.17: Connection Failure Ratio.The connection fixed weight assigned to the short property is 0.4, because is not the mostcommon defect regarding solder, present in a PCB. Open circuit is the most commondefect and therefore the connection fixed weight allocated to this property is 0.5. JointQuality has the remaining 0.1. In order to assess the connection property weight, theequation 4.12 is used and the results are shown in table 5.18.Property PercentageShort 39,72%Open 50,35%Joint Quality 9,93%Table 5.18: Connection Property Weight5.1.1.3.2 Board Connection ScoreHighest board connection score is the metric Range. The connection score or theindividual contribution of each tested connection is 7.868.5.1.1.3.3 Maximum Achievable Connection ScoreBased on the information given in section 5.1.1.2.5 about the tests performed, the qualityis a property that could not be verified by the used methods. Therefore .0993 from a totalof 1 is lost. The maximum achievable connection score is .9007 for either ICT or FT.5.1.2 Component AnalysisThe GDU has 47 active devices: ICs, transistors, filter, transformer and oscillator.Regarding passive devices, the circuit has 270 components: capacitors, diodes, inductorsand resistors. Notice that connectors are not taken in consideration.As stated previously, a list of the critical components shall be created. The analysis of thefunctionality of each device generates the list shown in table 5.19.55

Passive ComponentsComponent IDDiodeV63DiodeV7DiodeV87Resistor R20Resistor R50Resistor R22Resistor R48Resistor R71Resistor R82Resistor R280Resistor R109Resistor R105Resistor R103Table 5.19: Critical Components.Due to their purpose on the PCB’s behavior, the devices shown in table 5.19 shall betested and shall work properly. When applies, the orientation shall be checked as well.After analyzing the active devices, it is possible to determine that only one of these whenmissing, will not lead to a malfunction on the board, but a change in the functionality thatwill not be found during a functional test. This device is the V41, an n-channel fieldeffect transistor (FET) that in the case of the PMGD280 is two FETs which are containedin the same package. The purpose of this transistor is to turn on/off the LEDs whichdisplay the board status, as well as the CPLD and FPGA statuses. Transistor V83 has thesame purpose in one of the FETs and therefore will not lead to a malfunction, but thesecond FET in the same package is used to control the receiver’s optic fiber and hence ifmissing, the functionality will change.In the instance of passive components, the analysis is more complicated than the onedone for active components. Therefore, for some devices is not possible to determinewith a simple assessment whether their lack of presence will cause or not wrong behaviorof the circuit.The list of passive components, classified as proposed by figure 4.2 is shown in tables5.20 to 5.35. The information is given in several tables in order to sort the devices by56

functional blocks, making easier the search of these, as well as to provide an idea of theirrelated functionality.DC/DC Supply ConverterMight not lead to malfunctionLeads to MalfunctionDiode V40 Diode V39Capacitor C12 Diode V63*Capacitor C18 Resistor R52Capacitor C35 Resistor R68Resistor R53 Resistor R8Resistor R54 Resistor R76Resistor R40 Capacitor C47Capacitor C87 Resistor R62Resistor R41 Resistor R63Capacitor C88 Resistor R270CapacitorC137ResistorR254DiodeV60DiodeV12DiodeV13DiodeV48DiodeV49DiodeV38DiodeV27DiodeV3DiodeV4DiodeV9DiodeV1Table 5.20: Classification of passive devices.57

Supply Voltage Regulators +5V_P, +15V_P, +17V_P and -15V_PMight not lead to malfunctionLeads to MalfunctionCapacitor C172 Inductor L5Capacitor C10 Resistor R20*Capacitor C53 Resistor R5Diode V17 Inductor L6Resistor R295 Resistor R50*Capacitor C86 Resistor R47Resistor R45 Inductor L3Capacitor C44 Resistor R22*Diode V79 Resistor R2Diode V88 Inductor L4Resistor R294 Resistor R48*Capacitor C7 Resistor R46ResistorR3CapacitorC55CapacitorC56CapacitorC45DiodeV14DiodeV90CapacitorC173CapacitorC8ResistorR23CapacitorC46CapacitorC58CapacitorC59DiodeV15DiodeV89DiodeV20CapacitorC166DiodeV80CapacitorC169DiodeV18CapacitorC168DiodeV19CapacitorC167Table 5.21: Classification of passive devices.58

Supply Voltage Regulators +3V3_P, +1V5_PMight not lead to malfunctionLeads to MalfunctionCapacitor C139 Inductor L8Capacitor C141 Inductor L9CapacitorC160CapacitorC159CapacitorC151CapacitorC150CapacitorC149CapacitorC148CapacitorC147CapacitorC155CapacitorC154CapacitorC153CapacitorC152ResistorR296CapacitorC138CapacitorC140CapacitorC161CapacitorC158CapacitorC146CapacitorC145CapacitorC144CapacitorC143CapacitorC142Table 5.22: Classification of passive devices.Monitoring Collector-Emitter Voltage of IGBTMight not lead to malfunctionLeads to MalfunctionCapacitor C170 Resistor R93Capacitor C171 Capacitor C13Diode V33 Resistor R293Resistor R9 Resistor R94Capacitor C9 Capacitor C14CapacitorC178Table 5.23: Classification of passive devices.59

Monitoring Of Gate-Emitter and Collector-Emitter Voltage of IGBTMight not lead to malfunctionLeads to MalfunctionCapacitor C180 Resistor R95Capacitor C179 Capacitor C15ResistorR34CapacitorC5ResistorR49Resistor R71*ResistorR138ResistorR96CapacitorC16ResistorR97CapacitorC17ResistorR10Diode V7*ResistorR11ResistorR19Resistor R82*Table 5.24: Classification of passive devices.DI/DT Monitoring of IGBT CurrentMight not lead to malfunctionLeads to MalfunctionResistor R42 Resistor R253Resistor R31 Capacitor C133Resistor R6 Resistor R99Capacitor C66 Capacitor C19Diode V42 Resistor R100Resistor R39 Capacitor C20Diode V46 Resistor R90Resistor R1 Resistor R29Capacitor C122 Resistor R140ResistorR110ResistorR36ResistorR16ResistorR35CapacitorC6Table 5.25: Classification of passive devices.60

-15 and +17V Supply Voltage Supervisions and Download ProtectionMight not lead to malfunctionLeads to MalfunctionCapacitor C95 Resistor R65Capacitor C118 Resistor R66Capacitor C96 Resistor R25Resistor R67 Resistor R30Resistor R15 Resistor R83Diode V21 Capacitor C50Capacitor C40 Resistor R58Capacitor C4 Capacitor C11Resistor R232 Resistor R69Resistor R231 Resistor R55Capacitor C94 Capacitor C85Resistor R51 Resistor R33ResistorR21Table 5.26: Classification of passive devices.Supply Voltage SupervisionMight not lead to malfunctionLeads to MalfunctionResistor R278 Resistor R280*Resistor R281 Resistor R279Resistor R107 Resistor R106Resistor R112 Resistor R89Resistor R108 Resistor R38Resistor R136 Resistor R109*CapacitorC25CapacitorC134Table 5.27: Classification of passive devices.Optical Interface Receiver and TransmitterMight not lead to malfunctionLeads to MalfunctionCapacitor C135 Resistor R261Resistor R260 Resistor R271Capacitor C136 Resistor R256Resistor R258 Diode V87*Resistor R259 Resistor R272DiodeV82Table 5.28: Classification of passive devices.61

FPGA Interface 50 MHz ClockMight not lead to malfunctionLeads to MalfunctionResistor R297 Resistor R285Resistor R298 Resistor R269ResistorR289ResistorR288ResistorR287ResistorR286CapacitorC181Table 5.29: Classification of passive devices.FPGA InterfaceMight not lead to malfunctionResistorR282DiodeV37DiodeV93ResistorR283DiodeV92DiodeV43CapacitorC165Leads to MalfunctionTable 5.30: Classification of passive devices.CPLD Interface and Flash MemoryMight not lead to malfunctionLeads to MalfunctionResistorR274ResistorR275CapacitorC182ResistorR276ResistorR299ResistorR300ResistorR284ResistorR301DiodeV94DiodeV91Table 5.31: Classification of passive devices.IGBT Driving Amplifier Turn OnMight not lead to malfunctionLeads to MalfunctionCapacitorC175CapacitorC174CapacitorC41Table 5.32: Classification of passive devices.62

IGBT Driving Amplifier Turn OffMight not lead to malfunctionLeads to MalfunctionCapacitorC162CapacitorC163CapacitorC183CapacitorC177CapacitorC176Table 5.33: Classification of passive devices.Resistive Turn On/Off of IGBTMight not lead to malfunctionLeads to MalfunctionResistor R173 Resistor R105*Resistor R104 Resistor R28Resistor R86 Diode V55Resistor R139 Resistor R102Resistor R169 Resistor R4Resistor R194 Diode V54Resistor R13 Resistor R27Resistor R172 Resistor R103*ResistorR195ResistorR14ResistorR162Table 5.34: Classification of passive devices.Gate Guard and IGBT Gate-Emitter ConnectorMight not lead to malfunctionLeads to MalfunctionResistor R168 Diode V8Capacitor C81 Resistor R130Resistor R167 Resistor R152Capacitor C82 Diode V6ResistorR120CapacitorC54DiodeV45DiodeV36Table 5.35: Classification of passive devices.An important clarification is components with the star to the right are classified as criticaland their presence as well as their correct value and polarity (when this property applies)are necessaries to be tested in order to avoid damage to the PCB. Notice that thesedevices are listed in table 5.19.63

5.1.3 Tested ComponentsSection 4.1.4 states the requirements that each test, when is executed, shall fulfill. One ofthese requirements is to provide a list of tested and untested components, as well as thetolerances used, when these apply.Aforesaid, only ICT and Functional Test are used to verify the board at a structural leveland to comply with this requisite, the mentioned list is provided in the followingsubsections.5.1.3.1 ICT Tested/Untested ComponentsBased on the list of components not tested or tested in parallel with other devicesprovided by Enics, the board device score and board connection score was found. The listof untested components is shown in table 5.36.Device IDDigital Circuit D9DiodeV82Resistor R256Table 5.36: Components not tested by ICT.Capacitors C4, C41, C94, C95, C122, C136, C138, C139, C165, C170, C171, C178,C179, C180, C181, C182 and C183 are placed in parallel with the capacitor C53,between 0V_P and +5V_P. Each one of the former capacitors has a value of 100 nF,while the latter has a value of 56 μF. When the ICT is executed over these components,there is no mean to determine that the devices are there, except for the C53 and therefore,the former capacitors are not being tested.Capacitors C142-C146 with a value of 100 nF and C158 of 1 μF are mounted in parallelwith C161, which has a value of 56 μF, between 0V_P and +3V3_P. Due to the lowcapacitance of the former capacitors, is not possible to distinguish their presence on theboard thus, qualifying as not tested in any of their properties. The same situation appliesto capacitors C147-C155 (100 nF) and C159 (1 μF) placed in parallel with componentC160 (56 μF).64

The configuration of capacitor C25, whose value is 100 pF, is in parallel with C96 andC118, with a value of 1 μF each of them. Due to the low value of the first component, isnot possible to verify it during ICT.In the case of capacitors C45 and C56 placed in parallel with C55, even though theirvalue is the same (82 μF), if one of these is missing, the tester is unable to determine thissituation, due to the boundaries set. The fixtures are placed in such a way that thecapacitor C55 is always tested. Hence the other two capacitors are rated as untested. Thesame explanation applies to devices C58 and C59 which are checked in parallel with C46.From the report provided by ENICS, the polarization of capacitors C12, C18, C44, C45,C46, C53, C55, C56, C58, C59, C160, C161, C172 and C173 is tested for each board byHVI. Properties presence and polarization are covered by this test, but not correct andlive for the capacitors mentioned in last paragraph. All components not mentioned aboveare being tested when the ICT is performed.5.1.3.2 FT Tested/Untested ComponentsAs mentioned before, most of the active components are verified in their presence,orientation and live properties when a functional test is performed. Correct property ischecked but not completely, due to the fact that the device under test might have the samefeatures than the expected component. As stated in section 5.1.2, only the componentV41 is not possible of verifying when this test is executed.In order to prove the last statement, the aforesaid device shall be removed and thefunctional test shall be run. Practically, it is not necessary to remove the component,since this test is covered by the removal of other components. The explanation is givenlater in this section.The remaining step for finding the test coverage achieved by this test method is to knowthe passive components that are not being checked when this one is performed. Theinformation presented in table 5.20 to table 5.35 is used for this purpose.65

Then, components classified as might not lead to malfunction were removed for provingthat these will not be found during the execution of a functional test. Among the deviceslisted in the mentioned classification, some have the same functionality and therefore isnot necessary to remove all of them in order to show that if missing will lead to amalfunction or not, instead just one of these was removed.The information provided from table 5.37 through table 5.52 shows the finalclassification of passive components. Below each of these tables, a list of the removeddevices as well as an explanation of the criteria used to change a component from oneclassification to another is provided.DC/DC Supply ConverterMight not lead to malfunctionLeads to MalfunctionDiode V40 Diode V39Capacitor C12 Diode V63*Capacitor C18 Resistor R52Resistor R53 Resistor R68Resistor R54 Resistor R8Resistor R40 Capacitor C35Capacitor C87 Resistor R76Resistor R41 Capacitor C47Capacitor C88 Resistor R62Capacitor C137 Resistor R63Resistor R254 Resistor R270DiodeV60DiodeV12DiodeV13DiodeV48DiodeV49DiodeV38DiodeV27DiodeV3DiodeV4DiodeV9DiodeV1Table 5.37: Classification of passive devices.Components on the left column of table 5.20 were removed with exception of C12, R53,C87, R41, C88 and V13. C12 is covered by removing C18, which has the same functionin the circuit. The same case applies for R53 with respect of R54, R41 covered by R40,C88 related to C87 and V13 verified with V12.66

In the instance when R40 is removed and the functional test is performed, since it did notlead to malfunction, it has no sense to remove C87 that was in open circuit and also didnot cause any fault. Document 3EST000202-2932 depicts the situation.Comparing table 5.37 against table 5.20 it is possible to see that capacitor C35 wasmoved from classification. When the device was removed, a failure on the PCB’sbehavior was observed. This capacitor is charged through the resistor R8, thus providingwith enough current the IC UCC2808. When this component is not present, the IC is notfed and therefore no voltage is seen in the secondary side of the transformer. Then, nocircuit is supplied.Supply Voltage Regulators +5V_P, +15V_P, +17V_P and -15V_PMight not lead to malfunctionLeads to MalfunctionCapacitor C10 Capacitor C172*Capacitor C53 Inductor L5Diode V17 Resistor R20*Resistor R295 Resistor R5Capacitor C86 Inductor L6Resistor R45 Resistor R50*Diode V88 Resistor R47Resistor R294 Inductor L3Capacitor C7 Resistor R22*Resistor R3 Resistor R2Capacitor C55 Capacitor C173*Capacitor C56 Inductor L4Capacitor C45 Resistor R48*Diode V90 Resistor R46Capacitor C8 Capacitor C44Resistor R23 Diode V79Capacitor C46 Diode V14Capacitor C58 Diode V15CapacitorC59DiodeV89DiodeV20CapacitorC166DiodeV80CapacitorC169DiodeV18CapacitorC168DiodeV19CapacitorC167Table 5.38: Classification of passive devices.67

In the same manner than in last table, not all components in table 5.21 were tested.Capacitors C86, C7 and C8 are covered by capacitor C10, since all of them are bypasscapacitor used in the same type of IC.Resistor R294 was not withdrawn, because it is covered when R295 was taken away,since they are being used for the same purpose.Diodes V80, V18 and V19 are verified by removing diode V20. The same case appliesfor capacitors C169, C168 and C167 that are covered with the removal of capacitor C166.Diode V88 was taken away and hence, diodes V90 and V89 were not tested directly.Also, resistors R45, R3 and R23 were removed.Capacitor C53 was withdrawn and due to the capacitance between 0V_P and +5V_P nofault was produce in the circuit. Also, capacitor C55 (covering the test of C56 and C45)and C46 (related in functionality with C58 and C59) were removed.When C44 was taken away, a failure was found in the PCB regarding voltage supervisionin +15V_P because the ripple in the voltage at the output of the IC was higher than theallowed.The removal of diode V17 led to a failure in voltage supervision. At first sight diodesV79, V14 and V15 shall show the same behavior. However those were withdrawnachieving the same result, as expected.The last component taken away was the capacitor C172, in this case, the ICs A7 and A17were supplied directly with +22V_P. These were destroyed and most probably, also theCPLD. Hence, capacitor C173 was not tested, avoiding the possible damage of the PCB.A comparison between table 5.38 and table 5.21 shows the change in classification of thefollowing components C172, C173, V17, V79, V14, V15 and C44. Moreover, capacitorsC172 and C173 were pointed out as critical component as shown in table 5.53.68

Supply Voltage Regulators +3V3_P, +1V5_PMight not lead to malfunctionLeads to MalfunctionCapacitor C139 Inductor L8Capacitor C141 Inductor L9CapacitorC160CapacitorC159CapacitorC151CapacitorC150CapacitorC149CapacitorC148CapacitorC147CapacitorC155CapacitorC154CapacitorC153CapacitorC152ResistorR296CapacitorC138CapacitorC140CapacitorC161CapacitorC158CapacitorC146CapacitorC145CapacitorC144CapacitorC143CapacitorC142Table 5.39:Classification of passive devices.In the case of table 5.22, most of the devices have the same functionality and therefore,not all of them were removed. Thus capacitor C138 was covered by removing C139.Bypass capacitor C141 was taken away, avoiding the test of C140.Capacitor C160 was removed; hence capacitors C159, C151, C150, C149, C148, C147,C155, C154, C153 and C152 were verified. Capacitor C161 covered the verification forcapacitors C158, C145, C144, C143 and C142. Components C160 and C161 wereselected for being withdrawn, because their value is rather large compared with the valueof the other capacitors placed in parallel.Also, resistor R296 was removed, without causing any malfunction in the circuit behavior.The results for this functional block are no changes to table 5.39 in relation with table5.22.69

Monitoring Collector-Emitter Voltage of IGBTMight not lead to malfunctionLeads to MalfunctionCapacitor C170 Resistor R93Capacitor C171 Capacitor C13Diode V33 Resistor R293Resistor R9 Resistor R94Capacitor C9 Capacitor C14CapacitorC178Table 5.40:Classification of passive devices.All components in table 4.23 were taken away, except for C171 and C178. These werecovered with the removal of capacitor C170. These components are used for decouplingpurposes.Monitoring Of Gate-Emitter and Collector-Emitter Voltage of IGBTMight not lead to malfunctionLeads to MalfunctionCapacitor C180 Resistor R95Capacitor C179 Capacitor C15ResistorR34CapacitorC5ResistorR49Resistor R71*ResistorR138ResistorR96CapacitorC16ResistorR97CapacitorC17ResistorR10Diode V7*ResistorR11ResistorR19Resistor R82*Table 5.41: Classification of passive devices.Devices in table 5.24 were not removed at all. It was not necessary, because these areused for decoupling. Thus, covered by the test of capacitor C171 (refer to the explanationgiven in table 5.40).70

DI/DT Monitoring of IGBT CurrentMight not lead to malfunctionLeads to MalfunctionResistor R42 Resistor R253Resistor R31 Capacitor C133Resistor R6 Resistor R99Capacitor C66 Capacitor C19Diode V42 Resistor R100Resistor R39 Capacitor C20Diode V46 Resistor R90Resistor R1 Resistor R29Capacitor C122 Resistor R140ResistorR110ResistorR36ResistorR16ResistorR35CapacitorC6Table 5.42: Classification of passive devices.From table 5.25, all components were removed, except for the decoupling capacitor C122which is covered by the capacitor C171.-15 and +17V Supply Voltage Supervisions and Download ProtectionMight not lead to malfunctionLeads to MalfunctionCapacitor C95 Resistor R65Capacitor C118 Resistor R66Capacitor C96 Resistor R25Resistor R67 Resistor R30Resistor R15 Resistor R83Diode V21 Capacitor C50Capacitor C40 Resistor R58Capacitor C4 Capacitor C11Resistor R232 Resistor R69Resistor R231 Resistor R55Capacitor C94 Capacitor C85ResistorR33ResistorR51ResistorR21Table 5.43: Classification of passive devices.All components presented in table 5.26 were withdrawn except for the capacitor C96,which was tested by removing C118. Capacitors C4 and C94 were left in their placed,since these are used for decoupling purposes and are already tested with the removal ofcapacitor C171.71

Resistor R51 and resistor R21 when removed, cause the same malfunction to the PCB.Basically, the lack of these components creates a change in the signals _CLK_100KHZand _CLK_2HZ, respectively. Therefore were moved in the classification (compare table5.43 with table 5.26).Supply Voltage SupervisionMight not lead to malfunctionLeads to MalfunctionResistor R278 Resistor R280*Resistor R281 Resistor R279Resistor R107 Resistor R106Resistor R112 Resistor R89Resistor R108 Resistor R38Resistor R136 Resistor R109*CapacitorC25CapacitorC134Table 5.44: Classification of passive devices.Devices contained in table 5.27 were removed, with the exception of C134 because it is adecoupling capacitor, a situation that has been explained.The other exception is the resistor R107, due to its functionality (used as a voltagedivider), and since it is in parallel with a resistor of almost 5 times, it was easy to foreseethe result of withdrawing it: no change in functionality. R112 when removed did not leadto any malfunction of the board.Optical Interface Receiver and TransmitterMight not lead to malfunctionLeads to MalfunctionCapacitor C135 Resistor R261Resistor R260 Resistor R271Capacitor C136 Resistor R256Resistor R258 Diode V87*Resistor R259 Resistor R272DiodeV82Table 5.45: Classification of passive devices.All components shown in table 5.28 were taken away without finding any failure. Hencetables 5.28 and 5.45 have the same information.72

FPGA Interface 50 MHz ClockMight not lead to malfunctionLeads to MalfunctionResistor R297 Resistor R285Resistor R298 Resistor R269Resistor R287 Resistor R286Capacitor C181 Resistor R289ResistorR288Table 5.46: Classification of passive devices.The only device of those listed in table 5.29 which was not removed is the capacitorC181, since it was covered with the capacitor C171. Comparing table 5.46 against table5.29, the change in classification of resistor R286, R289 and R288 is observed. Thesecreated a fail in the circuit’s behavior.FPGA InterfaceMight not lead to malfunctionResistorR282DiodeV37DiodeV93ResistorR283DiodeV92DiodeV43CapacitorC165Leads to MalfunctionTable 5.47: Classification of passive devices.Component C165 in table 5.30 was not tested, because it is covered with the capacitorC171. In the instance of the other devices listed in table 5.30, from the schematic’sanalysis (refer to document 3EST000202-2932 sheet 12), it is possible to determine thatthe circuit comprised by the components V41, V43, V92 and R283 has exactly the samefunctionality than the one composed by V41, V93, V37 and R282. Therefore it is enoughif only one of these is verified.Furthermore, it is clear that removing any of the passive components is possible todetermine if there will be a malfunction or not. LED V43 was taken away and nomalfunction was present in the PCB. The dual n-channel FET (V41) was not removed,because of its difficulty to be withdrawn in comparison with any of the other components.73

CPLD Interface and Flash MemoryMight not lead to malfunctionLeads to MalfunctionResistor R274 Resistor R276ResistorR275CapacitorC182ResistorR299ResistorR300ResistorR284ResistorR301DiodeV94DiodeV91Table 5.48: Classification of passive devices.All devices given in table 5.31 were removed, except for R284, R301 and V94. Also theactive component V83 was not taken away. The explanation is found, following the samesyllogism stated in the previous paragraph.Table 5.48 compared with table 5.31 shows only one change. This is seen in resistorR276. It was removed, causing a malfunction.IGBT Driving Amplifier Turn OnMight not lead to malfunctionLeads to MalfunctionCapacitorC175CapacitorC174CapacitorC41Table 5.49: Classification of passive devices.From the components listed in table 5.32, only the C175 was removed, covering with thistest the capacitor C174. In the case of capacitor C41, this is covered by the test of thecapacitor C171.IGBT Driving Amplifier Turn OffMight not lead to malfunctionLeads to MalfunctionCapacitorC162CapacitorC163CapacitorC183CapacitorC177CapacitorC176Table 5.50: Classification of passive devices.74

From the components shown in table 5.33, capacitors C162 and C177 were withdrawn;therefore it was not necessary to perform the same test for capacitors C163 and C176.Device C183 fits in the same description as all decoupling capacitors.Resistive Turn On/Off of IGBTMight not lead to malfunctionLeads to MalfunctionResistor R173 Resistor R105*Resistor R104 Resistor R28Resistor R86 Diode V55Resistor R169 Resistor R102Resistor R194 Resistor R4Resistor R13 Diode V54Resistor R172 Resistor R27Resistor R195 Resistor R103*Resistor R14 Resistor R139ResistorR162Table 5.51: Classification of passive devices.Devices presented in table 5.34 were taken away, except for the resistor R194 and R13,covered with the test done over the resistor R169 and the devices R195 and R14 whichwere verified by removing R172.From a comparison between table 5.51 and table 5.34 it is seen the change inclassification of device R139. The malfunction appeared when the PCB tried to turn onthe current source bit 0. This issue creates the need for reviewing the purpose of thefunctional test that failed. In the meantime it is taken as a component being checkedduring the performance of a functional test.Gate Guard and IGBT Gate-Emitter ConnectorMight not lead to malfunctionLeads to MalfunctionResistor R168 Diode V8Capacitor C81 Resistor R130Resistor R167 Resistor R152Capacitor C82 Diode V6ResistorR120CapacitorC54DiodeV45DiodeV36Table 5.52: Classification of passive devices.75

Devices shown in table 5.35 were removed, with the exception of R168 and R167. Sincecapacitors C81 and C82 were taken away without creating any failure in the board, R168and R167 respectively were in open circuit without causing any failure. There was noneed to withdraw them.Important to mention is the fact that none of the devices marked as leads to malfunctionin table 5.20 to table 5.35 was removed, based on the fact that their removal for sure willcause a change in the functionality of the circuit.Table 5.37 through table 5.52 show in the column does not lead to malfunction all thedevices that can not be tested with the functional test. On the other hand, column leads tomalfunction contain all the components that are being checked by the functional test.All components with star to the right are components whose presence is essential not onlyfor the right function of the PCB, but also to avoid the destruction of other components orthe board itself. These are listed in table 5.53.Passive ComponentsComponent IDCapacitor C172Capacitor C173DiodeV63DiodeV7DiodeV87Resistor R20Resistor R50Resistor R22Resistor R48Resistor R71Resistor R82Resistor R280Resistor R109Resistor R105Resistor R103Table 5.53: Critical Components.Using the information presented in previous tables, the assessment of the practical testcoverage achieved with the performance of the functional test could be done.76

5.1.4 Test CoverageAll the input data for the standard of modeling PCOLA/SOQ has been defined, now it ispossible to calculate the board device score and the board connection score achieved byeach of the testers applied to the GDU. As aforesaid, the final test coverage is thecombination of the individual test coverage generated by the ICT and FT.5.1.4.1 ICT CoverageBoard device score and board connection score are achieved by taking into account theinformation provided in section 5.1.3.1 (untested components) and tables 5.14, 5.15 and5.18.5.1.4.1.1 Board Device ScoreA list of the untested and/or tested in parallel components whose presence (and thereforeany of the other properties) is not possible to determine is given in section 5.1.3.1 asaforesaid. The individual result of each type of device as well as the tested percentage isshown in table 5.54.Device BDS %Analog 1410,22 86,01%Capacitor 717,63 47,33%Connector 14,46 13,82%Digital 292,58 76,57%Diode 762,24 81,63%Filter 17,48 83,53%Inductor 1152,68 81,84%Oscillator 417,64 83,53%Resistor 2185,20 81,20%Transformer 658,22 83,53%Transistor 14,46 96,76%7642,81 76,43%Table 5.54: ICT Board Device Score.The column with the percentage shows some discrepancies with the maximum achievabledevice score for analog circuits and transformer. As stated in section 5.1.1.2.5, thehighest possible value is 0.82 or 82% for components whose orientation is relevant.Differences are due to the devices A15, A20 and A21 which are circuit specially77

manufactured for the GDU and therefore their correct property can be qualified as fullytested. The same explanation applies for the transformer.For other devices, when orientation is irrelevant, the maximum achievable device score is0.84 or 84% roughly. Therefore, the highest board device score is roughly 8300 or 83%when both sort of components, orientation relevant and irrelevant, are verified.From the information given in table 4.54, the board device score is 7642.81 or inpercentage 76.43%. Also, the components with the lowest coverage are connectors andcapacitors.5.1.4.1.2 Board Connection ScoreIn order to estimate the test coverage achieved over the connections, the informationprovided in section 5.1.3.1 and table 5.18 is used. Also, in the case of the integratedcircuits not all the pins are verified when the ICT is performed, just the pins necessariesto determine their properties. In this sense, the component is alive but not necessarilyworking properly.On the other hand, there are ICs whose functionality is completely tested by ICT, also alltheir connections. These ICs are: A5, A6, A8, A9, A16, D2, D4, D6, D9, D12, D13, D14,D17 and D18. The rest of the ICs (either analog or digital) are considered as untested inall their connections, for the BCS assessment.Due to the last statement and since most of the ICs have several pins, the boardconnection score is rather low, actually 5555.98 from a maximum of 9007 or 55.55% outof 90.07%. Also, it is important to state that all bypass capacitors are not being verified.Hence their connections are not tested, contributing to lower the figure.The calculation of the board connection score is done assuming that no short is present inthe circuit. Therefore the weight assigned to this property was added to the open property.This assumption is valid, since the ICT can not be executed if a short circuit does exist.78

5.1.4.2 FT CoverageThe information used to assess the test coverage of Functional Test is retrieved fromsection 5.1.3.2 and from tables 5.14, 5.15 and 5.18.5.1.4.2.1 Board Device ScoreComponents considered as verified by this test method are the ones contained in thecolumn leads to malfunction shown from table 5.37 to table 5.52. Also, table 5.15 wasused to define the board device score. Table 5.55 presents the individual contribution ofeach type of device as well as the board device score.Device BDS %Analog 1410,22 86,01%Capacitor 243,61 16,07%Connector 57,86 55,29%Digital 323,39 84,63%Diode 194,99 20,88%Filter 17,48 83,53%Inductor 1152,68 81,84%Oscillator 417,64 83,53%Resistor 1280,39 47,58%Transformer 614,34 77,96%Transistor 14,46 96,76%5727,06 57,27%Table 5.55: FT Board Device Score.In table 5.55 it is possible to observe the same discrepancies in the coverage percentageachieved by the analog circuits and the transformer, presents in table 5.54. Therefore, thesame explanation provided in section 5.1.4.1.1 applies.The 5727.06 points of a maximum of roughly 83000 is the board device score achievedby using this test technology. The components with the lowest coverage are capacitorsand diodes.5.1.4.2.2 Board Connection ScoreIn this instance, information provided in section 5.1.3.2 and table 5.18 was not enough tocalculate the test coverage attained over the connections. As explained in section 4.1.3,79

most of the active devices are checked during the performance of an FT, but it does notmean necessarily that the component is being tested on all its pins. Furthermore, theanalysis done in section 5.1.3.2 is not completely useful to determine the pins whoseconnections are verified.A thorough analysis was necessary in order to determine the connections tested in theiropen property. Since a functional test is executed always after the performance of an ICT,no short circuit is present and the weight assigned to this property is added to the lastmentioned property.A board connection score of 6080.40 out of 9007 or 60.80% from a total of 90.07% wasachieved with this test method. There is a huge increment in the connection testingregarding active components, since most of those are verified during a Functional test.On the other hand, several passive components are not checked and hence the verificationof their connections is not done.5.1.4.3 Special TestsIn order to increase the test coverage early in the production stage, special tests areperformed over specific components. These are executed as part of the test programdeveloped by Enics.More important than the individual coverage achieved by these special tests, is the factthat they are verifying the components and connections untested by the other two testmethods.5.1.4.3.1 Board Device ScoreRelated to this figure, Human Visual Inspection is performed over all the capacitors withpolarity. In this case, live property is not possible to test, due to the nature of the test.Correct and alignment properties are possible to test, but there is no evidence that theseproperties are being verified. Therefore, only presence and orientation are qualified asfully tested and the remaining as not tested.80

HVI provides means to test the aforementioned properties of capacitors C45, C56 whichare tested in parallel with C55 and whose placement on the board could not bedetermined due to this fact. The same situation is present in capacitors C58 and C59 thatare verified in parallel with capacitor C46. The BDS of these components is 65.45 from amaximum of 197.76.The indirect test of the connector X14 is done when the flash memory is programmed.All the properties that apply to this component are verified, except for alignment.Obviously, X1 is tested since the board needs to be supplied with 24 V. BDS ofconnectors is 28.93 out of 104.64.5.1.4.3.2 Board Connection ScoreRegarding connections, a special test called Opens Xpress is performed in order to findopen circuits between a pin and its respective node pad. This test, as reported by Enics,verifies all pins of the checked circuits. Thus, 100% test coverage is attained regardingopens in the following integrated circuits: A1, A2, A4, A7, A11, A12, A15, A17, A18,A20, A21, D10, D11 and D16.With the information provided in last paragraph and applying the method to the ICs, theboard connection score is 914.19 for the analog circuits and 1608.68 for the digitalcircuits.In the same manner explained in previous section, the connector X14 is tested when theflash memory is programmed. Any short or open will be found while a programmingevent is executed. Achieved BCS is 56.69.5.1.4.4 Combined Test CoverageThe individual board device score and board connection score generated by each of thetests performed over the circuit afford an idea of how good the test is, but only thecombination of the test coverage will give the achieved BDS and BCS that are the figuresof interest.81

5.1.4.4.1 Combined Board Device ScoreTable 5.56 shows the individual board device score and the percentage of each testmethod. This table serves as a comparison of how good are the tests.TestICTFTHVIProgrammingDevice BDS % BDS % BDS % BDS %Analog 1409,67 86,01% 1410,22 86,01% NA NA NA NACapacitor 717,35 47,33% 243,61 16,07% 65,46 4,32% NA NAConnector 14,46 13,82% 57,86 55,29% NA NA 28,928 27,65%Digital 292,47 76,57% 323,39 84,63% NA NA NA NADiode 761,94 81,63% 194,99 20,88% NA NA NA NAFilter 17,47 83,53% 17,48 83,53% NA NA NA NAInductor 1152,24 81,84% 1152,68 81,84% NA NA NA NAOscillator 417,64 83,53% 417,64 83,53% NA NA NA NAResistor 2184,35 81,20% 1280,39 47,58% NA NA NA NATransformer 14,46 96,76% 614,34 77,96% NA NA NA NATransistor 661,03 83,53% 14,46 96,76% NA NA NA NA7643,09 76,43% 5727,06 57,27% 65,43 0,65% 28,91 0,29%Table 5.56: Individual Board Device Score.The combined BDS and the percentage it represents of each type of device is provided intable 5.57.Device BDS %Analog 1410,22 86,01%Capacitor 749,82 49,45%Connector 72,32 69,11%Digital 323,39 84,63%Diode 779,96 83,53%Filter 17,48 83,53%Inductor 1152,68 81,84%Oscillator 417,64 83,53%Resistor 2202,27 81,84%Transformer 658,22 83,53%Transistor 14,46 96,76%7798,47 77,98%Table 5.57: Combined Board Device Score.Retrieved from table 5.57, the board device scored achieved by the combination of thetests applied to the GDU is 7798.47 from a total of 10000, the range defined in section5.1.1. However, the highest score that might be achieved with the test technologies usedis approximately 8300. The test coverage over the devices is 77.98% from a maximum of83%.82

5.1.4.4.2 Combined Board Connection ScoreThe BCS produced by the tests executed in the PCB are shown in table 5.58. This onedisplays the information following the same strategy than in last section.TestICT FT Opens Xpress ProgrammingDevice BCS % BCS % BCS % BCS %Analog 538,59 32,75% 1325,21 80,59% 914,19 55,59% NA NACapacitor 751,19 51,89% 255,12 17,62% NA NA NA NAConnector 14,17 4,09% 113,39 32,75% NA NA 56,69 16,38%Digital 1133,87 37,33% 2508,69 82,60% 1608,68 52,97% NA NADiode 659,06 84,61% 212,60 27,29% NA NA NA NAFilter 42,52 90,07% 42,52 90,07% NA NA NA NAInductor 85,04 90,07% 85,04 90,07% NA NA NA NAOscillator 28,35 90,07% 28,35 90,07% NA NA NA NAResistor 1814,20 89,37% 1063,01 52,37% NA NA NA NATransformer 92,13 167,27% 92,13 167,27% NA NA NA NATransistor 396,86 90,07% 354,34 80,42% NA NA NA NA5555,98 55,56% 6080,40 60,80% 2522,87 25,23% 56,69 0,57%Table 5.58: Individual Board Connection Score.The combined board connection score is presented in table 5.59.Device BCS %Analog 1452,78 88,35%Capacitor 765,36 52,87%Connector 170,08 49,13%Digital 2763,82 91,00%Diode 701,58 90,07%Filter 42,52 90,07%Inductor 85,04 90,07%Oscillator 28,35 90,07%Resistor 1828,37 90,07%Transformer 92,13 90,07%Transistor 396,86 90,07%8326,88 83,27%Table 5.59: Combined Board Connection Score.From the information contained in table 5.59, the combined BCS is 8326.88 out of10000. It is important to remark that due to the sort of test performed and the limitationsthat these entail, the maximum achievable BCS is 9007. The connection test coverage is83.27%.The utter list of grades given to each component, by property as well as by testtechnology is shown in appendix A.83

5.2 Functional Test Coverage AnalysisThere are two documents that contain the requirements which describe the functionalityof the components placed on the board. These are the specification of manufacturing testand production test specification.The former document is seen as a complement to the normal ICT. It is an electricalverification of different parameters such as resistance and voltage. Also, there arerequirements for specifying the behavior of the oscillators present in the board. Thesetests do not use external stimuli and a program is not loaded in flash memory in order toperform them.The tests which involve the resistance measurement are intended to probe thefunctionality of the ICs A15, A20 and A21. Whilst the ones related with voltagemeasurement have different purposes. The voltage supervision of the voltages whichsupply the board is one of these purposes. Also, the over voltage and under voltageprotection capabilities are tested. The last purpose of the voltage measurement tests is toverify the internal voltage dividers.The specification of manufacturing test defines the requirements that apply to the Burn-inTest and the programming of the CPLD and flash memory.After analyzing the document, it states clearly what shall be measured and the criteria forqualifying whether the test passes or fails. Also, it describes how the test shall beperformed. By following the strategy exposed in section 4.2, as long as all therequirements contained in the mentioned document are implemented and hence, verifiedby the tests applied to the circuit, the test coverage is 100%.The latter document describes the tests executed in the PCB, while the Burn-in Test isperformed. This set of tests is running continuously during the whole execution of theBIT and most of them are intended to verify the response of the integrated circuits toexternal stimuli. A program with the set of tests is loaded in flash memory and the board84

works in test mode. The unit under test interacts with a board that generates the externalstimuli by the optical transmitter and receiver.The external stimuli as well as the external circuitry are designed to simulate possiblescenarios under which the circuit will work. Therefore, the tests developed measurecircuit’s responses in time and voltage. As it could be inferred, these sorts of tests, ratherthan simply electrical verifications are functional verifications. Most of the activecomponents are verified on their functionality during the performance of these tests, alsosome of the passive devices are verified, indirectly.After analyzing the document, it is possible to determine that requirements are clear andthe pass/fail criteria are well specified. As in the first document, this one states how thetest shall be performed. By applying the same criteria, as long as all the requirements aretested, the test coverage is 100%.However, a thorough revision of both documents is a best practice. Also, the revision ofthe tests performed and the criteria to qualify the test is rather important in order toensure that the requirement being verified is indeed, adequately tested.The requirement traceability document was not created because there are some issues andimprovements that must be done to the specification of manufacturing test andproduction test specification. The comments regarding issues and improvements wereinserted in the electronic version of both documents.85

6 Results and ImprovementsIn this section, the results attained by the method’s application are reviewed. Also, theimprovements suggested for increasing the reliability in the result yielded by the methodare given. It is important to mention that there are some improvements mentioned in ageneral manner and not specifically for the product that was used as a study case.6.1 PCB’s structureThe figures yielded after applying the method for analyzing structural test coverage fordevices is 77.98% from a maximum of 83%. For connections is 83.27% out of 90.07%.Although there are no other figures available to compare the achieved result, it is possiblea comparison taken into consideration the maximum achievable scores and the resultsattained.Derived from this comparison, the test coverage over the devices is rather high.Furthermore, most of the untested components are decoupling capacitors. As it wasmentioned, the verification of their properties is complicated due to the fact that these areplaced in parallel, besides their low value. There is a tradeoff related with test cost inorder to verify the non-tested components.Regarding connections, the test coverage is not as high as the one achieved over thedevices. In addition to the untested components (whose connection, obviously is notchecked), there are some untested connections between pins of ICs and their respectivenode pad. Again, there is a tradeoff, if the unverified connections are going to be tested.Design for test (DFT) is an important tool for increasing the test coverage at a structurallevel. DFT is a name for design techniques that add certain testability features to thehardware of a PCB. The premise of the added features is to make easier the developmentand application of manufacturing tests for the designed hardware.DFT often is associated with design modifications that provide improved access tointernal circuit elements such that the local internal state can be controlled and/or86

observed more easily. The design modifications can be strictly physical in nature (e.g. byadding a physical test point to a net) and/or add active circuit elements to facilitate thecontrol/observation (e.g. by inserting a multiplexer into a net) [21].While control and observation improvements for internal circuit elements are importantfor test, these are not the only type of DFT. Other guideline, for instance is to deal withthe electromechanical characteristics of the interface between the unit under test and thetest equipment. Examples are guidelines for the size, shape and spacing of test points orsuggestion to add a high-impedance state to drivers attached to probed nets such that therisk of damage from back-driving is mitigated [21].Due to the high complexity design, the access to the different components that comprisesa printed circuit board is not an easy task. In order to simplify test generation, DFTaddresses the accessibility problem by removing the need for complicated state transitionsequences when trying to control and/or observe the behavior at some internal circuitelement.One objective of DFT methodologies, hence, is to allow designers to make tradeoffsbetween the amount and type of DFT and the cost/benefit (time, effort, quality) of the testgeneration task [21].6.2 PCB’s FunctionalityThe functional test coverage is 100%, since all the requirements are implemented andverified by the tests defined in the specification of manufacturing test and production testspecification.This figure means perfect test coverage. However, it is important to stress the necessity ofreviewing both documents in order to be completely sure that all the requirements relatedwith the functionality of the board are stated. One way of ensuring the quality of thedocument is to hold a peer review that is attended by people with knowledge regardingwith the PCB and therefore, its functionality.87

Also, it is necessary to review each of the tests developed for verifying the requirements.This revision includes the measured parameters, their values and tolerances. The analysisof the steps of each test is also subject of revision. As well as for the documentation, apeer review of the test is rather important.The peer reviews are intended to verify documentation and test development by differentpeople. By doing this, not only the person that generates either the documentation or thetests review the quality of these, but also people with expertise in the area.It was mentioned in section 5.2 that both documents state the requirements as well as thetests implemented in order to verify them. It is a best practice to have one documentestablishing the requirements and one for the tests.After reviewing both documents and by comparing them against the differentcomponents and their functionality, there are some tests (and their respectiverequirements) that may be added in order to increase the quality of the documentation andthe correct test of the board’s functionality. These are listed in the following paragraphs.For the specification of manufacturing test, the internal voltage dividers’ requirements arestated for most of the voltage dividers, except for the one comprised for the resistors R19and R82. This shall be added in the document and the verification shall be implemented.Regarding the production test specification, it is necessary to add requirements forchecking the gate guard functionality. Also, the High_Ud functionality lacks ofrequirements. The last requirements that are needed in order to test the wholefunctionality of the circuit are related with the on_off signal.The functionality of the internal clocks as well as the communication module(transmission and reception) is tested implicitly. Nevertheless, there are no specificrequirements for them. There are tests to perform an electrical verification over them.88

7 References:[1] http://en.wikipedia.org/wiki/Quality, November 7, 2007.[2] http://www.m-w.com/dictionary/quality, November 7, 2007.[3] http://www.isixsigma.com/dictionary/QUALITY_-_DEFINITION-764.htm,November 7, 2007.[4] http://www.asq.org/glossary/q.html, November 7, 2007.[5] http://en.wikipedia.org/wiki/Quality_assurance, November 7, 2007.[6] http://www.m-w.com/cgi-bin/dictionary?book=Dictionary&va=quality+assurance,November 7, 2007.[7] http://www.isixsigma.com/dictionary/Quality_Assurance-105.htm, November 7, 2007.[8] Christophe Lotz, Peter Collins, Dominique Wiatrowski, FUNCTIONAL BOARDTEST – COVERAGE ANALYSIS, what does it mean when a functional test passes?,BOARD TEST WORKSHOP, September 14 th & 15 th , 2006.[9] Katy Hird, Kenneth P. Parker, Bill Follis, Test Coverage: What Does It Mean when aBoard Test Passes?, IEEE, 2002.[10] Jukka Antila, Markku Moilanen, Test Process Efficiency Analysis with BasicQuality Data.[11] Kenneth P. Parker, Kathleen J. Hird, Erik A. Ramos, Methods and apparatus forcharacterizing board test coverage, US2004/00244498 A1, March 4 th , 2004.[12] Kenneth P. Parker, Defect Coverage of Boundary-Scan Tests: What does it meanwhen a Boundary-Scan test passes?, International Test Conference, 2003.[13] http://www.bench.com/viewer/services_test-dev_ict.asp, 12 th November, 2007.[14]http://www.evaluationengineering.com/archive/articles/0705/0705applying_automated.asp, 12 th November, 2007.[15] http://www.bench.com/viewer/services_test-dev_axi.asp, 12 th November, 2007.[16] http://www.acculogic.com/index.php?content=product&category=fp&id=scor, 12 thNovember, 2007.[17] http://www.faulhaber-group.com/n221379/n.html, 12 th November, 2007.[18] http://www.corelis.com/products/Boundary-Scan_Tutorial.htm, 12 th November,2007.89

[19] http://www-ee.eng.hawaii.edu/~msmith/ASICs/HTML/Book/CH14/CH14.2.htm,12 th November 2007.[20] http://en.wikipedia.org/wiki/Failure_rate, 29 th October , 2007.[21] http://en.wikipedia.org/wiki/Design_For_Test, 1 st January, 2008.90

Appendix AThis appendix contains the grades assigned to each of the components, depending on thetest method that is verifying them. It is divided in devices and connections.ADevicesIn this section, the grades attained by each device in the different tests performed to themare shown.A.1ICTAnalog CircuitsDevice P C O L A RDS DSA1 1 0.75 1 1 0 0.835 85.597A11 1 0.75 1 1 0 0.835 85.597A12 1 0.75 1 1 0 0.835 85.597A15 1 1 1 1 0 0.968 99.153A16 1 0.75 1 1 0 0.835 85.597A17 1 0.75 1 1 0 0.835 85.597A18 1 0.75 1 1 0 0.835 85.597A2 1 0.75 1 1 0 0.835 85.597A20 1 1 1 1 0 0.968 99.153A21 1 1 1 1 0 0.968 99.153A4 1 0.75 1 1 0 0.835 85.597A5 1 0.75 1 1 0 0.835 85.597A6 1 0.75 1 1 0 0.835 85.597A7 1 0.75 1 1 0 0.835 85.597A8 1 0.75 1 1 0 0.835 85.597A9 1 0.75 1 1 0 0.835 85.597Table A.1Non-Polarized CapacitorsDevice P C O L A RDS DSC10 1 0.75 NA 1 0 0.818 13.488C11 1 0.75 NA 1 0 0.818 13.488C118 1 0.75 NA 1 0 0.818 13.488C122 0 0 NA 0 0 0 0C13 1 0.75 NA 1 0 0.818 13.488C133 1 0.75 NA 1 0 0.818 13.488C134 1 0.75 NA 1 0 0.818 13.488C135 1 0.75 NA 1 0 0.818 13.488C136 0 0 NA 0 0 0 0C137 1 0.75 NA 1 0 0.818 13.488C138 0 0 NA 0 0 0 0

C139 0 0 NA 0 0 0 0C14 1 0.75 NA 1 0 0.818 13.488C140 1 0.75 NA 1 0 0.818 13.488C141 1 0.75 NA 1 0 0.818 13.488C142 0 0 NA 0 0 0 0C143 0 0 NA 0 0 0 0C144 0 0 NA 0 0 0 0C145 0 0 NA 0 0 0 0C146 0 0 NA 0 0 0 0C147 0 0 NA 0 0 0 0C148 0 0 NA 0 0 0 0C149 0 0 NA 0 0 0 0C15 0 0 NA 0 0 0 0C150 0 0 NA 0 0 0 0C151 0 0 NA 0 0 0 0C152 0 0 NA 0 0 0 0C153 0 0 NA 0 0 0 0C154 0 0 NA 0 0 0 0C155 0 0 NA 0 0 0 0C158 0 0 NA 0 0 0 0C159 0 0 NA 0 0 0 0C16 1 0.75 NA 1 0 0.818 13.488C162 1 0.75 NA 1 0 0.818 13.488C163 1 0.75 NA 1 0 0.818 13.488C165 0 0 NA 0 0 0 0C166 1 0.75 NA 1 0 0.818 13.488C167 1 0.75 NA 1 0 0.818 13.488C168 1 0.75 NA 1 0 0.818 13.488C169 1 0.75 NA 1 0 0.818 13.488C17 1 0.75 NA 1 0 0.818 13.488C170 0 0 NA 0 0 0 0C171 0 0 NA 0 0 0 0C174 1 0.75 NA 1 0 0.818 13.488C175 1 0.75 NA 1 0 0.818 13.488C176 1 0.75 NA 1 0 0.818 13.488C177 1 0.75 NA 1 0 0.818 13.488C178 0 0 NA 0 0 0 0C179 0 0 NA 0 0 0 0C180 0 0 NA 0 0 0 0C181 0 0 NA 0 0 0 0C182 0 0 NA 0 0 0 0C183 0 0 NA 0 0 0 0C19 1 0.75 NA 1 0 0.818 13.488C20 1 0.75 NA 1 0 0.818 13.488C25 0 0 NA 0 0 0 0C35 1 0.75 NA 1 0 0.818 13.488C4 0 0 NA 0 0 0 0C40 1 0.75 NA 1 0 0.818 13.488C41 0 0 NA 0 0 0 0C47 1 0.75 NA 1 0 0.818 13.488

C5 1 0.75 NA 1 0 0.818 13.488C50 1 0.75 NA 1 0 0.818 13.488C54 1 0.75 NA 1 0 0.818 13.488C6 1 0.75 NA 1 0 0.818 13.488C66 1 0.75 NA 1 0 0.818 13.488C7 1 0.75 NA 1 0 0.818 13.488C8 1 0.75 NA 1 0 0.818 13.488C81 1 0.75 NA 1 0 0.818 13.488C82 1 0.75 NA 1 0 0.818 13.488C85 1 0.75 NA 1 0 0.818 13.488C86 1 0.75 NA 1 0 0.818 13.488C87 1 0.75 NA 1 0 0.818 13.488C88 1 0.75 NA 1 0 0.818 13.488C9 1 0.75 NA 1 0 0.818 13.488C94 0 0 NA 0 0 0 0C95 0 0 NA 0 0 0 0C96 1 0.75 NA 1 0 0.818 13.488Table A.2Polarized CapacitorsDevice P C O L A RDS DSC12 1 0.75 1 1 0 0.835 13.767C160 1 0.75 1 1 0 0.835 13.767C161 1 0.75 1 1 0 0.835 13.767C172 1 0.75 1 1 0 0.835 13.767C173 1 0.75 1 1 0 0.835 13.767C18 1 0.75 1 1 0 0.835 13.767C44 1 0.75 1 1 0 0.835 13.767C45 0 0 0 0 0 0 0C46 1 0.75 1 1 0 0.835 13.767C53 1 0.75 1 1 0 0.835 13.767C55 1 0.75 1 1 0 0.835 13.767C56 0 0 0 0 0 0 0C58 0 0 0 0 0 0 0C59 0 0 0 0 0 0 0Table A.3ConnectorsDevice P C O L A RDS DSX1 1 1 1 1 0 0.968 14.464X2 0 0 0 0 0 0 0X3 0 0 0 0 0 0 0X7 0 0 0 0 0 0 0X12 0 0 0 0 0 0 0X13 0 0 0 0 0 0 0X14 0 0 0 0 0 0 0Table A.4

Digital CircuitsDevice P C O L A RDS DSD10 1 0.75 1 1 0 0.835 26.598D11 1 0.75 1 1 0 0.835 26.598D12 1 0.75 1 1 0 0.835 26.598D13 1 0.75 1 1 0 0.835 26.598D14 1 0.75 1 1 0 0.835 26.598D16 1 0.75 1 1 0 0.835 26.598D17 1 0.75 1 1 0 0.835 26.598D18 1 0.75 1 1 0 0.835 26.598D2 1 0.75 1 1 0 0.835 26.598D4 1 0.75 1 1 0 0.835 26.598D6 1 0.75 1 1 0 0.835 26.598D9 0 0 0 0 0 0 0Table A.5DiodesDevice P C O L A RDS DSV1 1 0.75 1 1 0 0.835 17.726V12 1 0.75 1 1 0 0.835 17.726V13 1 0.75 1 1 0 0.835 17.726V14 1 0.75 1 1 0 0.835 17.726V15 1 0.75 1 1 0 0.835 17.726V17 1 0.75 1 1 0 0.835 17.726V18 1 0.75 1 1 0 0.835 17.726V19 1 0.75 1 1 0 0.835 17.726V20 1 0.75 1 1 0 0.835 17.726V21 1 0.75 1 1 0 0.835 17.726V27 1 0.75 1 1 0 0.835 17.726V3 1 0.75 1 1 0 0.835 17.726V33 1 0.75 1 1 0 0.835 17.726V36 1 0.75 1 1 0 0.835 17.726V37 1 0.75 1 1 0 0.835 17.726V38 1 0.75 1 1 0 0.835 17.726V39 1 0.75 1 1 0 0.835 17.726V4 1 0.75 1 1 0 0.835 17.726V40 1 0.75 1 1 0 0.835 17.726V42 1 0.75 1 1 0 0.835 17.726V43 1 0.75 1 1 0 0.835 17.726V45 1 0.75 1 1 0 0.835 17.726V46 1 0.75 1 1 0 0.835 17.726V48 1 0.75 1 1 0 0.835 17.726V49 1 0.75 1 1 0 0.835 17.726V54 1 0.75 1 1 0 0.835 17.726V55 1 0.75 1 1 0 0.835 17.726V6 1 0.75 1 1 0 0.835 17.726V60 1 0.75 1 1 0 0.835 17.726

V63 1 0.75 1 1 0 0.835 17.726V7 1 0.75 1 1 0 0.835 17.726V79 1 0.75 1 1 0 0.835 17.726V8 1 0.75 1 1 0 0.835 17.726V80 1 0.75 1 1 0 0.835 17.726V82 0 0 0 0 0 0 0V87 1 0.75 1 1 0 0.835 17.726V88 1 0.75 1 1 0 0.835 17.726V89 1 0.75 1 1 0 0.835 17.726V9 1 0.75 1 1 0 0.835 17.726V90 1 0.75 1 1 0 0.835 17.726V91 1 0.75 1 1 0 0.835 17.726V92 1 0.75 1 1 0 0.835 17.726V93 1 0.75 1 1 0 0.835 17.726V94 1 0.75 1 1 0 0.835 17.726Table A.6FilterDevice P C O L A RDS DSZ1 1 0.75 1 1 0 0.83528 17.481Table A.7InductorsDevice P C O L A RDS DSL3 1 0.75 NA 1 0 0.818 192.114L4 1 0.75 NA 1 0 0.818 192.114L5 1 0.75 NA 1 0 0.818 192.114L6 1 0.75 NA 1 0 0.818 192.114L7 1 0.75 NA 1 0 0.818 192.114L8 1 0.75 NA 1 0 0.818 192.114Table A.8OscillatorDevice P C O L A RDS DSB1 1 0.75 1 1 0 0.835 417.640Table A.9ResistorsDevice P C O L A RDS DSR1 1 0.75 NA 1 0 0.818 17.072R10 1 0.75 NA 1 0 0.818 17.072R100 1 0.75 NA 1 0 0.818 17.072R102 1 0.75 NA 1 0 0.818 17.072R103 1 0.75 NA 1 0 0.818 17.072R104 1 0.75 NA 1 0 0.818 17.072

R105 1 0.75 NA 1 0 0.818 17.072R106 1 0.75 NA 1 0 0.818 17.072R107 1 0.75 NA 1 0 0.818 17.072R108 1 0.75 NA 1 0 0.818 17.072R109 1 0.75 NA 1 0 0.818 17.072R11 1 0.75 NA 1 0 0.818 17.072R110 1 0.75 NA 1 0 0.818 17.072R112 1 0.75 NA 1 0 0.818 17.072R120 1 0.75 NA 1 0 0.818 17.072R13 1 0.75 NA 1 0 0.818 17.072R130 1 0.75 NA 1 0 0.818 17.072R136 1 0.75 NA 1 0 0.818 17.072R138 1 0.75 NA 1 0 0.818 17.072R139 1 0.75 NA 1 0 0.818 17.072R14 1 0.75 NA 1 0 0.818 17.072R140 1 0.75 NA 1 0 0.818 17.072R15 1 0.75 NA 1 0 0.818 17.072R152 1 0.75 NA 1 0 0.818 17.072R16 1 0.75 NA 1 0 0.818 17.072R162 1 0.75 NA 1 0 0.818 17.072R167 1 0.75 NA 1 0 0.818 17.072R168 1 0.75 NA 1 0 0.818 17.072R169 1 0.75 NA 1 0 0.818 17.072R172 1 0.75 NA 1 0 0.818 17.072R173 1 0.75 NA 1 0 0.818 17.072R19 1 0.75 NA 1 0 0.818 17.072R194 1 0.75 NA 1 0 0.818 17.072R195 1 0.75 NA 1 0 0.818 17.072R2 1 0.75 NA 1 0 0.818 17.072R20 1 0.75 NA 1 0 0.818 17.072R21 1 0.75 NA 1 0 0.818 17.072R22 1 0.75 NA 1 0 0.818 17.072R23 1 0.75 NA 1 0 0.818 17.072R231 1 0.75 NA 1 0 0.818 17.072R232 1 0.75 NA 1 0 0.818 17.072R25 1 0.75 NA 1 0 0.818 17.072R253 1 0.75 NA 1 0 0.818 17.072R254 1 0.75 NA 1 0 0.818 17.072R256 0 0 NA 0 0 0 0R258 1 0.75 NA 1 0 0.818 17.072R259 1 0.75 NA 1 0 0.818 17.072R260 1 0.75 NA 1 0 0.818 17.072R261 1 0.75 NA 1 0 0.818 17.072R269 1 0.75 NA 1 0 0.818 17.072R27 1 0.75 NA 1 0 0.818 17.072R270 1 0.75 NA 1 0 0.818 17.072R271 1 0.75 NA 1 0 0.818 17.072R272 1 0.75 NA 1 0 0.818 17.072R274 1 0.75 NA 1 0 0.818 17.072R275 1 0.75 NA 1 0 0.818 17.072

R276 1 0.75 NA 1 0 0.818 17.072R278 1 0.75 NA 1 0 0.818 17.072R279 1 0.75 NA 1 0 0.818 17.072R28 1 0.75 NA 1 0 0.818 17.072R280 1 0.75 NA 1 0 0.818 17.072R281 1 0.75 NA 1 0 0.818 17.072R282 1 0.75 NA 1 0 0.818 17.072R283 1 0.75 NA 1 0 0.818 17.072R284 1 0.75 NA 1 0 0.818 17.072R285 1 0.75 NA 1 0 0.818 17.072R286 1 0.75 NA 1 0 0.818 17.072R287 1 0.75 NA 1 0 0.818 17.072R288 1 0.75 NA 1 0 0.818 17.072R289 1 0.75 NA 1 0 0.818 17.072R29 1 0.75 NA 1 0 0.818 17.072R293 1 0.75 NA 1 0 0.818 17.072R294 1 0.75 NA 1 0 0.818 17.072R295 1 0.75 NA 1 0 0.818 17.072R296 1 0.75 NA 1 0 0.818 17.072R297 1 0.75 NA 1 0 0.818 17.072R298 1 0.75 NA 1 0 0.818 17.072R299 1 0.75 NA 1 0 0.818 17.072R3 1 0.75 NA 1 0 0.818 17.072R30 1 0.75 NA 1 0 0.818 17.072R300 1 0.75 NA 1 0 0.818 17.072R301 1 0.75 NA 1 0 0.818 17.072R31 1 0.75 NA 1 0 0.818 17.072R33 1 0.75 NA 1 0 0.818 17.072R34 1 0.75 NA 1 0 0.818 17.072R35 1 0.75 NA 1 0 0.818 17.072R36 1 0.75 NA 1 0 0.818 17.072R38 1 0.75 NA 1 0 0.818 17.072R39 1 0.75 NA 1 0 0.818 17.072R4 1 0.75 NA 1 0 0.818 17.072R40 1 0.75 NA 1 0 0.818 17.072R41 1 0.75 NA 1 0 0.818 17.072R42 1 0.75 NA 1 0 0.818 17.072R45 1 0.75 NA 1 0 0.818 17.072R46 1 0.75 NA 1 0 0.818 17.072R47 1 0.75 NA 1 0 0.818 17.072R48 1 0.75 NA 1 0 0.818 17.072R49 1 0.75 NA 1 0 0.818 17.072R5 1 0.75 NA 1 0 0.818 17.072R50 1 0.75 NA 1 0 0.818 17.072R51 1 0.75 NA 1 0 0.818 17.072R52 1 0.75 NA 1 0 0.818 17.072R53 1 0.75 NA 1 0 0.818 17.072R54 1 0.75 NA 1 0 0.818 17.072R55 1 0.75 NA 1 0 0.818 17.072R58 1 0.75 NA 1 0 0.818 17.072

R6 1 0.75 NA 1 0 0.818 17.072R62 1 0.75 NA 1 0 0.818 17.072R63 1 0.75 NA 1 0 0.818 17.072R65 1 0.75 NA 1 0 0.818 17.072R66 1 0.75 NA 1 0 0.818 17.072R67 1 0.75 NA 1 0 0.818 17.072R68 1 0.75 NA 1 0 0.818 17.072R69 1 0.75 NA 1 0 0.818 17.072R71 1 0.75 NA 1 0 0.818 17.072R76 1 0.75 NA 1 0 0.818 17.072R8 1 0.75 NA 1 0 0.818 17.072R82 1 0.75 NA 1 0 0.818 17.072R83 1 0.75 NA 1 0 0.818 17.072R86 1 0.75 NA 1 0 0.818 17.072R89 1 0.75 NA 1 0 0.818 17.072R9 1 0.75 NA 1 0 0.818 17.072R90 1 0.75 NA 1 0 0.818 17.072R93 1 0.75 NA 1 0 0.818 17.072R94 1 0.75 NA 1 0 0.818 17.072R95 1 0.75 NA 1 0 0.818 17.072R96 1 0.75 NA 1 0 0.818 17.072R97 1 0.75 NA 1 0 0.818 17.072R99 1 0.75 NA 1 0 0.818 17.072Table A.10TransformerDevice P C O L A RDS DST1 1 1 1 1 0 0.968 14.464Table A.11TransistorsDevice P C O L A RDS DSV22 1 0.75 1 1 0 0.835 43.881V23 1 0.75 1 1 0 0.835 43.881V28 1 0.75 1 1 0 0.835 43.881V29 1 0.75 1 1 0 0.835 43.881V30 1 0.75 1 1 0 0.835 43.881V31 1 0.75 1 1 0 0.835 43.881V32 1 0.75 1 1 0 0.835 43.881V35 1 0.75 1 1 0 0.835 43.881V41 1 0.75 1 1 0 0.835 43.881V44 1 0.75 1 1 0 0.835 43.881V5 1 0.75 1 1 0 0.835 43.881V56 1 0.75 1 1 0 0.835 43.881V62 1 0.75 1 1 0 0.835 43.881V83 1 0.75 1 1 0 0.835 43.881V86 1 0.75 1 1 0 0.835 43.881

Table A.12A.2Functional TestAnalog CircuitsDevice P C O L A RDS DSA1 1 0.75 1 1 0 0.835 85.597A11 1 0.75 1 1 0 0.835 85.597A12 1 0.75 1 1 0 0.835 85.597A15 1 1 1 1 0 0.968 99.153A16 1 0.75 1 1 0 0.835 85.597A17 1 0.75 1 1 0 0.835 85.597A18 1 0.75 1 1 0 0.835 85.597A2 1 0.75 1 1 0 0.835 85.597A20 1 1 1 1 0 0.968 99.153A21 1 1 1 1 0 0.968 99.153A4 1 0.75 1 1 0 0.835 85.597A5 1 0.75 1 1 0 0.835 85.597A6 1 0.75 1 1 0 0.835 85.597A7 1 0.75 1 1 0 0.835 85.597A8 1 0.75 1 1 0 0.835 85.597A9 1 0.75 1 1 0 0.835 85.597Table A.13Non-Polarized CapacitorsDevice P C O L A RDS DSC10 0 0 NA 0 0 0 0C11 1 0.75 NA 1 0 0.818 13.488C118 0 0 NA 0 0 0 0C122 0 0 NA 0 0 0 0C13 1 0.75 NA 1 0 0.818 13.488C133 1 0.75 NA 1 0 0.818 13.488C134 0 0 NA 0 0 0 0C135 0 0 NA 0 0 0 0C136 0 0 NA 0 0 0 0C137 0 0 NA 0 0 0 0C138 0 0 NA 0 0 0 0C139 0 0 NA 0 0 0 0C14 1 0.75 NA 1 0 0.818 13.488C140 0 0 NA 0 0 0 0C141 0 0 NA 0 0 0 0C142 0 0 NA 0 0 0 0C143 0 0 NA 0 0 0 0C144 0 0 NA 0 0 0 0C145 0 0 NA 0 0 0 0C146 0 0 NA 0 0 0 0C147 0 0 NA 0 0 0 0

C148 0 0 NA 0 0 0 0C149 0 0 NA 0 0 0 0C15 1 0.75 NA 1 0 0.818 13.488C150 0 0 NA 0 0 0 0C151 0 0 NA 0 0 0 0C152 0 0 NA 0 0 0 0C153 0 0 NA 0 0 0 0C154 0 0 NA 0 0 0 0C155 0 0 NA 0 0 0 0C158 0 0 NA 0 0 0 0C159 0 0 NA 0 0 0 0C16 1 0.75 NA 1 0 0.818 13.488C162 0 0 NA 0 0 0 0C163 0 0 NA 0 0 0 0C165 0 0 NA 0 0 0 0C166 0 0 NA 0 0 0 0C167 0 0 NA 0 0 0 0C168 0 0 NA 0 0 0 0C169 0 0 NA 0 0 0 0C17 1 0.75 NA 1 0 0.818 13.488C170 0 0 NA 0 0 0 0C171 0 0 NA 0 0 0 0C174 0 0 NA 0 0 0 0C175 0 0 NA 0 0 0 0C176 0 0 NA 0 0 0 0C177 0 0 NA 0 0 0 0C178 0 0 NA 0 0 0 0C179 0 0 NA 0 0 0 0C180 0 0 NA 0 0 0 0C181 0 0 NA 0 0 0 0C182 0 0 NA 0 0 0 0C183 0 0 NA 0 0 0 0C19 1 0.75 NA 1 0 0.818 13.488C20 1 0.75 NA 1 0 0.818 13.488C25 0 0 NA 0 0 0 0C35 1 0.75 NA 1 0 0.818 13.488C4 0 0 NA 0 0 0 0C40 0 0 NA 0 0 0 0C41 0 0 NA 0 0 0 0C47 1 0.75 NA 1 0 0.818 13.488C5 1 0.75 NA 1 0 0.818 13.488C50 1 0.75 NA 1 0 0.818 13.488C54 0 0 NA 0 0 0 0C6 1 0.75 NA 1 0 0.818 13.488C66 0 0 NA 0 0 0 0C7 0 0 NA 0 0 0 0C8 0 0 NA 0 0 0 0C81 0 0 NA 0 0 0 0C82 0 0 NA 0 0 0 0C85 1 0.75 NA 1 0 0.818 13.488

C86 0 0 NA 0 0 0 0C87 0 0 NA 0 0 0 0C88 0 0 NA 0 0 0 0C9 0 0 NA 0 0 0 0C94 0 0 NA 0 0 0 0C95 0 0 NA 0 0 0 0C96 0 0 NA 0 0 0 0Table A.14Polarized CapacitorsDevice P C O L A RDS DSC12 0 0 0 0 0 0 0C160 0 0 0 0 0 0 0C161 0 0 0 0 0 0 0C172 1 0.75 1 1 0 0.835 13.767C173 1 0.75 1 1 0 0.835 13.767C18 0 0 0 0 0 0 0C44 1 0.75 1 1 0 0.835 13.767C45 0 0 0 0 0 0 0C46 0 0 0 0 0 0 0C53 0 0 0 0 0 0 0C55 0 0 0 0 0 0 0C56 0 0 0 0 0 0 0C58 0 0 0 0 0 0 0C59 0 0 0 0 0 0 0Table A.15ConnectorsDevice P C O L A RDS DSX1 1 1 1 1 0 0.968 14.464X2 1 1 1 1 0 0.968 14.464X3 1 1 1 1 0 0.968 14.464X7 1 1 1 1 0 0.968 14.464X12 0 0 0 0 0 0 0X13 0 0 0 0 0 0 0X14 0 0 0 0 0 0 0Table A.16Digital CircuitsDevice P C O L A RDS DSD10 1 0.75 1 1 0 0.835 26.598D11 1 0.75 1 1 0 0.835 26.598D12 1 0.75 1 1 0 0.835 26.598D13 1 0.75 1 1 0 0.835 26.598D14 1 0.75 1 1 0 0.835 26.598D16 1 0.75 1 1 0 0.835 26.598

D17 1 0.75 1 1 0 0.835 26.598D18 1 0.75 1 1 0 0.835 26.598D2 1 0.75 1 1 0 0.835 26.598D4 1 0.75 1 1 0 0.835 26.598D6 1 0.75 1 1 0 0.835 26.598D9 1 1 1 1 0 0.968 30.811Table A.17DiodesDevice P C O L A RDS DSV1 0 0 0 0 0 0 0V12 0 0 0 0 0 0 0V13 0 0 0 0 0 0 0V14 1 0.75 1 1 0 0.835 17.726V15 1 0.75 1 1 0 0.835 17.726V17 0 0 0 0 0 0 0V18 0 0 0 0 0 0 0V19 0 0 0 0 0 0 0V20 0 0 0 0 0 0 0V21 0 0 0 0 0 0 0V27 0 0 0 0 0 0 0V3 0 0 0 0 0 0 0V33 0 0 0 0 0 0 0V36 0 0 0 0 0 0 0V37 0 0 0 0 0 0 0V38 0 0 0 0 0 0 0V39 0 0 0 0 0 0 0V4 0 0 0 0 0 0 0V40 0 0 0 0 0 0 0V42 0 0 0 0 0 0 0V43 0 0 0 0 0 0 0V45 0 0 0 0 0 0 0V46 0 0 0 0 0 0 0V48 0 0 0 0 0 0 0V49 0 0 0 0 0 0 0V54 1 0.75 1 1 0 0.835 17.726V55 1 0.75 1 1 0 0.835 17.726V6 1 0.75 1 1 0 0.835 17.726V60 0 0 0 0 0 0 0V63 1 0.75 1 1 0 0.835 17.726V7 1 0.75 1 1 0 0.835 17.726V79 1 0.75 1 1 0 0.835 17.726V8 1 0.75 1 1 0 0.835 17.726V80 0 0 0 0 0 0 0V82 1 0.75 1 1 0 0.835 17.726V87 1 0.75 1 1 0 0.835 17.726V88 0 0 0 0 0 0 0V89 0 0 0 0 0 0 0V9 0 0 0 0 0 0 0

V90 0 0 0 0 0 0 0V91 0 0 0 0 0 0 0V92 0 0 0 0 0 0 0V93 0 0 0 0 0 0 0V94 0 0 0 0 0 0 0Table A.18FilterDevice P C O L A RDS DSZ1 1 0.75 1 1 0 0.835 17.481Table A.19InductorsDevice P C O L A RDS DSL3 1 0.75 NA 1 0 0.818 192.114L4 1 0.75 NA 1 0 0.818 192.114L5 1 0.75 NA 1 0 0.818 192.114L6 1 0.75 NA 1 0 0.818 192.114L7 1 0.75 NA 1 0 0.818 192.114L8 1 0.75 NA 1 0 0.818 192.114Table A.20OscillatorDevice P C O L A RDS DSB1 1 0.75 1 1 0 0.835 417.640Table A.21ResistorsDevice P C O L A RDS DSR1 0 0 NA 0 0 0 0R10 1 0.75 NA 1 0 0.818 17.072R100 1 0.75 NA 1 0 0.818 17.072R102 1 0.75 NA 1 0 0.818 17.072R103 1 0.75 NA 1 0 0.818 17.072R104 0 0 NA 0 0 0 0R105 1 0.75 NA 1 0 0.818 17.072R106 1 0.75 NA 1 0 0.818 17.072R107 0 0 NA 0 0 0 0R108 0 0 NA 0 0 0 0R109 1 0.75 NA 1 0 0.818 17.072R11 1 0.75 NA 1 0 0.818 17.072R110 1 0.75 NA 1 0 0.818 17.072R112 0 0 NA 0 0 0 0R120 0 0 NA 0 0 0 0R13 0 0 NA 0 0 0 0R130 1 0.75 NA 1 0 0.818 17.072R136 0 0 NA 0 0 0 0R138 1 0.75 NA 1 0 0.818 17.072

R139 1 0.75 NA 1 0 0.818 17.072R14 0 0 NA 0 0 0 0R140 1 0.75 NA 1 0 0.818 17.072R15 0 0 NA 0 0 0 0R152 1 0.75 NA 1 0 0.818 17.072R16 1 0.75 NA 1 0 0.818 17.072R162 0 0 NA 0 0 0 0R167 0 0 NA 0 0 0 0R168 0 0 NA 0 0 0 0R169 0 0 NA 0 0 0 0R172 0 0 NA 0 0 0 0R173 0 0 NA 0 0 0 0R19 1 0.75 NA 1 0 0.818 17.072R194 0 0 NA 0 0 0 0R195 0 0 NA 0 0 0 0R2 1 0.75 NA 1 0 0.818 17.072R20 1 0.75 NA 1 0 0.818 17.072R21 1 0.75 NA 1 0 0.818 17.072R22 1 0.75 NA 1 0 0.818 17.072R23 0 0 NA 0 0 0 0R231 0 0 NA 0 0 0 0R232 0 0 NA 0 0 0 0R25 1 0.75 NA 1 0 0.818 17.072R253 1 0.75 NA 1 0 0.818 17.072R254 0 0 NA 0 0 0 0R256 1 0.75 NA 1 0 0.818 17.072R258 0 0 NA 0 0 0 0R259 0 0 NA 0 0 0 0R260 0 0 NA 0 0 0 0R261 1 0.75 NA 1 0 0.818 17.072R269 1 0.75 NA 1 0 0.818 17.072R27 1 0.75 NA 1 0 0.818 17.072R270 1 0.75 NA 1 0 0.818 17.072R271 1 0.75 NA 1 0 0.818 17.072R272 1 0.75 NA 1 0 0.818 17.072R274 0 0 NA 0 0 0 0R275 0 0 NA 0 0 0 0R276 1 0.75 NA 1 0 0.818 17.072R278 0 0 NA 0 0 0 0R279 1 0.75 NA 1 0 0.818 17.072R28 1 0.75 NA 1 0 0.818 17.072R280 1 0.75 NA 1 0 0.818 17.072R281 0 0 NA 0 0 0 0R282 0 0 NA 0 0 0 0R283 0 0 NA 0 0 0 0R284 0 0 NA 0 0 0 0R285 1 0.75 NA 1 0 0.818 17.072R286 1 0.75 NA 1 0 0.818 17.072R287 0 0 NA 0 0 0 0R288 1 0.75 NA 1 0 0.818 17.072

R289 1 0.75 NA 1 0 0.818 17.072R29 1 0.75 NA 1 0 0.818 17.072R293 1 0.75 NA 1 0 0.818 17.072R294 0 0 NA 0 0 0 0R295 0 0 NA 0 0 0 0R296 0 0 NA 0 0 0 0R297 0 0 NA 0 0 0 0R298 0 0 NA 0 0 0 0R299 0 0 NA 0 0 0 0R3 0 0 NA 0 0 0 0R30 1 0.75 NA 1 0 0.818 17.072R300 0 0 NA 0 0 0 0R301 0 0 NA 0 0 0 0R31 0 0 NA 0 0 0 0R33 1 0.75 NA 1 0 0.818 17.072R34 1 0.75 NA 1 0 0.818 17.072R35 1 0.75 NA 1 0 0.818 17.072R36 1 0.75 NA 1 0 0.818 17.072R38 1 0.75 NA 1 0 0.818 17.072R39 0 0 NA 0 0 0 0R4 1 0.75 NA 1 0 0.818 17.072R40 0 0 NA 0 0 0 0R41 0 0 NA 0 0 0 0R42 0 0 NA 0 0 0 0R45 0 0 NA 0 0 0 0R46 1 0.75 NA 1 0 0.818 17.072R47 1 0.75 NA 1 0 0.818 17.072R48 1 0.75 NA 1 0 0.818 17.072R49 1 0.75 NA 1 0 0.818 17.072R5 1 0.75 NA 1 0 0.818 17.072R50 1 0.75 NA 1 0 0.818 17.072R51 1 0.75 NA 1 0 0.818 17.072R52 1 0.75 NA 1 0 0.818 17.072R53 0 0 NA 0 0 0 0R54 0 0 NA 0 0 0 0R55 1 0.75 NA 1 0 0.818 17.072R58 1 0.75 NA 1 0 0.818 17.072R6 0 0 NA 0 0 0 0R62 1 0.75 NA 1 0 0.818 17.072R63 1 0.75 NA 1 0 0.818 17.072R65 1 0.75 NA 1 0 0.818 17.072R66 1 0.75 NA 1 0 0.818 17.072R67 0 0 NA 0 0 0 0R68 1 0.75 NA 1 0 0.818 17.072R69 1 0.75 NA 1 0 0.818 17.072R71 1 0.75 NA 1 0 0.818 17.072R76 1 0.75 NA 1 0 0.818 17.072R8 1 0.75 NA 1 0 0.818 17.072R82 1 0.75 NA 1 0 0.818 17.072R83 1 0.75 NA 1 0 0.818 17.072

R86 0 0 NA 0 0 0 0R89 1 0.75 NA 1 0 0.818 17.072R9 0 0 NA 0 0 0 0R90 1 0.75 NA 1 0 0.818 17.072R93 1 0.75 NA 1 0 0.818 17.072R94 1 0.75 NA 1 0 0.818 17.072R95 1 0.75 NA 1 0 0.818 17.072R96 1 0.75 NA 1 0 0.818 17.072R97 1 0.75 NA 1 0 0.818 17.072R99 1 0.75 NA 1 0 0.818 17.072Table A.22TransformerDevice P C O L A RDS DST1 1 1 1 1 0 0.968 14.464Table A.23TransistorsDevice P C O L A RDS DSV22 1 0.75 1 1 0 0.835 43.881V23 1 0.75 1 1 0 0.835 43.881V28 1 0.75 1 1 0 0.835 43.881V29 1 0.75 1 1 0 0.835 43.881V30 1 0.75 1 1 0 0.835 43.881V31 1 0.75 1 1 0 0.835 43.881V32 1 0.75 1 1 0 0.835 43.881V35 1 0.75 1 1 0 0.835 43.881V41 0 0 0 0 0 0 0V44 1 0.75 1 1 0 0.835 43.881V5 1 0.75 1 1 0 0.835 43.881V56 1 0.75 1 1 0 0.835 43.881V62 1 0.75 1 1 0 0.835 43.881V83 1 0.75 1 1 0 0.835 43.881V86 1 0.75 1 1 0 0.835 43.881Table A.24A.3Special testsA.3.1HVIPolarized CapacitorsDevice P C O L A RDS DSC12 1 0 1 0 0 0.284 4.676C160 1 0 1 0 0 0.284 4.676C161 1 0 1 0 0 0.284 4.676C172 1 0 1 0 0 0.284 4.676

C173 1 0 1 0 0 0.284 4.676C18 1 0 1 0 0 0.284 4.676C44 1 0 1 0 0 0.284 4.676C45 1 0 1 0 0 0.284 4.676C46 1 0 1 0 0 0.284 4.676C53 1 0 1 0 0 0.284 4.676C55 1 0 1 0 0 0.284 4.676C56 1 0 1 0 0 0.284 4.676C58 1 0 1 0 0 0.284 4.676C59 1 0 1 0 0 0.284 4.676Table A.25A.3.2ProgrammingConnectorsDevice P C O L A RDS DSX1 1 1 1 1 0 0.968 14.464X2 0 0 0 0 0 0 0X3 0 0 0 0 0 0 0X7 0 0 0 0 0 0 0X12 1 1 1 1 0 0.968 14.464X13 0 0 0 0 0 0 0X14 0 0 0 0 0 0 0Table A.26BConnectionsIn this section, the grades attained by each device’s connection in the different testsperformed to them are shown.B.1 ICTAnalog CircuitsDevice S O Q Tested Pins CSA1 NA 0 0 0 0A11 NA 0 0 0 0A12 NA 0 0 0 0A15 NA 0 0 0 0A16 NA 1 0 14 99.214A17 NA 0 0 0 0A18 NA 0 0 0 0A2 NA 0 0 0 0A20 NA 0 0 0 0A21 NA 0 0 0 0A4 NA 0 0 0 0

A5 NA 1 0 16 113.387A6 NA 1 0 16 113.387A7 NA 0 0 0 0A8 NA 1 0 16 113.387A9 NA 1 0 14 99.214Table B.1Non-polarized CapacitorsDevice S O Q Tested Pins CSC10 NA 1 0 2 14.173C11 NA 1 0 2 14.173C118 NA 1 0 2 14.173C122 NA 0 0 0 0C13 NA 1 0 2 14.173C133 NA 1 0 2 14.173C134 NA 1 0 2 14.173C135 NA 1 0 2 14.173C136 NA 0 0 0 0C137 NA 1 0 2 14.173C138 NA 0 0 0 0C139 NA 0 0 0 0C14 NA 1 0 2 14.173C140 NA 1 0 2 14.173C141 NA 1 0 2 14.173C142 NA 0 0 0 0C143 NA 0 0 0 0C144 NA 0 0 0 0C145 NA 0 0 0 0C146 NA 0 0 0 0C147 NA 0 0 0 0C148 NA 0 0 0 0C149 NA 0 0 0 0C15 NA 0 0 0 0C150 NA 0 0 0 0C151 NA 0 0 0 0C152 NA 0 0 0 0C153 NA 0 0 0 0C154 NA 0 0 0 0C155 NA 0 0 0 0C158 NA 0 0 0 0C159 NA 0 0 0 0C16 NA 1 0 2 14.173C162 NA 1 0 2 14.173C163 NA 1 0 2 14.173C165 NA 0 0 0 0C166 NA 1 0 2 14.173C167 NA 1 0 2 14.173C168 NA 1 0 2 14.173C169 NA 1 0 2 14.173

C17 NA 1 0 2 14.173C170 NA 0 0 0 0C171 NA 0 0 0 0C174 NA 1 0 2 14.173C175 NA 1 0 2 14.173C176 NA 1 0 2 14.173C177 NA 1 0 2 14.173C178 NA 0 0 0 0C179 NA 0 0 0 0C180 NA 0 0 0 0C181 NA 0 0 0 0C182 NA 0 0 0 0C183 NA 0 0 0 0C19 NA 1 0 2 14.173C20 NA 1 0 2 14.173C25 NA 0 0 0 0C35 NA 1 0 2 14.173C4 NA 0 0 0 0C40 NA 1 0 2 14.173C41 NA 0 0 0 0C47 NA 1 0 2 14.173C5 NA 1 0 2 14.173C50 NA 1 0 2 14.173C54 NA 1 0 2 14.173C6 NA 1 0 2 14.173C66 NA 1 0 2 14.173C7 NA 1 0 2 14.173C8 NA 1 0 2 14.173C81 NA 1 0 2 14.173C82 NA 1 0 2 14.173C85 NA 1 0 2 14.173C86 NA 1 0 2 14.173C87 NA 1 0 2 14.173C88 NA 1 0 2 14.173C9 NA 1 0 2 14.173C94 NA 0 0 0 0C95 NA 0 0 0 0C96 NA 1 0 2 14.1734Table B.2Polarized CapacitorsDevice S O Q Tested Pins CSC12 NA 1 0 2 14.173C160 NA 1 0 2 14.173C161 NA 1 0 2 14.173C172 NA 1 0 2 14.173C173 NA 1 0 2 14.173C18 NA 1 0 2 14.173C44 NA 1 0 2 14.173

C45 NA 0 0 0 0C46 NA 1 0 2 14.173C53 NA 1 0 2 14.173C55 NA 1 0 2 14.173C56 NA 0 0 0 0C58 NA 0 0 0 0C59 NA 0 0 0 0Table B.3ConnectorsDevice S O Q Tested Pins CSX1 NA 1 0 2 14.173X2 NA 0 0 0 0X3 NA 0 0 0 0X7 NA 0 0 0 0X12 NA 0 0 0 0X13 NA 0 0 0 0X14 NA 0 0 0 0Table B.4ConnectorsDevice S O Q Tested Pins CSX1 NA 1 0 2 14.173X2 NA 0 0 0 0X3 NA 0 0 0 0X7 NA 0 0 0 0X12 NA 0 0 0 0X13 NA 0 0 0 0X14 NA 0 0 0 0Table B.5Digital CircuitsDevice S O Q Tested Pins CSD10 NA 0 0 0 0D11 NA 0 0 0 0D12 NA 1 0 20 141.734D13 NA 1 0 20 141.734D14 NA 1 0 20 141.734D16 NA 0 0 0 0D17 NA 1 0 20 141.734D18 NA 1 0 20 141.734D2 NA 1 0 20 141.734D4 NA 1 0 20 141.734D6 NA 1 0 20 141.734D9 NA 0 0 0 0Table B.6

DiodesDevice S O Q Tested Pins CSV1 NA 1 0 2 14.173V12 NA 1 0 2 14.173V13 NA 1 0 2 14.173V14 NA 1 0 2 14.173V15 NA 1 0 2 14.173V17 NA 1 0 2 14.173V18 NA 1 0 2 14.173V19 NA 1 0 2 14.173V20 NA 1 0 2 14.173V21 NA 1 0 2 14.173V27 NA 1 0 2 14.173V3 NA 1 0 2 14.173V33 NA 1 0 3 21.260V36 NA 1 0 2 14.173V37 NA 1 0 2 14.173V38 NA 1 0 2 14.173V39 NA 1 0 2 14.173V4 NA 1 0 2 14.173V40 NA 1 0 2 14.173V42 NA 1 0 3 21.260V43 NA 1 0 2 14.173V45 NA 1 0 2 14.173V46 NA 1 0 3 21.260V48 NA 1 0 2 14.173V49 NA 1 0 2 14.173V54 NA 1 0 2 14.173V55 NA 1 0 2 14.173V6 NA 1 0 2 14.173V60 NA 1 0 2 14.173V63 NA 1 0 3 21.260V7 NA 1 0 3 21.260V79 NA 1 0 2 14.173V8 NA 1 0 3 21.260V80 NA 1 0 2 14.173V82 NA 0 0 0 0V87 NA 1 0 3 21.260V88 NA 1 0 2 14.173V89 NA 1 0 2 14.173V9 NA 1 0 2 14.173V90 NA 1 0 2 14.173V91 NA 1 0 2 14.173V92 NA 1 0 2 14.173V93 NA 1 0 2 14.173V94 NA 1 0 2 14.173Table B.7

FilterDevice S O Q Tested Pins CSZ1 NA 1 0 6 42.520Table B.8FilterDevice S O Q Tested Pins CSL3 NA 1 0 2 14.173L4 NA 1 0 2 14.173L5 NA 1 0 2 14.173L6 NA 1 0 2 14.173L7 NA 1 0 2 14.173L8 NA 1 0 2 14.173Table B.9OscillatorDevice S O Q Tested Pins CSB1 NA 1 0 4 28.347Table B.10ResistorsDevice S O Q Tested Pins CSR1 NA 1 0 2 14.173R10 NA 1 0 2 14.173R100 NA 1 0 2 14.173R102 NA 1 0 2 14.173R103 NA 1 0 2 14.173R104 NA 1 0 2 14.173R105 NA 1 0 2 14.173R106 NA 1 0 2 14.173R107 NA 1 0 2 14.173R108 NA 1 0 2 14.173R109 NA 1 0 2 14.173R11 NA 1 0 2 14.173R110 NA 1 0 2 14.173R112 NA 1 0 2 14.173R120 NA 1 0 2 14.173R13 NA 1 0 2 14.173R130 NA 1 0 2 14.173R136 NA 1 0 2 14.173R138 NA 1 0 2 14.173R139 NA 1 0 2 14.173R14 NA 1 0 2 14.173R140 NA 1 0 2 14.173R15 NA 1 0 2 14.173R152 NA 1 0 2 14.173

R16 NA 1 0 2 14.173R162 NA 1 0 2 14.173R167 NA 1 0 2 14.173R168 NA 1 0 2 14.173R169 NA 1 0 2 14.173R172 NA 1 0 2 14.173R173 NA 1 0 2 14.173R19 NA 1 0 2 14.173R194 NA 1 0 2 14.173R195 NA 1 0 2 14.173R2 NA 1 0 2 14.173R20 NA 1 0 2 14.173R21 NA 1 0 2 14.173R22 NA 1 0 2 14.173R23 NA 1 0 2 14.173R231 NA 1 0 2 14.173R232 NA 1 0 2 14.173R25 NA 1 0 2 14.173R253 NA 1 0 2 14.173R254 NA 1 0 2 14.173R256 NA 0 0 0 0R258 NA 1 0 2 14.173R259 NA 1 0 2 14.173R260 NA 1 0 2 14.173R261 NA 1 0 2 14.173R269 NA 1 0 2 14.173R27 NA 1 0 2 14.173R270 NA 1 0 2 14.173R271 NA 1 0 2 14.173R272 NA 1 0 2 14.173R274 NA 1 0 2 14.173R275 NA 1 0 2 14.173R276 NA 1 0 2 14.173R278 NA 1 0 2 14.173R279 NA 1 0 2 14.173R28 NA 1 0 2 14.173R280 NA 1 0 2 14.173R281 NA 1 0 2 14.173R282 NA 1 0 2 14.173R283 NA 1 0 2 14.173R284 NA 1 0 2 14.173R285 NA 1 0 2 14.173R286 NA 1 0 2 14.173R287 NA 1 0 2 14.173R288 NA 1 0 2 14.173R289 NA 1 0 2 14.173R29 NA 1 0 2 14.173R293 NA 1 0 2 14.173R294 NA 1 0 2 14.173R295 NA 1 0 2 14.173

R296 NA 1 0 2 14.173R297 NA 1 0 2 14.173R298 NA 1 0 2 14.173R299 NA 1 0 2 14.173R3 NA 1 0 2 14.173R30 NA 1 0 2 14.173R300 NA 1 0 2 14.173R301 NA 1 0 2 14.173R31 NA 1 0 2 14.173R33 NA 1 0 2 14.173R34 NA 1 0 2 14.173R35 NA 1 0 2 14.173R36 NA 1 0 2 14.173R38 NA 1 0 2 14.173R39 NA 1 0 2 14.173R4 NA 1 0 2 14.173R40 NA 1 0 2 14.173R41 NA 1 0 2 14.173R42 NA 1 0 2 14.173R45 NA 1 0 2 14.173R46 NA 1 0 2 14.173R47 NA 1 0 2 14.173R48 NA 1 0 2 14.173R49 NA 1 0 2 14.173R5 NA 1 0 2 14.173R50 NA 1 0 2 14.173R51 NA 1 0 2 14.173R52 NA 1 0 2 14.173R53 NA 1 0 2 14.173R54 NA 1 0 2 14.173R55 NA 1 0 2 14.173R58 NA 1 0 2 14.173R6 NA 1 0 2 14.173R62 NA 1 0 2 14.173R63 NA 1 0 2 14.173R65 NA 1 0 2 14.173R66 NA 1 0 2 14.173R67 NA 1 0 2 14.173R68 NA 1 0 2 14.173R69 NA 1 0 2 14.173R71 NA 1 0 2 14.173R76 NA 1 0 2 14.173R8 NA 1 0 2 14.173R82 NA 1 0 2 14.173R83 NA 1 0 2 14.173R86 NA 1 0 2 14.173R89 NA 1 0 2 14.173R9 NA 1 0 2 14.173R90 NA 1 0 2 14.173R93 NA 1 0 2 14.173

R94 NA 1 0 2 14.173R95 NA 1 0 2 14.173R96 NA 1 0 2 14.173R97 NA 1 0 2 14.173R99 NA 1 0 2 14.173Table B.11TransformerDevice S O Q Tested Pins CST1 NA 1 0 13 92.127Table B.12TransistorsDevice S O Q Tested Pins CSV22 NA 1 0 4 28.347V23 NA 1 0 4 28.347V28 NA 1 0 4 28.347V29 NA 1 0 3 21.260V30 NA 1 0 3 21.260V31 NA 1 0 3 21.260V32 NA 1 0 3 21.260V35 NA 1 0 4 28.347V41 NA 1 0 6 42.520V44 NA 1 0 3 21.260V5 NA 1 0 3 21.260V56 NA 1 0 4 28.347V62 NA 1 0 3 21.260V83 NA 1 0 6 42.520V86 NA 1 0 3 21.260Table B.13B.2 Functional TestAnalog CircuitsDevice S O Q Tested Pins CSA1 NA 1 0 5 35.434A11 NA 1 0 5 35.434A12 NA 1 0 3 21.260A15 NA 1 0 4 28.347A16 NA 1 0 14 99.214A17 NA 1 0 7 49.607A18 NA 1 0 7 49.607A2 NA 1 0 5 35.434A20 NA 1 0 29 205.515A21 NA 1 0 34 240.948A4 NA 1 0 7 49.607

A5 NA 1 0 16 113.387A6 NA 1 0 16 113.387A7 NA 1 0 5 35.434A8 NA 1 0 16 113.387A9 NA 1 0 14 99.214Table B.14Non-polarized CapacitorsDevice S O Q Tested Pins CSC10 NA 0 0 0 0C11 NA 1 0 2 14.173C118 NA 0 0 0 0C122 NA 0 0 0 0C13 NA 1 0 2 14.173C133 NA 1 0 2 14.173C134 NA 0 0 0 0C135 NA 0 0 0 0C136 NA 0 0 0 0C137 NA 0 0 0 0C138 NA 0 0 0 0C139 NA 0 0 0 0C14 NA 1 0 2 14.173C140 NA 0 0 0 0C141 NA 0 0 0 0C142 NA 0 0 0 0C143 NA 0 0 0 0C144 NA 0 0 0 0C145 NA 0 0 0 0C146 NA 0 0 0 0C147 NA 0 0 0 0C148 NA 0 0 0 0C149 NA 0 0 0 0C15 NA 1 0 2 14.173C150 NA 0 0 0 0C151 NA 0 0 0 0C152 NA 0 0 0 0C153 NA 0 0 0 0C154 NA 0 0 0 0C155 NA 0 0 0 0C158 NA 0 0 0 0C159 NA 0 0 0 0C16 NA 1 0 2 14.173C162 NA 0 0 0 0C163 NA 0 0 0 0C165 NA 0 0 0 0C166 NA 0 0 0 0C167 NA 0 0 0 0C168 NA 0 0 0 0C169 NA 0 0 0 0C17 NA 1 0 2 14.173

C170 NA 0 0 0 0C171 NA 0 0 0 0C174 NA 0 0 0 0C175 NA 0 0 0 0C176 NA 0 0 0 0C177 NA 0 0 0 0C178 NA 0 0 0 0C179 NA 0 0 0 0C180 NA 0 0 0 0C181 NA 0 0 0 0C182 NA 0 0 0 0C183 NA 0 0 0 0C19 NA 1 0 2 14.173C20 NA 1 0 2 14.173C25 NA 0 0 0 0C35 NA 1 0 2 14.173C4 NA 0 0 0 0C40 NA 0 0 0 0C41 NA 0 0 0 0C47 NA 1 0 2 14.173C5 NA 1 0 2 14.173C50 NA 1 0 2 14.173C54 NA 0 0 0 0C6 NA 1 0 2 14.173C66 NA 0 0 0 0C7 NA 0 0 0 0C8 NA 0 0 0 0C81 NA 0 0 0 0C82 NA 0 0 0 0C85 NA 1 0 2 14.173C86 NA 0 0 0 0C87 NA 0 0 0 0C88 NA 0 0 0 0C9 NA 0 0 0 0C94 NA 0 0 0 0C95 NA 0 0 0 0C96 NA 0 0 0 0Table B.15Polarized CapacitorsDevice S O Q Tested Pins CSC12 NA 0 0 0 0C160 NA 0 0 0 0C161 NA 0 0 0 0C172 NA 1 0 2 14.173C173 NA 1 0 2 14.173C18 NA 0 0 0 0C44 NA 1 0 2 14.173C45 NA 0 0 0 0

C46 NA 0 0 0 0C53 NA 0 0 0 0C55 NA 0 0 0 0C56 NA 0 0 0 0C58 NA 0 0 0 0C59 NA 0 0 0 0Table B.16ConnectorsDevice S O Q Tested Pins CSX1 NA 1 0 2 14.173X2 NA 1 0 3 21.260X3 NA 1 0 1 7.087X7 NA 1 0 10 70.867X12 NA 1 0 0 0X13 NA 0 0 0 0X14 NA 0 0 0 0Table B.17Digital CircuitsDevice S O Q Tested Pins CSD10 NA 1 0 125 885.838D11 NA 1 0 63 446.463D12 NA 1 0 20 141.734D13 NA 1 0 19 134.647D14 NA 1 0 20 141.734D16 NA 1 0 8 56.694D17 NA 1 0 16 113.387D18 NA 1 0 20 141.734D2 NA 1 0 20 141.734D4 NA 1 0 20 141.734D6 NA 1 0 20 141.734D9 NA 1 0 3 21.260Table B.18DiodesDevice S O Q Tested Pins CSV1 NA 0 0 0 0V12 NA 0 0 0 0V13 NA 0 0 0 0V14 NA 1 0 2 14.173V15 NA 1 0 2 14.173V17 NA 0 0 0 0V18 NA 0 0 0 0V19 NA 0 0 0 0V20 NA 0 0 0 0

V21 NA 0 0 0 0V27 NA 0 0 0 0V3 NA 0 0 0 0V33 NA 0 0 0 0V36 NA 0 0 0 0V37 NA 0 0 0 0V38 NA 0 0 0 0V39 NA 0 0 0 0V4 NA 0 0 0 0V40 NA 0 0 0 0V42 NA 0 0 0 0V43 NA 0 0 0 0V45 NA 0 0 0 0V46 NA 0 0 0 0V48 NA 0 0 0 0V49 NA 0 0 0 0V54 NA 1 0 2 14.173V55 NA 1 0 2 14.173V6 NA 1 0 2 14.173V60 NA 0 0 0 0V63 NA 1 0 3 21.260V7 NA 1 0 3 21.260V79 NA 1 0 2 14.173V8 NA 1 0 3 21.260V80 NA 0 0 0 0V82 NA 1 0 6 42.520V87 NA 1 0 3 21.260V88 NA 0 0 0 0V89 NA 0 0 0 0V9 NA 0 0 0 0V90 NA 0 0 0 0V91 NA 0 0 0 0V92 NA 0 0 0 0V93 NA 0 0 0 0V94 NA 0 0 0 0Table B.19FilterDevice S O Q Tested Pins CSZ1 NA 1 0 6 42.520Table B.20FilterDevice S O Q Tested Pins CSL3 NA 1 0 2 14.173L4 NA 1 0 2 14.173L5 NA 1 0 2 14.173

L6 NA 1 0 2 14.173L7 NA 1 0 2 14.173L8 NA 1 0 2 14.173Table B.21OscillatorDevice S O Q Tested Pins CSB1 NA 1 0 4 28.347Table B.22ResistorsDevice S O Q Tested Pins CSR1 NA 0 0 0 0R10 NA 1 0 2 14.173R100 NA 1 0 2 14.173R102 NA 1 0 2 14.173R103 NA 1 0 2 14.173R104 NA 0 0 0 0R105 NA 1 0 2 14.173R106 NA 1 0 2 14.173R107 NA 0 0 0 0R108 NA 0 0 0 0R109 NA 1 0 2 14.173R11 NA 1 0 2 14.173R110 NA 1 0 2 14.173R112 NA 0 0 0 0R120 NA 0 0 0 0R13 NA 0 0 0 0R130 NA 1 0 2 14.173R136 NA 0 0 0 0R138 NA 1 0 2 14.173R139 NA 1 0 2 14.173R14 NA 0 0 0 0R140 NA 1 0 2 14.173R15 NA 0 0 0 0R152 NA 1 0 2 14.173R16 NA 1 0 2 14.173R162 NA 0 0 0 0R167 NA 0 0 0 0R168 NA 0 0 0 0R169 NA 0 0 0 0R172 NA 0 0 0 0R173 NA 0 0 0 0R19 NA 1 0 2 14.173R194 NA 0 0 0 0R195 NA 0 0 0 0R2 NA 1 0 2 14.173

R20 NA 1 0 2 14.173R21 NA 1 0 2 14.173R22 NA 1 0 2 14.173R23 NA 0 0 0 0R231 NA 0 0 0 0R232 NA 0 0 0 0R25 NA 1 0 2 14.173R253 NA 1 0 2 14.173R254 NA 0 0 2 0R256 NA 1 0 2 14.173R258 NA 0 0 0 0R259 NA 0 0 0 0R260 NA 0 0 0 0R261 NA 1 0 2 14.173R269 NA 1 0 2 14.173R27 NA 1 0 2 14.173R270 NA 1 0 2 14.173R271 NA 1 0 2 14.173R272 NA 1 0 2 14.173R274 NA 0 0 0 0R275 NA 0 0 0 0R276 NA 1 0 2 14.173R278 NA 0 0 0 0R279 NA 1 0 2 14.173R28 NA 1 0 2 14.173R280 NA 1 0 2 14.173R281 NA 0 0 0 0R282 NA 0 0 0 0R283 NA 0 0 0 0R284 NA 0 0 0 0R285 NA 1 0 2 14.173R286 NA 1 0 2 14.173R287 NA 0 0 0 0R288 NA 1 0 2 14.173R289 NA 1 0 2 14.173R29 NA 1 0 2 14.173R293 NA 1 0 2 14.173R294 NA 0 0 0 0R295 NA 0 0 0 0R296 NA 0 0 0 0R297 NA 0 0 0 0R298 NA 0 0 0 0R299 NA 0 0 0 0R3 NA 0 0 0 0R30 NA 1 0 2 14.173R300 NA 0 0 0 0R301 NA 0 0 0 0R31 NA 0 0 0 0R33 NA 1 0 2 14.173R34 NA 1 0 2 14.173

R35 NA 1 0 2 14.173R36 NA 1 0 2 14.173R38 NA 1 0 2 14.173R39 NA 0 0 0 0R4 NA 1 0 2 14.173R40 NA 0 0 0 0R41 NA 0 0 0 0R42 NA 0 0 0 0R45 NA 0 0 0 0R46 NA 1 0 2 14.173R47 NA 1 0 2 14.173R48 NA 1 0 2 14.173R49 NA 1 0 2 14.173R5 NA 1 0 2 14.173R50 NA 1 0 2 14.173R51 NA 1 0 2 14.173R52 NA 1 0 2 14.173R53 NA 0 0 0 0R54 NA 0 0 0 0R55 NA 1 0 2 14.173R58 NA 1 0 2 14.173R6 NA 0 0 0 0R62 NA 1 0 2 14.173R63 NA 1 0 2 14.173R65 NA 1 0 2 14.173R66 NA 1 0 2 14.173R67 NA 0 0 0 0R68 NA 1 0 2 14.173R69 NA 1 0 2 14.173R71 NA 1 0 2 14.173R76 NA 1 0 2 14.173R8 NA 1 0 2 14.173R82 NA 1 0 2 14.173R83 NA 1 0 2 14.173R86 NA 0 0 0 0R89 NA 1 0 2 14.173R9 NA 0 0 0 0R90 NA 1 0 2 14.173R93 NA 1 0 2 14.173R94 NA 1 0 2 14.173R95 NA 1 0 2 14.173R96 NA 1 0 2 14.173R97 NA 1 0 2 14.173R99 NA 1 0 2 14.173Table B.23TransformerDevice S O Q Tested Pins CST1 NA 1 0 13 92.127Table B.24

TransistorsDevice S O Q Tested Pins CSV22 NA 1 0 4 28.347V23 NA 1 0 4 28.347V28 NA 1 0 4 28.347V29 NA 1 0 3 21.260V30 NA 1 0 3 21.260V31 NA 1 0 3 21.260V32 NA 1 0 3 21.260V35 NA 1 0 4 28.347V41 NA 0 0 0 0V44 NA 1 0 3 21.260V5 NA 1 0 3 21.260V56 NA 1 0 4 28.347V62 NA 1 0 3 21.260V83 NA 1 0 6 42.520V86 NA 1 0 3 21.260Table B.25B.3Special TestsB.3.1Opens XpressAnalog CircuitsDevice S O Q Tested Pins CSA1 NA 1 0 8 56.694A11 NA 1 0 8 56.694A12 NA 1 0 3 21.260A15 NA 1 0 5 35.434A16 NA 0 0 0 0A17 NA 1 0 7 49.607A18 NA 1 0 7 49.607A2 NA 1 0 8 56.694A20 NA 1 0 31 219.688A21 NA 1 0 36 255.121A4 NA 1 0 8 56.694A5 NA 0 0 0 0A6 NA 0 0 0 0A7 NA 1 0 8 56.694A8 NA 0 0 0 0A9 NA 0 0 0 0Table B.26Digital CircuitsDevice S O Q Tested Pins CSD10 NA 1 0 143 1013.399

D11 NA 1 0 76 538.590D12 NA 0 0 0 0D13 NA 0 0 0 0D14 NA 0 0 0 0D16 NA 1 0 8 56.694D17 NA 0 0 0 0D18 NA 0 0 0 0D2 NA 0 0 0 0D4 NA 0 0 0 0D6 NA 0 0 0 0D9 NA 0 0 0 0Table B.27B.3.2ProgrammingConnectorsDevice S O Q Tested Pins CSX1 NA 1 0 0 0X2 NA 0 0 0 0X3 NA 0 0 0 0X7 NA 0 0 0 0X12 NA 1 0 8 56.694X13 NA 0 0 0 0X14 NA 0 0 0 0Table B.28