AV555-PCI-LVDS High Performance Flat Panel/CRT ... - OoCities

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AV555-PCI-LVDS Internal Digital CMOS Panel Interface DefinitionDescription: Selectable 3.3V or 5.0V logic levels. Fully EMI Filtered. Compatibility Note: Internal 50 Pin IDC (J3) is backwards compatible with all otherAVED products. Additional 20 Pin IDC (J10) is a new definition and is required for Dual Pixel Per Clock Panel Interfaces. All cable lengths should bekept to a minimum and the maximum amount of grounds from the board carried across to the panel should always be used.Signal Name AV555Internal 50 PinIDC - J3+5VOLT NCFUSEDVDDSAFE 1,4,5+12VSAFE 2,3+12 V FUSED 6AV555 Internal20 Pin IDC, J1024 Bit TFTSingle Pixel/Clock36 bit TFTDual Pixel/Clock12 Bit TFTDual Pixel/Clock24 Bit ColorDSTN16 Bit ColorDSTNM (DE) 8LP (HS) 10FLM (VS) 11SHFCLK 13P0 15 B0 FB0 FB0 UR0 UR0P1 16 B1 FB1 FB1 UG0 UG0P2 18 B2 FB2 FB2 UB0 UB0P3 19 B3 FB3 FB3 LR0 UR1P4 21 B4 FB4 SB0 LG0 LR0P5 22 B5 FB5 SB1 LB0 LG0P6 24 B6 SB0 SB2 UR1 LB0P7 25 B7 SB1 SB3 UG1 LR1P8 27 G0 SB2 FG0 UB1 UG1P9 28 G1 SB3 FG1 LR1 UB1P10 30 G2 SB4 FG2 LG1 UR2P11 31 G3 SB5 FG3 LB1 UG2P12 33 G4 FG0 SGO UR2 LG1P13 34 G5 FG1 SG1 UG2 LB1P14 36 G6 FG2 SG2 UB2 LR2P15 37 G7 FG3 SG3 LR2 LG2P16 39 R0 FG4 FR0 LG2P17 40 R1 FG5 FR1 LB2P18 42 R2 SG0 FR2 UR3P19 43 R3 SG1 FR3 UG3P20 45 R4 SG2 SR0 UB3P21 46 R5 SG3 SR1 LR3P22 48 R6 SG4 SR2 LG3P23 49 R7 SG5 SR3 LB3P24 2 FR0P25 3 FR1P26 5 FR2P27 6 FR3P28 8 FR4P29 9 FR5P30 11 SR0P31 12 SR1P32 14 SR2P33 15 SR3P34 17 SR4P35 18 SR5GND 7,9,12,14,17,20,23,26,29,32,35,38,41,44,47, 501,4,7,10,13,16,19,20AVED Display Technologies WWW.AVEDDISPLAY. COM AV-555-PCI-LVDS Specification V1.2
AV555-PCI-LVDS LVDS Signal MappingDescription: The following table describes the mapping between the LVDS Transmission Lines and the organization of interface signal thatdrive the LVDS IC’s before they are combined into serial transmission line data. Two discrete 18 Bit LVDS IC’s are used to support all panelinterface types. The most common supported panel interfaces are: Dual Pixel/Clock 18 Bit TFT, Single Pixel/Clock 24 Bit TFT, 24 Bit ColorDSTN, 18 Bit Color DSTN.36 Bit Dual-Pixel/Clock(Industry Standard for XGA andSXGA TFT LVDS Interfaces)24 Bit SinglePixel/Clock24 Bit Color DSTN 18 Bit Color DSTNTXOUT1X DefinitionsTXIN0 First RED 0 - - -TXIN1 First RED 1 Blue 0 UR0 UR0TXIN2 First RED 2 - - -TXIN3 First RED 3 - - -TXIN4 First RED 4 - - -TXIN5 First RED 5 - - -TXIN6 First Green 0 Green 4 UR2 LG1TXIN7 First Green 1 Green 5 UG2 LB1TXIN8 First Green 2 Green 6 UB2 LR2TXIN9 First Green 3 Green 7 LR2 LG2TXIN10 First Green 4 Red 0 LG2 -TXIN11 First Green 5 Red 1 LB2 -TXIN12 First Blue 0 NC (Blue 0) Don’t Use - -TXIN13 First Blue 1 Blue 1 UG0 UG0TXIN14 First Blue 2 Blue 2 UB0 UB0TXIN15 First Blue 3 Blue 3 LR0 UR1TXIN16 First Blue 4 Blue 4 LG0 LR0TXIN17 First Blue 5 Blue 5 LB0 LG0TXIN18 HSYNC HSYNC LP LPTXIN19 VSYNC VSYNC FLM FLMTXIN20 DE DE M MTXCLKIN SHFCLK (Pixel Clock/2) SHFCLK (Pixel Clock) Pixel Clock Pixel ClockTXOUT2X DefinitionsTXIN0 Second RED 0 - Panel Data Clock Panel Data ClockTXIN1 Second RED 1 - - -TXIN2 Second RED 2 - - -TXIN3 Second RED 3 - - -TXIN4 Second RED 4 - - -TXIN5 Second RED 5 - - -TXIN6 Second Green 0 Red 2 UR3 -TXIN7 Second Green 1 Red 3 UG3 -TXIN8 Second Green 2 Red 4 UB3 -TXIN9 Second Green 3 Red 5 LR3 -TXIN10 Second Green 4 Red 6 LG3 -TXIN11 Second Green 5 Red 7 LB3 -TXIN12 Second Blue 0 Blue 6 UR1 LB0TXIN13 Second Blue 1 Blue 7 UG1 LR1TXIN14 Second Blue 2 Green 0 UB1 UG1TXIN15 Second Blue 3 Green 1 LR1 UB1TXIN16 Second Blue 4 Green 2 LG1 UR2TXIN17 Second Blue 5 Green 3 LB1 UG2TXIN18 Pull Down/ J9-1 GPIO/ENABKL Same Same SameTXIN19 Pull Down/J9-2 GPIO/GPIO1 Same Same SameTXIN20 Pull Down/J9-3 GPIO Same Same SameTXCLKIN SHFCLK (Pixel Clock/2) SHFCLK (Pixel Clock) Pixel Clock Pixel ClockAVED Display Technologies WWW.AVEDDISPLAY. COM AV-555-PCI-LVDS SpecificationV1.2
Page 1 and 2: Product SpecificationAVED Display T
Page 3 and 4: Technical data subject to change wi
Page 5: AV555-PCI-LVDS Controller Pin Defin

AV555-PCI-LVDS High Performance Flat Panel/CRT ... - OoCities

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