Internet Data Sheet HYS72T512022HFD–3.7–A Rev. 1.2 - UBiio

December 2006Cover PageHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesDDR2 SDRAMRoHS Compliant ProductsInternet Data SheetRev. 1.2

Internet Data SheetRevision HistoryHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesRevision History: 2006-12-07, Rev. 1.2AllAdapted internet editionPage 19 Updated “Current Spec. and Conditions” on Page 19Page 22 Updated “SPD Codes” on Page 22Previous Revision: 2006-09-13, Rev. 1.1AllConverted to QAG templateWe Listen to Your CommentsWe Listen to Your CommentsAny information within this document that you feel is wrong, unclear or missing at all?Your feedback will help us to continuously improve the quality of this document.Please send your proposal (including a reference to this document) to:techdoc@qimonda.comqag_techdoc_rev400 / 3.2 QAG / 2006-07-21 203292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules1 OverviewThis chapter describes the main characteristics of the 240-Pin Fully-Buffered DDR2 SDRAM Modules product family.1.1 Features• 240-pin Fully-Buffered ECC Dual-In-LineDDR2 SDRAM Module for PC, Workstation and Servermain memory applications.• Module organisation two ranks 512M ×72• JEDEC Standard Double Data Rate 2Synchronous DRAMs (DDR2 SDRAMs) with 1.8 V(± 0.1 V) power supply.• 4GB Module built with 1Gb Dual Die DDR2 SDRAMs in71-ball FBGA Common Package.• Re-drive and re-sync of all address, command, clock anddata signals using AMB (Advanced Memory Buffer).• High-Speed Differential Point-to-Point Link Interface at1.5 V (Jedec standard pending).• Host Interface and AMB component industry standardcompliant.• Supports SMBus protocol interface for access to the AMBconfiguration registers.• Detects errors on the channel and reports them to the hostmemory controller.• Automatic DDR2 DRAM Bus Calibration.• Automatic Channel Calibration.• Full Host Control of the DDR2 DRAMs.• Over-Temperature Detection and Alert.• Hot Add-on and Hot Remove Capability.• MBIST and IBIST Test Functions.• Transparent Mode for DRAM Test Support.• Low profile: 133.35mm x 30.35 mm• 240 Pin gold plated card connector with 1.00mm contactcenters (JEDEC standard pending).• Based on JEDEC standard reference card designs (Jedecstandard pending).• SPD (Serial Presence Detect) with 256 Byte serialE 2 PROM.Performance:• RoHS Compliant Products 1) TABLE 1Performance for DDR2–533Product Type Speed Code –3.7 UnitSpeed Grade PC2–4200 4–4–4 —max. Clock Frequency @CL5 f CK5 266 MHz@CL4 f CK4 266 MHz@CL3 f CK3 200 MHzmin. RAS-CAS-Delay t RCD 15 nsmin. Row Precharge Time t RP 15 nsmin. Row Active Time t RAS 45 nsmin. Row Cycle Time t RC 60 ns1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as definedin the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.Rev. 1.2, 2006-12 303292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules1.2 DescriptionThis document describes the electrical and mechanicalfeatures of Qimonda’s 240-pin, PC2-4200F ECC type, FullyBuffered Double-Data-Rate Two Synchronous DRAM DualIn-Line Memory Modules (DDR2 SDRAM FB-DIMMs). FullyBuffered DIMMs use commodity DRAMs isolated from thememory channel behind a buffer on the DIMM. They areintended for use as main memory when installed in systemssuch as servers and workstations. PC2-4200 refers to theDIMM naming convention indicating the DDR2 SDRAMsrunning at 266 MHz clock speed and offering 4200 MB/s peakbandwidth. FB-DIMM features a novel architecture includingthe Advanced Memory Buffer. This single chip component,located in the center of each DIMM, acts as a repeater andbuffer for all signals and commands which are exchangedbetween the host controller and the DDR2 SDRAMs includingdata in- and output. The AMB communicates with the hostcontroller and / or the adjacent DIMMs on a system boardusing an Industry Standard High-Speed Differential Point-to-Point Link Interface at 1.5 V.The Advanced Memory Buffer also allows buffering ofmemory traffic to support large memory capacities. Allmemory control for the DRAM resides in the host, includingmemory request initiation, timing, refresh, scrubbing, sparing,configuration access, and power management. TheAdvanced Memory Buffer interface is responsible for handlingchannel and memory requests to and from the local DIMMand for forwarding requests to other DIMMs on the memorychannel. Fully Buffered DIMM provides a high memorybandwidth, large capacity channel solution that has a narrowhost interface. The maximum memory capacity is 288 DDR2SDRAM devices per channel or 8 DIMMs.Product Type 1)Compliance Code 2)TABLE 2Ordering Information (Pb-free components and assembly)DescriptionSDRAM TechnologyPC2-4200F (DDR2-533):HYS72T512022HFD–3.7–A 4GB 2R×4 PC2-4200F–444–11–D 2 Ranks, FB–DIMM 2Gbit (×4)1) All product types end with a place code, designating the silicon die revision. Example: HYS 72T64000HFA-3.7-A, indicating Rev. A diceare used for DDR2 SDRAM components. To learn more on QIMONDA DDR2 module and component nomenclature see section 8 of thisdatasheet.2) The Compliance Code is printed on the module label and describes the speed grade, e.g. “PC2-4200F-444-11-A”, where 4200F meansFully Buffered DIMM with 4.26 GB/sec. Module Bandwidth and “444-11” means CAS latency = 4, t rcd latency = 4 and t rp latency = 4 usingJEDEC SPD Revision 1.1 and assembled on Raw Card “A”.DIMMDensityModuleOrganizationMemoryRanksECC/Non-ECC# ofSDRAMsTABLE 3Address Format# of row/bank/columns bits RawCard4GB 512M ×72 2 ECC 18 13/2/11 DProduct Type DRAM components 1)TABLE 4Components on ModulesDRAM Density DRAM Organisation Note 2)HYS72T512022HF HYB18T2G402AF 2 Gbit 512M ×41) Green Product2) For a detailed description of all functionalities of the DRAM components on these modules see the component datasheet.Rev. 1.2, 2006-12 403292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules2 Pin ConfigurationThe pin configuration of the DDR2 SDRAM DIMM is listed by function in Table 5 (240 pins). The abbreviations used in columnsPin and Buffer Type are explained in Table 6 and Table 7 respectively. The pin numbering is depicted in Figure 1.Pin# Name PinTypeBufferTypeFunctionTABLE 5Pin Configuration of FB-DIMMClock Signals228 SCK I HSDL_15 System Clock Input, positive line229 SCK I HSDL_15 System Clock Input, negative lineControl Signals17 RESET I LV-CMOS AMB reset signalNorthbound22 PN0 O HSDL_15 Primary Northbound Data, positive lines25 PN1 O HSDL_1528 PN2 O HSDL_1531 PN3 O HSDL_1534 PN4 O HSDL_1537 PN5 O HSDL_1551 PN6 O HSDL_1554 PN7 O HSDL_1557 PN8 O HSDL_1560 PN9 O HSDL_1563 PN10 O HSDL_1566 PN11 O HSDL_1548 PN12 O HSDL_1540 PN13 O HSDL_1523 PN0 O HSDL_1526 PN1 O HSDL_1529 PN2 O HSDL_1532 PN3 O HSDL_1535 PN4 O HSDL_1538 PN5 O HSDL_1552 PN6 O HSDL_1555 PN7 O HSDL_1558 PN8 O HSDL_1561 PN9 O HSDL_1564 PN10 O HSDL_15Rev. 1.2, 2006-12 503292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesPin# Name PinTypeBufferTypeFunction67 PN11 O HSDL_1549 PN12 O HSDL_1541 PN13 O HSDL_15142 SN0 I HSDL_15 Secondary Northbound Data, positive145 SN1 I HSDL_15 lines148 SN2 I HSDL_15151 SN3 I HSDL_15154 SN4 I HSDL_15157 SN5 I HSDL_15171 SN6 I HSDL_15174 SN7 I HSDL_15177 SN8 I HSDL_15180 SN9 I HSDL_15183 SN10 I HSDL_15186 SN11 I HSDL_15168 SN12 I HSDL_15160 SN13 I HSDL_15143 SN0 I HSDL_15146 SN1 I HSDL_15149 SN2 I HSDL_15152 SN3 I HSDL_15155 SN4 I HSDL_15158 SN5 I HSDL_15172 SN6 I HSDL_15175 SN7 I HSDL_15178 SN8 I HSDL_15181 SN9 I HSDL_15184 SN10 I HSDL_15187 SN11 I HSDL_15169 SN12 I HSDL_15161 SN13 I HSDL_15Southbound70 PS0 I HSDL_15 Primary Southbound Data, positive lines73 PS1 I HSDL_1576 PS2 I HSDL_1579 PS3 I HSDL_1582 PS4 I HSDL_1593 PS5 I HSDL_1596 PS6 I HSDL_1599 PS7 I HSDL_15Rev. 1.2, 2006-12 603292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesPin# Name PinTypeBufferTypeFunction102 PS8 I HSDL_1590 PS9 I HSDL_1571 PS0 I HSDL_15 Primary Southbound Data, negative lines74 PS1 I HSDL_1577 PS2 I HSDL_1580 PS3 I HSDL_1583 PS4 I HSDL_1594 PS5 I HSDL_1597 PS6 I HSDL_15100 PS7 I HSDL_15103 PS8 I HSDL_1591 PS9 I HSDL_15190 SS0 O HSDL_15 Secondary Southbound data, positive193 SS1 O HSDL_15 lines196 SS2 O HSDL_15199 SS3 O HSDL_15202 SS4 O HSDL_15213 SS5 O HSDL_15216 SS6 O HSDL_15219 SS7 O HSDL_15222 SS8 O HSDL_15210 SS9 O HSDL_15191 SS0 O HSDL_15 Secondary Southbound data, negative194 SS1 O HSDL_15 lines197 SS2 O HSDL_15200 SS3 O HSDL_15203 SS4 O HSDL_15214 SS5 O HSDL_15217 SS6 O HSDL_15220 SS7 O HSDL_15223 SS8 O HSDL_15211 SS9 O HSDL_15EEPROM120 SCL I CMOS Serial Bus Clock119 SDA I/O OD Serial Bus Data239 SA0 I CMOS Serial Address Select Bus 2:0240 SA1 I CMOS118 SA2 I CMOSRev. 1.2, 2006-12 703292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesPin# Name PinTypePower Supplies238 V DDSPD PWR – EEPROM Power Supply9,10,12,13,129,130,132,133 V CC PWR – AMB Core Power / Channel InterfacePower15,117,135,237 V TT PWR – Address/Command/Clock TerminationPower1,2,3,5,6,7,108,109,111,112,113,115,116,121,122,123,125,126,127,231,232,233,235,236V DD PWR – Power Supply4,8,11,14,18,21,24,27,30,33,36,39,42,43,46,47,50,53,56,59,62,65,68,69,72,75,78,81,84,85,88,89,92,95,98,101,104,107,110,114,124,128,131,134,138,141,144,147,150,153,156,159,162,163,166,167,170,173,176,179,182,185,188,189,192,195,198,201,204,205,208,209,212,215,218,221,224,227,230,234BufferTypeFunctionV SS GND – Ground PlaneOther Pins19,20,44,45,86,87,105,106,139, RFU NC – Not connected140,164,165,206,207,225,226136 VID0 – – Voltage ID16 VID1 – –137 Test AI – VREFRev. 1.2, 2006-12 803292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesAbbreviationHSDL_15LV-CMOSCMOSODDescriptionHigh-Speed Differential Point-to-Point Link Interface at 1.5 VLow Voltage CMOSCMOS LevelsTABLE 6Abbreviations for Buffer TypeOpen Drain. The corresponding pin has 2 operational states, active low and tristate,and allows multiple devices to share as a wire-OR.AbbreviationIOI/OAIPWRGNDNUNCDescriptionStandard input-only pin. Digital levels.Output. Digital levels.I/O is a bidirectional input/output signal.Input. Analog levels.PowerGroundNot UsableNot ConnectedTABLE 7Abbreviations for Pin TypeRev. 1.2, 2006-12 903292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesFIGURE 1Pin Configuration for FB-DIMM (240 pin) Rev. 1.2, 2006-12 1003292006-8F49-X9WC

Internet Data Sheet3 Basic FunctionalityHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesThe Advanced Memory Buffer (AMB) reference design complies with the FB-DIMM Architecture and Protocol Specification.3.1 Advanced Memory Buffer FunctionalityThe Advanced Memory Buffer will perform the following FB-DIMM channel functions:• Supports channel initialization procedures as defined inthe initialization chapter of the FB-DIMM Architecture andProtocol Specification to align the clocks and the frameboundaries, verify channel connectivity, and identify AMBDIMM position.• Supports the forwarding of southbound and northboundframes, servicing requests directed to a specific AMB orDIMM, as defined in the protocol chapter, and merging thereturn data into the northbound frames.• If the AMB resides on the last DIMM in the channel, theAMB initializes northbound frames.• Detects errors on the channel and reports them to the hostmemory controller.• Support the FB-DIMM configuration register set as definedin the register chapters.• Acts as DRAM memory buffer for all read, write, andconfiguration accesses addressed to the DIMM.• Provides a read buffer FIFO and a write buffer FIFO.• Supports an SMBus protocol interface for access to theAMB configuration registers.• Provides logic to support MEMBIST and IBIST Design forTest functions.• Provides a register interface for the thermal sensor andstatus indicator.• Functions as a repeater to extend the maximum length ofFB-DIMM Links.Transparent Mode for DRAM Test SupportIn this mode, the Advanced Memory Buffer will provide lowerspeed tester access to DRAM pins through the FB-DIMM I/Opins. This allows the tester to send an arbitrary test pattern tothe DRAMs. Transparent mode only supports a maximumDRAM frequency equivalent to DDR2 400. Transparent modefunctionality:• Reconfigures FB-DIMM inputs from differential high speedlink receivers to two single ended lower speed receivers(~200 MHz)• These inputs directly control DDR2 Command/Addressand input data that is replicated to all DRAMs• Uses low speed direct drive FB-DIMM outputs to bypasshigh speed Parallel/Serial circuitry and provide test resultsback to testerDDR2 SDRAM Interface• Supports DDR2 at speeds of 533MT/s• Supports 256Mb, 512Mb and 1Gb devices in x4 and x8configurations• 72-bit DDR2 SDRAM memory arrayRev. 1.2, 2006-12 1103292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules3.2 InterfacesFigure 2 illustrates the Advanced Memory Buffer and all of itsinterfaces. They consist of two FB-DIMM links, one DDR2channel and an SMBus interface. Each FB-DIMM linkconnects the Advanced Memory Buffer to a host memorycontroller or an adjacent FB-DIMM. The DDR2 channelsupports direct connection to the DDR2 SDRAMs on a FullyBuffered DIMM.FIGURE 2Block Diagram Advanced Memory Buffer InterfaceInterface TopologyThe FB-DIMM channel uses a daisy-chain topology to provideexpansion from a single DIMM per channel to up to 8 DIMMsper channel. The host sends data on the southbound link tothe first DIMM where it is received and redriven to the secondDIMM. On the southbound data path each DIMM receives thedata and again re-drives the data to the next DIMM until thelast DIMM receives the data. The last DIMM in the chaininitiates the transmission of data in the direction of the host(a.k.a. northbound). On the northbound data path each DIMMreceives the data and re-drives the data to the next DIMMuntil the host is reached.Rev. 1.2, 2006-12 1203292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesFIGURE 3Block Diagram of Channel Southbound and Northbound Paths3.3 High-Speed Differential Point-to-Point Link (at 1.5 V)InterfacesThe Advanced Memory Buffer supports one FB-DIMMChannel consisting of two bidirectional link interfaces usinghighspeed differential point-to-point electrical signaling. Thesouthbound input link is 10 lanes wide and carries commandsand write data from the host memory controller or theadjacent DIMM in the host direction. The southbound outputlink forwards this same data to the next FB-DIMM. Thenorthbound input link is 14 lanes wide and carries read returndata or status information from the next FB-DIMM in the chainback towards the host. The northbound output link forwardsthis information back towards the host and multiplexes in anyread return data or status information that is generatedinternally. Data and commands sent to the DRAMs travelsouthbound on 10 primary differential signal line pairs. Datareceived from the DRAMs and status information travelnorthbound on 14 primary differential pairs. Data andcommands sent to the adjacent DIMM upstream are repeatedand travel further southbound on 10 secondary differentialpairs. Data and status information received from the adjacentDIMM upstream travel further northbound on 14 secondarydifferential pairs.3.3.1 DDR2 ChannelThe DDR2 channel on the Advanced Memory Buffer supportsdirect connection to DDR2 SDRAMs. The DDR2 channelsupports two ranks of eight banks with 16 row/columnrequest, 64 data, and eight check-bit signals. There are twocopies of address and command signals to support DIMMrouting and electrical requirements. Four transfer bursts aredriven on the data and check-bit lines at 800 MHz.Propagation delays between read data/check-bit strobe laneson a given channel can differ. Each strobe can be calibratedby hardware state machines using write/read trial and error.Rev. 1.2, 2006-12 1303292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesHardware aligns the read data and check-bits to a single coreclock. The Advanced Memory Buffer provides four copies ofthe command clock phase references (CLK[3:0]) and writedata/check-bit strobes (DQSs) for each DRAM nibble.3.3.2 SMBus Slave InterfaceThe Advanced Memory Buffer supports an SMBus interfaceto allow system access to configuration registers independentof the FB-DIMM link. The Advanced Memory Buffer will neverbe a master on the SMBus, only a slave. Serial SMBus datatransfer is supported at 100 kHz. SMBus access to theAdvanced Memory Buffer may be a requirement to boot andto set link strength, frequency and other parameters neededto insure robust configurations. It is also required fordiagnostic support when the link is down. The SMBusaddress straps located on the DIMM connector are used bythe unique ID.3.3.3 Channel LatencyFB-DIMM channel latency is measured from the time a readrequest is driven on the FB-DIMM channel pins to the timewhen the first 16 bytes (2nd chunk) of read completion data issampled by the memory controller. When not using theVariable Read Latency capability, the latency for a specificDIMM on a channel is always equal to the latency for anyother DIMM on that channel. However, the latency for eachDIMM in a specific configuration with some number of DIMMsinstalled may not be equal to the latency for each FB-DIMMin a configuration with some different number of DIMMsinstalled. As more DIMMs are added to the channel,additional latency is required to read from each DIMM on thechannel. Because the channel is based on the point-to-pointinterconnection of buffer components between DIMMs,memory requests are required to travel through N-1 buffersbefore reaching the Nth buffer. The result is that a 4 DIMMchannel configuration will have greater idle read latencycompared to a 1 DIMM channel configuration. The VariableRead Latency capability can be used to reduce latency forDIMMs closer to the host. The idle latencies listed in thissection are representative of what might be achieved intypical AMB designs. Actual implementations with latenciesless than the values listed will have higher applicationperformance and vice versa.3.3.4 Peak Theoretical Channel ThroughputAn FB-DIMM channel transfers read completion data on theNorthbound data connection. 144 bits of data are transferredfor every Northbound data frame. This matches the 18-bytedata transfer of an ECC DDR DRAM in a single DRAMcommand clock. A DRAM burst of 8 from a single channel ora DRAM burst of four from two lock stepped channelsprovides a total of 72 bytes of data (64 bytes plus 8 bytesECC). The FB-DIMM frame rate matches the DRAMcommand clock because of the fixed 6:1 ratio of the FB-DIMMchannel clock to the DRAM command clock. Therefore, theNorthbound data connection will exhibit the same peaktheoretical throughput as a single DRAM channel. Forexample, when using DDR2 533 DRAMs, the peak theoreticalbandwidth of the Northbound data connection is 4.267GB/sec. Write data is transferred on the Southboundcommand and data connection, via Command+Wdataframes. 72 bits of data are transferred for everyCommand+Wdata frame. Two Command+Wdata framesmatch the 18-byte data transfer of an ECC DDR DRAM in asingle DRAM command clock. A DRAM burst of 8 transfersfrom a single channel, or a burst of 4 from two lock-stepchannels provides a total of 72 bytes of data (64 bytes plus 8bytes ECC). When the frame rate matches the DRAMcommand clock, the Southbound command and dataconnection will exhibit one half the peak theoreticalthroughput of a single DRAM channel. For example, whenusing DDR2 533 DRAMs, the peak theoretical bandwidth ofthe Southbound command and data connection is 2.133GB/sec. The total peak theoretical throughput for a single FB-DIMM channel is defined as the sum of the peak theoreticalthroughput of the Northbound data connection and theSouthbound command and data connection. When the framerate matches the DRAM command clock, this is equal to 1.5times the peak theoretical throughput of a single DRAMchannel. For example, when using DDR2 533 DRAMs, thepeak theoretical throughput of a single DDR2-533 channelwould be 4.267 GB/sec., while the peak theoreticalthroughput of the entire FB-DIMM PC4200F channel wouldbe 6.4GB/sec.Rev. 1.2, 2006-12 1403292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules3.4 Hot-addThe FB-DIMM channel does not provide a mechanism toautomatically detect and report the addition of a new DIMMsouth of the currently active last DIMM. It is assumed thesystem will be notified through some means of the addition ofone or more new DIMMs so that specific commands can besent to the host controller to initialize the newly addedDIMM(s) and perform a Hot-Add Reset to bring them into thechannel timing domain. It should be noted that the power tothe DIMM socket must be removed before a “hot-add” DIMMis inserted or removed. Applying or removing the power to aDIMM socket is a system platform function.3.5 Hot-removeIn order to accomplish removal of DIMMs the host mustperform a Fast Reset sequence targeted at the last DIMM thatwill be retained on the channel. The Fast Reset re-establishthe appropriate last DIMM so that the Southbound Tx outputsof the last active DIMM and the Southbound and Northboundoutputs of the DIMMs beyond the last active DIMM aredisabled. Once the appropriate outputs are disabled thesystem can coordinate the procedure to remove power inpreparation for physical removal of the DIMM if needed. Itshould be noted that the power to the DIMM socket must beremoved before a “hot-add” DIMM is inserted or removed.Applying or removing the power to a DIMM socket is a systemplatform function.3.6 Hot-replaceHot replace of DIMM is accomplished through combining the Hot-Remove and Hot-Add process.Rev. 1.2, 2006-12 1503292006-8F49-X9WC

Internet Data Sheet4 Electrical CharacteristicsHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules4.1 Operating ConditionsTABLE 8Absolute Maximum RatingsSymbol Parameter Rating Unit NoteMin. Max.V DD Voltage on V DD pin relative to V SS –0.5 +2.3 V1)V CC Voltage on V CC pin relative to V SS –0,3 1.75 VV DDQ Voltage on V DDQ pin relative to V SS –0.5 +2.3 V1)2)V DDL Voltage on V DDL pin relative to V SS –0.5 +2.3 V1)2)V IN , V OUT Voltage on any pin relative to V SS –0.3 +1.75 V1)T STG Storage Temperature –55 +100 °C1)2)V TT Voltage on V TT pin relative to V SS –0.5 2.3 V1) When V DD and V DDQ and V DDL are less than 500 mV; V REF may be equal to or less than 300 mV.2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage tothe device. This is a stress rating only and functional operation of the device at these or any otherconditions above those indicated in the operational sections of this specification is not implied. Exposureto absolute maximum rating conditions for extended periods may affect reliability.TABLE 9Operating Temperature RangeSymbol Parameter Values Unit NoteMin.Max.T CASE DRAM Component Case Temperature Range 0 +95 °C1)2)3)T CASE AMB Component Case Temperature Range 0 +110 °C1)1) Within the DRAM Component Case Temperature range all DRAM specification will be supported.2) Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C casetemperature before initiating self-refresh operation.3) Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.Rev. 1.2, 2006-12 1603292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesTABLE 10Supply Voltage Levels and DC Operating ConditionsParameter Symbol Limit Values Unit NoteMin. Nom. Max.AMB Supply Voltage V CC 1.455 1.5 1.575 VDRAM Supply Voltage V DD 1.7 1.8 1.9 VTermination Voltage V TT 0.48 × V DD 0.50 × V DD 0.52 × V DD VEEPROM Supply Voltage V DDSPD 3.0 3.3 3.6 VDC Input Logic High(SPD) V IH(DC) 2.1 — V DDSPD VDC Input Logic Low(SPD) V IL(DC) — — 0.8 VDC Input Logic High(RESET) V IH(DC) 1.0 — — VDC Input Logic Low(RESET) V IL(DC) — — +0.5 VLeakage Current (RESET) I L –90 — +90 µΑ2)Leakage Current (Link) I L –5 — +5 µΑ3)1) applies for SMB and SPD Bus Signals2) applies for AMB CMOS Signal RESET3) for all other AMB related DC parameters, please refer to the High Speed Differential Link Interface Specifications1)1)2)1)TABLE 11Timing ParametersParameter Symbol Min. Typ. Max. Units NoteEI Assertion Pass-Thru Timing t EI Propagate t — — 4 clksEI Deassertion Pass-Thru Timing t EID — — Bitlock clks1)EI Assertion Duration t EI 100 — — clks1)2)FBD Cmd to DDR Clk out that latches Cmd — — 8.1 — ns3)FBD Cmd to DDR Write — — TBD — nsDDR Read to FBD (last DIMM) — — 5.0 — ns4)Resample Pass-Thru time — — 1.075 — nsResynchPass-Thru time — — 2.075 — nsBit Lock Interval t BitLock — — 119 frames1)Frame Lock Interval t FrameLock — — 154 frames1)1) Defined in FB-DIMM Architecture and Protocol Spec2) Clocks defined as core clocks = 2x SCK input3) @ DDR2-667 - measured from beginning of frame at southbound input to DDR clock output that latches the first command of a frame tothe DRAMs4) @ DDR2-667 - measured from latest DQS input to AMB to start of matching data frame at northbound FB-DIMM outputsRev. 1.2, 2006-12 1703292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesTABLE 12Environmental ParametersParameter Symbol Rating Units NoteOperating Temperature T OPR See Note —Operating Humidity (relative) H OPR 10 to 90 %Storage Temperature T STG -50 to +100 °CStorage Humidity (without condensation) H STG 5 to 95 %Barometric pressure (operating) P BAR 3050 mBarometric pressure (storage) P BAR 14240 m1) The designer must meet the case temperature specifications for individual module components.2) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and the device funcionaloperation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods mayaffect reliability.1)2)2)2)2)2)Rev. 1.2, 2006-12 1803292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules5 Current Spec. and ConditionsThe following table provides an overview of the measurement conditions.TABLE 13I DD Measurement ConditionsParameterIdle Current, single or last DIMML0 state, idle (0 BW)Primary channel enabled, Secondary channel disabledCKE high. Command and address lines stable.DRAM clock activeIdle Current, first DIMML0 state, idle (0 BW)Primary and Secondary channels enabled.CKE high. Command and address lines stable.DRAM clock activeActive PowerL0 state50% DRAM BW, 67% read, 33% write.Primary and Secondary channels enabled.DRAM clock active, CKE high.Active Power, data pass throughL0 state50% DRAM BW to downstream DIMM, 67% read, 33% write.Primary and Secondary channels enabled.CKE high. Command and address lines stable.DRAM clock active.TrainingPrimary and Secondary channels enabled.100% toggle on all channels lanes.DRAMs idle (0 BW).CKE high. Command and address lines stable.DRAM clock active.IBISTOver all IBIST modesDRAM Idle (0 BW)Primary channel EnabledSecondary channel EnabledCKE high. Command and Address lines stableDRAM clock activeSymbolI CC_Idle_0I DD_Idle_0I CC_Idle_1I DD_Idle_1I CC_Active_1I DD_Active_1I CC_Active_2I DD_Active_2I CC_TrainingI DD_TrainingI CC_IBISTI DD_IBISTRev. 1.2, 2006-12 1903292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesParameterMemBISTOver all MemBIST modes >50% DRAM BW (as dictated by the AMB)Primary channel EnabledSecondary channel EnabledCKE high. Command and Address lines stableDRAM clock activeElectrical IdleDRAM Idle (0 BW)Primary channel DisabledSecondary channel DisabledCKE low. Command and Address lines FloatedDRAM clock active, ODT and CKE driven lowSymbolI CC_MEMBISTI DD_MEMBISTI CC_EII DD_EINotes1. Primary channel Drive strength at 100 % with De-emphasis at -6.5 dB2. Secondary channel drive strength at 60 % with De-emphasis at -3 dB when enabled.3. Address and Data fields provide a 50 % toggle rate on DRAM data and link lanes.4. Burst Length = 4.5. 10 lanes southbound and 14 lanes northbound are enabled and active (12 lanes NB if non-ECC DIMM).6. Modeled with 27 Ω termination for command, address, and clocks, and 47 Ω termination for control.7. Termination is referenced to V TT =V DD /2.TABLE 14I CC /I DD Specification for PC2-4200FProduct Type HYS72T512022HFD-3.7-A Unit NoteSpeed GradePC2-4200FSymbolTyp.ICC_Idle_0 1.65 APCC_Idle_0 2.51 WIDD_Idle_0 2.1 APDD_Idle_0 3.7 WITOT_Idle_0 3.76 APTOT_Idle_0 6.22 WICC_Idle_1 2.49 APCC_Idle_1 3.75 WIDD_Idle_1 1.85 APDD_Idle_1 3.26 WITOT_Idle_1 4.35 APTOT_Idle_1 7.02 WICC_Active_1 2.61 APCC_Active_1 3.91 WIDD_Active_1 3.94 APDD_Active_1 6.89 WRev. 1.2, 2006-12 2003292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesProduct Type HYS72T512022HFD-3.7-A Unit NoteSpeed GradePC2-4200FSymbolTyp.ITOT_Active_1 6.56 APTOT_Active_1 10.81 WICC_Active_2 2.62 APCC_Active_2 3.94 WIDD_Active_2 1.86 APDD_Active_2 3.28 WITOT_Active_2 4.51 APTOT_Active_2 7.24 WICC_IBIST 2.88 APCC_IBIST 4.32 WIDD_IBIST 1.7 APDD_IBIST 3 WITOT_IBIST 4.61 APTOT_IBIST 7.34 WICC_Training 2.53 APCC_Training 3.81 WIDD_Trainig 1.7 APDD_Training 3 WITOT_Trainig 4.26 APTOT_Training 6.83 WICC_EI 1.69 APCC_EI 2.57 WIDD_EI 0.3 APDD_EI 0.53 WITOT_EI 2.15 APTOT_EI 3.23 WICC_MEMBIST 2.51 APCC_MEMBIST 3.77 WIDD_MEMBIST 4.2 APDD_MEMBIST 7.35 WITOT_MEMBIST 6.77 APTOT_MEMBIST 11.18 WRev. 1.2, 2006-12 2103292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules6 SPD CodesThis chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD standsfor serial presence detect. All values with XX in the table are module specific bytes which are defined during production.List of SPD Code Tables• Table 15 “PC2–4200F–444” on Page 22Product TypeOrganizationLabel CodeHYS72T512022HFD–3.7–A4 GByte×722 Ranks (×4)PC2–4200F–444TABLE 15PC2–4200F–444JEDEC SPD Revision Rev. 1.1Byte# Description HEX0 SPD Size CRC / Total / Used 921 SPD Revision 112 Key Byte / DRAM Device Type 093 Voltage Level of this Assembly 124 SDRAM Addressing 495 Module Physical Attributes 236 Module Type 077 Module Organization 108 Fine Timebase (FTB) Dividend and Divisor 009 Medium Timebase (MTB) Dividend 0110 Medium Timebase (MTB) Divisor 0411 t CK.MIN (min. SDRAM Cycle Time) 0F12 t CK.MAX (max. SDRAM Cycle Time) 2013 CAS Latencies Supported 3314 t CAS.MIN (min. CAS Latency Time) 3C15 Write Recovery Values Supported (WR) 3216 t WR.MIN (Write Recovery Time) 3C17 Write Latency Times Supported 7218 Additive Latency Times Supported 5019 t RCD.MIN (min. RAS# to CAS# Delay) 3C20 t RRD.MIN (min. Row Active to Row Active Delay) 1E21 t RP.MIN (min. Row Precharge Time) 3CRev. 1.2, 2006-12 2203292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesProduct TypeOrganizationHYS72T512022HFD–3.7–A4 GByte×722 Ranks (×4)Label CodePC2–4200F–444JEDEC SPD Revision Rev. 1.1Byte# Description HEX22 t RAS and t RC Extension 0023 t RAS.MIN (min. Active to Precharge Time) B424 t RC.MIN (min. Active to Active / Refresh Time) F025 t RFC.MIN LSB (min. Refresh Recovery Time Delay) FE26 t RFC.MIN MSB (min. Refresh Recovery Time Delay) 0127 t WTR.MIN (min. Internal Write to Read Cmd Delay) 1E28 t RTP.MIN (min. Internal Read to Precharge Cmd Delay) 1E29 Burst Lengths Supported 0330 Terminations Supported 0731 Drive Strength Supported 0132 t REFI (avg. SDRAM Refresh Period) C233 T CASE.MAX Delta / ∆T 4R4W Delta 5134 Psi(T-A) DRAM 6035 ∆T 0 (DT0) DRAM 3436 ∆T 2Q (DT2Q) DRAM 1D37 ∆T 2P (DT2P) DRAM 2338 ∆T 3N (DT3N) DRAM 1E39 ∆T 4R (DT4R) / ∆T 4R4W Sign (DT4R4W) DRAM 4340 ∆T 5B (DT5B) DRAM 2241 ∆T 7 (DT7) DRAM 2A42 - 78 Not used 0079 FBDIMM ODT Values 1280 Not used 0081 Channel Protocols Supported LSB 0282 Channel Protocols Supported MSB 0083 Back-to-Back Access Turnaround Time 0084 AMB Read Access Delay for DDR2-800 3685 AMB Read Access Delay for DDR2-667 3886 AMB Read Access Delay for DDR2-533 3687 Psi(T-A) AMB 2A88 ∆T Idle_0 (DT Idle_0) AMB 5489 ∆T Idle_1 (DT Idle_1) AMB 6790 ∆T Idle_2 (DT Idle_2) AMB 50Rev. 1.2, 2006-12 2303292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesProduct TypeOrganizationHYS72T512022HFD–3.7–A4 GByte×722 Ranks (×4)Label CodePC2–4200F–444JEDEC SPD Revision Rev. 1.1Byte# Description HEX91 ∆T Active_1 (DT Active_1) AMB 8D92 ∆T Active_2 (DT Active_2) AMB 7493 ∆T L0s (DT L0s) AMB 0094 - 97 Not used 0098 AMB Junction Temperature Maximum (T jmax ) 1F99 Category Byte 59100 Not used 00101 AMB Personality Bytes: Pre-initialization (1) 40102 AMB Personality Bytes: Pre-initialization (2) C0103 AMB Personality Bytes: Pre-initialization (3) 12104 AMB Personality Bytes: Pre-initialization (4) 44105 AMB Personality Bytes: Pre-initialization (5) 9C106 AMB Personality Bytes: Pre-initialization (6) 30107 AMB Personality Bytes: Post-initialization (1) 60108 AMB Personality Bytes: Post-initialization (2) 33109 AMB Personality Bytes: Post-initialization (3) 60110 AMB Personality Bytes: Post-initialization (4) 1B111 AMB Personality Bytes: Post-initialization (5) 60112 AMB Personality Bytes: Post-initialization (6) 1B113 AMB Personality Bytes: Post-initialization (7) 60114 AMB Personality Bytes: Post-initialization (8) 1B115 AMB Manufacturers JEDEC ID Code LSB 80116 AMB Manufacturers JEDEC ID Code MSB B3117 DIMM Manufacturers JEDEC ID Code LSB 85118 DIMM Manufacturers JEDEC ID Code MSB 51119 Module Manufacturing Location xx120 Module Manufacturing Date Year xx121 Module Manufacturing Date Week xx122 - Module Serial Numberxx125126 Cyclical Redundancy Code LSB 42127 Cyclical Redundancy Code MSB 88128 Module Product Type, Char #1 37Rev. 1.2, 2006-12 2403292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesProduct TypeOrganizationHYS72T512022HFD–3.7–A4 GByte×722 Ranks (×4)Label CodePC2–4200F–444JEDEC SPD Revision Rev. 1.1Byte# Description HEX129 Module Product Type, Char #2 32130 Module Product Type, Char #3 54131 Module Product Type, Char #4 35132 Module Product Type, Char #5 31133 Module Product Type, Char #6 32134 Module Product Type, Char #7 30135 Module Product Type, Char #8 32136 Module Product Type, Char #9 32137 Module Product Type, Char #10 48138 Module Product Type, Char #11 46139 Module Product Type, Char #12 44140 Module Product Type, Char #13 33141 Module Product Type, Char #14 2E142 Module Product Type, Char #15 37143 Module Product Type, Char #16 41144 Module Product Type, Char #17 20145 Module Product Type, Char #18 20146 Module Revision Code 6x147 Test Program Revision Code xx148 DRAM Manufacturers JEDEC ID Code LSB 85149 DRAM Manufacturers JEDEC ID Code MSB 51150 informal AMB content revision tag (MSB) 01151 informal AMB content revision tag (LSB) 05152 - Not used 00175176 -255Blank for customer useFFRev. 1.2, 2006-12 2503292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM Modules7 Package OutlineAll Components are surface mounted on one or both sides ofthe PCB and positioned on the PCB to meet the minimum andmaximum trace lengths required for DDR2 SDRAM signals.Bypass capacitors for DDR2 SDRAM devices are locatednear the device power pins. The AMB device in the center ofthe DIMM has a metal Heat Sink. The FB-DIMM mechanicaloutlines are consistent with JEDEC MO-256.JEDEC Raw Card Qimonda PCB DimensionsTABLE 16Raw Card ReferenceWidth [mm] Height [mm] Thickness [mm] NotesR/C D L-DIM-240-24 Figure 4 133.35 30.35 7.31) Thickness includes Qimonda Heat Sink. Some early production modules with Jedec Heatspreader may be thicker up to 8.2mm.1)Attention: Heat Sink heat up during operation. When unplugging a DIMM from a system direct skin contact should beavoided until the Heat Sink has reached room temperature.Attention: The Heat Sink is mechanically loaded. Do not remove. Removal of the clip may cause injuries.Attention: Any mechanical stress on the Heat Sink should be avoided. Touching the Heat Sink while plugging orunplugging the module may permanently damage the DIMM.Rev. 1.2, 2006-12 2603292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesFIGURE 4Package Outline L-DIM-240-24 Notes1. Please contact your sales or marketing representative formore details on package dimensions.2. Drawing according to ISO 80153. Dimensions in mm4. General tolerances +/- 0.15Rev. 1.2, 2006-12 2703292006-8F49-X9WC

Internet Data Sheet8 DDR2 NomenclatureHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesExample forField NumberTABLE 17Nomenclature Fields and Examples1 2 3 4 5 6 7 8 9 10 11Micro-DIMM HYS 64 T 64128 0 2 0 K M –5 –ADDR2 DRAM HYB 18 T 5121G 16 0 A C –5Field Description Values Coding1 QIMONDAHYSConstantModule Prefix2 Module Data Width [bit] 64 Non-ECC72 ECC3 DRAM Technology T DDR24 Memory Density per I/O [Mbit];32 256 MByteModule Density 1) 64 512 MByte128 1 GByte256 2 GByte512 4 GByte5 Raw Card Generation 0 .. 9 Look up table6 Number of Module Ranks 0, 2, 4 1, 2, 47 Product Variations 0 .. 9 Look up table8 Package,A .. ZLook up tableLead-Free Status9 Module Type D SO-DIMMMMicro-DIMMRRegisteredUUnbufferedFFully Buffered10 Speed Grade –2.5 PC2–6400 6–6–6–3 PC2–5300 4–4–4–3S PC2–5300 5–5–5–3.7 PC2–4200 4–4–4–5 PC2–3200 3–3–3TABLE 18DDR2 DIMM NomenclatureRev. 1.2, 2006-12 2803292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesField Description Values Coding11 Die Revision –A First–B Second1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overallmodule memory density in MBytes as listed in column “Coding”.Field Description Values Coding1 QIMONDAHYBConstantComponent Prefix2 Interface Voltage [V] 18 SSTL_183 DRAM Technology T DDR24 Component Density [Mbit] 256 256 Mbit512 512 Mbit1G1 Gbit2G2 Gbit5+6 Number of I/Os 40 ×480 ×816 ×167 Product Variations 0 .. 9 Look up table8 Die Revision A FirstBSecond9 Package,Lead-Free StatusCFBGA,lead-containingFBGA, lead-freeF10 Speed Grade –2.5 DDR2-800 6-6-6–3 DDR2-667 4-4-4–3S DDR2-667 5-5-5–3.7 DDR2-533 4-4-4–5 DDR2-400 3-3-3TABLE 19DDR2 DRAM NomenclatureRev. 1.2, 2006-12 2903292006-8F49-X9WC

Internet Data SheetHYS72T512022HFD–3.7–A240-Pin Fully-Buffered DDR2 SDRAM ModulesTable of Contents1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Basic Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.1 Advanced Memory Buffer Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123.3 High-Speed Differential Point-to-Point Link (at 1.5 V) Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.1 DDR2 Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.3.2 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3.3 Channel Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.3.4 Peak Theoretical Channel Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.4 Hot-add . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.5 Hot-remove . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.6 Hot-replace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Current Spec. and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 DDR2 Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30Rev. 1.2, 2006-12 3003292006-8F49-X9WC

Internet Data SheetEdition 2006-12Published by Qimonda AGGustav-Heinemann-Ring 212D-81739 München, Germany© Qimonda AG 2006.All Rights Reserved.Legal DisclaimerThe information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or anyinformation regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,including without limitation warranties of non-infringement of intellectual property rights of any third party.InformationFor further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question pleasecontact your nearest Qimonda Office.Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if afailure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affectthe safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the humanbody, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the healthof the user or other persons may be endangered.www.qimonda.com