Program Logic Manual - All about the IBM 1130 Computing System

SECTION 8. CORE LOAD BUILDERFLOWCHARTSPhase 1 (IN): CLBO1Phase 2 (MC): CLB02The Core Load Builder builds a specified mainlineprogram into an executable core load. The mainlineprogram, with its required subroutines (LOCALsand SOCALs included), is converted from disksystem format (DSF) to a format suitable for execution.During the conversion, the Core Load Builderalso builds the core image header record and thetransfer vector. The resulting core load is suitablefor immediate execution or for storing on the disk indisk core image format (DCI) for future execution.GENERAL COMMENTSEach phase of the Core Load Builder has beenbroken up into a series of relatively small, selfcontainedsubroutines. After initialization (phase 1)control remains in the Master Control subroutine,which is a part of phase 2. (The labels in this subroutineall start with "MC". ) In other words, thebasic control logic is found in the Master Controlsubroutine.The labels assigned to constants and work areaswithin subroutines are in the range 900-999. Whenevernoted, even-numbered labels are on evenboundaries, and odd-numbered labels are on oddboundaries. Constants and work areas in RCOM(phase 0) are mnemonic and are arranged in fourgroups, each ordered alphabetically. Double-wordcells are in one group, indexed cells are in a second;constants are in a third; and switches and work areasare in a fourth. The labels of switches are of theform "LSWx", where "x" is a number. The labelsof constants are of the form "Kx", where "x" iseither the number, in decimal, defined in the constantor the four hexadecimal digits defined in theconstant.Patch areas are usually found at the end of a phase.Each one is defined by a BSS followed by a DC.OVERLAY SCHEME AND CORE LAYOUTThe overlays (phases) of the Core Load Builder havebeen organized to allow maximum core storage forthe Load Table while minimizing the flip-flopping ofphases. "Minimizing" here means that, during aone-pass building process (no LOCALs or SOCALs),the phases are executed serially from 1 through 6(excluding 5). During a two-pass building process(LOCALs and/or SOCALs required), there is someflip-flopping of phases 3 and 5.Phase 0 is never overlaid. It contains the subroutinesthat must never be overlaid, as well aswork areas and constants required by more than onesubroutine.Phase 1 is fetched along with phase 0. The onlydifference is that phase 2 overlays phase 1 but not,of course, phase 0. Phases 3, 4, 5, 6, and 12 overlaythe last part of phase 2.Phases 7-10 contain messages. They all requirethat the principal print subroutine be in the databuffer; these phases themselves are executed fromthe LET/FLET search buffer.Phase 11 prints the file map and phase 12 the coremap. Both of these phases require that the principalprint device subroutine be in the LET/FLET searchbuffer. Phase 11 is executed from the data buffer.Figure 9, panel 1 shows the layout of the contentsof core storage after phases 0 and 1 of the Core LoadBuilder have been fetched into core storage by phase1 of the Core Image Loader or the STORE functionof DUP.Figure 9, panel 2 shows the layout of the contentsof core storage after phase 1 has fetched phase 2,overlaying itself. Phase 2 has allocated the areas forthe Load Table and the disk I/O buffers.Figure 9, panel 3 shows the layout of the contentsof core storage after any one of the overlay phaseshas been fetched by phase 2.Phase 1 includes the subroutines called by the initializationsubroutine. In this way, phase 2 can overlayphase 1 completely. Phase 2 includes the subroutinescalled by the relocation subroutine, RL. Theorder of the subroutines in this phase is important.Those that are required only during the relocation ofthe mainline (MV, ML, CK, DC, DF, and FM) comeSection S. Core Load Builder 33