Design Challenges in HBT MMIC Amplifier Bias Circuits

Design Challenges in HBT MMIC Amplifier Bias CircuitsJohn D BirkbeckConsultant Engineer – MMIC Design, RFIC Group – Wireless Business Unit,Roke Manor Research Limited, Roke Manor, Romsey, Hampshire, SO51 0ZN, UKDirect Telephone +44(0)1794 833143. Fax: +44(0)1794 833433Email: john.birkbeck@roke.co.uk Website: http://www.roke.co.ukABSTRACTDuring the development of a custom HBT MMIC,solutions will be evolved for the RF and DC circuits inparallel with the packaging and thermal design. Thetype of MMIC being developed will determine therelative difficulty these areas present. Following a briefintroduction to HBT MMICs, this paper focuses on theissues associated with the design of the DC bias circuit,which need to be correctly addressed if the fullperformance capability of the process is to be unlocked.Merits and disadvantages of basic and advanced biasschemes are discussed for circuits targeting Class Athrough to Class AB operation.INTRODUCTIONHetero-junction Bipolar Transistor (HBT) MonolithicMicrowave Integrated Circuit (MMIC) technology isfirmly established and has been serving the RF &Microwave industry for many years.Simplistically, the technology can be considered as ameans to integrate bipolar transistors, diodes, resistors,capacitors and inductors together on a single integratedcircuit. A typical MMIC is shown in Figure 1 below.Figure 1: A plastic packaged MMIC (lid removed),with support components, on an FR4 PCB.The high useful operating frequency (GHz) and highoperating current density (200µA/µm 2 ) features of thetechnology make it eminently suitable for realising avast range of different products from low powermultifunctional circuits through to power amplifiers.From a designer’s point of view, an important factwhich distinguishes GaAs HBTs from traditionalSilicon bipolar transistors, is that the ‘Vbe’ of thesedevices is somewhat higher at around 1.3V, and issubject to a negative temperature slope giving avariation of around ±0.1V over typical operatingtemperature ranges. Other than this, from an initialdesign perspective, HBTs can be thought of simply asvery fast, high performance bipolar transistors.Finally, it is worth noting here, that standard processesonly support NPN devices, which we will see is a majorlimitation in the scope of bias circuit design that ispossible.APPLICATION CHALLENGESAny HBT MMIC development requires consideration ofat least the following elements:• Circuit design• High frequency electrical circuit• DC electrical circuit• Thermal circuit (ie modelling effectsof device self heating)• Packaging and assembly design• Electrical performance• Thermal performanceDesign can be relatively straightforward for cases wherethere is good headroom on the supply rail, only modestRF powers are required, and the circuit is allowed tooperate largely as a Class A design. Here, the designareas listed above are relatively independent, and thedevelopment can generally be undertaken using asimple bias scheme, and basing the RF design onstandard foundry s-parameter data, which ifrepresentative should almost guarantee 1 st pass designsuccess.The other extreme is the case where there is minimalheadroom on the supply rail, and considerable RFpower is required from devices, necessitating operationnearer to Class B to achieve combined efficiency andlinearity targets. In this case, the RF, DC and thermalcircuits become highly interactive, and circuit designbecomes a potentially more iterative process as thedesign areas listed above become significantly moreinterdependent.One important means to limit this unwanted interaction,to enable design to be undertaken in a moredeterministic and less iterative manner, is by appropriatedevelopment of the DC base bias circuit topology.For the purposes of this discussion, we will say that themost demanding case we will consider is thedevelopment of a bias circuit for an HBT MMIC for usein a battery powered equipment such as a mobile phone,

equired to run from an unregulated DC supply in the 3-4V region. Also, we would like to consider designoptions for both low power Class A circuits through tohigh power Class AB circuits.Starting from the HBT shown in Figure 2 below, wewill develop basic base bias circuits, to highlight areaswhich present a particular design challenge. Means tomitigate these challenges will be proposed, and themerits and disadvantages discussed.This paper will conclude by showing how this designknowledge can be used to develop alternative highperformance bias circuits, by using one of the authorspatent pending designs as an example.collector current to vary, in turn causing poor RF andDC performance. Secondly, if the transistor was a large‘power’ device, the current required from the basesupply may be of the order of tens of milliamps, whichdoes not lend itself to connection to a low power SiliconIC control circuit as may be typically used. Finally, thissort of topology will not operate well as a so-called deepClass AB power amplifier, this class being required fora good efficiency/linearity trade off in a mobile phonetransmit power amplifier (more on this shortly).Two approaches could be considered here for reducingthe circuit’s sensitivity to process, temperature andsupply rail. The classic approach of the addition of anemitter degeneration resistor would yield a serviceabletopology for very low power operation, as would the useof a current mirror, which works very well in an ICenvironment. These approaches are shown in Figure 4and Figure 5 respectively.Base DCSupplyCollectorDC Supply(optional L)RFoutFigure 2: HBT Transistor to biasRFinBASIC BIAS CIRCUIT DESIGNThe addition of a few components to the transistor ofFigure 2, takes us to one of the simplest forms of biascircuit possible shown in Figure 3 below.Base DC Supply0V /3.0V(±0.1V)Base BiasResistor3-4VCollector DC SupplyCollectorBiasChokeRFoutFigure 4: Bias Stabilisation by emitter de-generationBase DC Supply Collector DC SupplyRFoutRFinDCBlockVbe = 1.3V ±0.1Vover temperatureDCBlockß = 50-100 overprocess &temperatureA=kR=rn(optional L)R=rA=knDCBlockFigure 3: A simple HBT bias circuitIn this case, the collector bias remains permanentlyconnected through the bias choke, and the circuit isactivated by a switched regulated DC voltage fed to thebase via a resistor, which also functions as an RF blockto some degree, additional series inductance beingadded to improve this if required. Leakage current inHBTs is very low, and so permanent collector biasworks for most battery powered applications. Whilstthe base current injected will remain fairly independentof temperature and the modest supply rail variationsshown, this circuit suffers from a number of problems.Beta variation with process and temperature causes theRFinFigure 5: Bias stabilisation by current mirrorHowever, we are interested in a developing a solutioncapable of use with power amplifiers too. So for thiscase, the next stage is to add DC buffering in the basebias feed. This is typically achieved by use of anemitter follower from the control line as shown inFigure 6. This improved circuit reduces the potentiallyhigh current demand from the regulated control line toan acceptable level by transferring most of the drain tothe unregulated supply.

This circuit however has a new disadvantage over theoriginal circuit of Figure 3, in that we have run out ofvoltage headroom on our control line and our circuit isnow critically sensitive to temperature and supply railvariation, since we are relying on generating a currentsource from a potential difference which may vary inthis example from 0.1V to 0.7V across the bias resistor.RFinBase DCSupply0V /3.0V(±0.1V)Vbe = 1.3V ±0.1V0.1 to 0.7V !!!DCBlockBaseBiasResistorVbe = 1.3V ±0.1VCollector DC Supply3-4VCollectorBiasChokeDCBlockRFoutß = 50-100 overprocess &temperatureFigure 6: HBT bias circuit with DC bufferA variation factor of the order of seven is unacceptable,and some temperature and power rail compensation isrequired. The addition of two diodes and a resistoryields the circuit of Figure 8. This circuit relies on goodthermal coupling such that the diode voltage tracks Vbechanges with temperature, clamping the base voltage atthe emitter follower, reducing the circuit’s sensitivity.Before we leave the circuit of Figure 6, anotherimportant advantage needs to be described. Theaddition of the emitter follower transistor means that wenow have a circuit which can be tailored to provide aClass AB mode of operation. Class AB amplifierdesign is a subject in itself, so only a basic description isnecessary here, to highlight features of a bias circuit thatare needed to address this requirement:An aside: Class AB operation basicsIn Class AB, the circuit is set up so that in the absenceof an RF signal, the main transistor is biased at somelow quiescent collector current, such that for low RFdrive levels it functions as a linear amplifier. As the RFdrive level increases, rectification causes the circuit toself-bias, and operation is more towards Class B. Thiscan be explained with reference to Figure 7 below.Base DCSupply3.0VEmitterFollowerVxCollector DC SupplyBiasResistorAmpFigure 7: Class AB operationOn the forward current half cycle, Vx tends to riseslightly as the RF current drives the base of the maintransistor. This clamps the base emitter voltage of theemitter follower, such that it does not supply current tothe main transistor. On the negative going half cycle,Vx drops, and the ‘return’ RF current is supplied fromthe emitter follower. The rectification which occursmeans the time averaged voltage at the base of the maintransistor is lower than when the RF signal was absent,and its collector current is higher. In this way the circuitoperates as a deep Class AB design, and can maintain amuch improved total battery efficiency over a widerange of operating powers, than could be achieved forClass A. It can readily be appreciated that the choice ofbias resistor will strongly influence the self biasingprofile achieved, and indeed there is an optimum valuefor this component for different modulation schemesand linearity requirements. In practice of course,additional challenges present themselves for goodoverall Class AB circuit design. However for thepurposes of this bias circuit discussion, the need toincorporate features to allow and tailor self biasing hasbeen explained.To summarise then, the circuit of Figure 6, has reducedcontrol current requirements, and an option for ClassAB operation.Base DCSupply0V /3.0V(±0.1V)RFinBaseBiasResistorCollector DC Supply3-4VDCBlockRFoutFigure 8: A circuit just suitable for providing deepClass AB bias for a ‘saturated’ modulation type PA.The circuit of Figure 8, with the previously describedcompensation diodes, is our first fully practical biascircuit, minor variants of which may be found forexample in deep Class AB GSM HBT power amplifiersMMICs selling in high volume.However, this circuit is not without its disadvantages.Whilst providing some thermal compensation, the biaspoint may still vary by as much as a factor of three overa typical temperature range of -25°C to +80°C. Thecontrol current is rather high again (up to 15mA in somecases), due to the need to waste a certain amount in thediode clamp. Next, whilst suitable for driving a poweramplifier in a Class AB mode for the case where asaturated modulation scheme is used, it is not suitablefor use with linear modulation schemes (CDMA etc),where unacceptable adjacent channel leakage wouldresult for adequately low quiescent currents. Finally,

limitations in device models and CAD software, meansthis sort of circuit is difficult to design for 1 st passsuccess, and iterations of many variants may be neededto find the one that gives the best trade off betweenperformance and yield. It is essential, for mobile phonepower amplifiers in particular to optimise every last bitof performance from the smallest die possible, sinceonly the very best components will sell successfully.From Figure 8, to take the next step in bias circuitdevelopment to achieve a circuit that works well withlinear modulation and lower control currents, takes us tothe area of advanced bias circuit design, where manypatent applications can be found. This level of IPgeneration highlights the importance of a good biascircuit - it really is a major key to unlocking theperformance of the target HBT process, for theapplication in hand.Reading through these works reveals a surprising rangeof clearly distinct methods used to tackle the problem.On one extreme, solutions exist that use relativelysimple circuits combining the three basic forms ofbiasing we have discussed (resistive based, currentmirror based & emitter follower based). The topologyis configured to access the benefits of each yielding acircuit that works well for high power linear modulationClass AB amplifiers. On the other extreme, solutionscan be found which are based on more complex circuitsusing multiple current mirrors or a control loopapproach. Whilst more complex in terms of the numberof components, these solutions are still adequatelycompact on-chip. Finally, to augment these schemes,modifications to the standard HBT process areoccasionally made. Such modifications include specialultra-compact low frequency transistors for the biascircuit, or changes to the metalisation arrangements forbetter thermal performance.Before such an advanced bias scheme is discussed, it isappropriate to summarise the key points of thediscussion so far:Why is proper design of the bias circuit topology soimportant?• To unlock the full performance potential of theHBT process• To improve the ‘designability’ of the circuit toreduce development costsWhat are the design issues?• Need to optimise the bias circuit interaction withthe RF signal• Need a power down function• May need high power / low power modes & linear /saturated modes• Need minimum current draw from regulated controllines.• Need good process, supply and temperaturetolerance• Need a compact on-chip implementationWhy are these issues difficult?• Some solutions require large on-chip componentssuch as inductors to maintain linearity, and soreduce the cost effectiveness of the design.• A switched 0/2.8V ‘enable’ control line is typicallyavailable. NPN devices only, means that it isdifficult to design a topology with a power downmode, with low control current draw in the on-state.• A bias circuit with different modes is difficult todesign without compromising some aspect ofperformance.• Emerging high performance processes offering a‘ß’ circa three times higher than conventional HBTwill mean suppliers using conventional technologyand simple bias circuits only could eventually beforced from the market.• High Vbe=1.3V, compared to supply rail typically3.0V makes useful circuits involving stackeddevices impossible.• High Vbe in combination with low Vcc and typicaltemperature coefficients, can lead to poor stabilityover temperature.ADVANCED BIAS CIRCUIT DESIGNThe previous section developed simple bias topologiesby sequentially adding components until the requiredfunctionality was achieved, and then adding furthercomponents to correct additional problems that arosealong the way.The understanding that this process has provided, assummarised in the bullet points above, is a necessaryprecursor to enable more advanced topologies as used inthe industry, to be designed.As an example, the development of one such bias circuitas undertaken by the author will now be discussed. Theaim was to generate a bias circuit that could beconfigured either for Class A operation or for deepClass AB operation and allow for ready modification toinclude additional features such as switched bias points.Also, and very importantly, to reduce the circuit’ssensitivity to process, temperature and supply railvariation not only in final hardware, but also at thedesign stage, such that the circuit could be simulatedusing existing CAD software and models with improvedcorrelation to measurement.As an R&D consultant to the MMIC industry,ownership of such a circuit by the RFICs Group at RokeManor Research Limited was clearly highly desirable.Figure 9 below contains the elements which wereasserted to be essential for the aims targeted. The mainRF transistor (bottom right) is permanently connectedvia the collector circuit to the supply rail which mayvary from 3.0V at the end of the batteries life up to 6.0Vwhen on-charge. An emitter follower is essential tominimise the current drawn from the regulated controlline, which is now shown as the more typical 0/2.8V. Asmall mirror transistor, in close thermal coupling to the

main transistor, provides accurate monitoring of thequiescent condition in the transistor. From this startpoint, additional circuitry is required to somehowconvert the low level ‘sensed’ current in the mirrortransistor into an ‘error’ current that can be used to pullthe emitter follower’s base node down, such that thecircuit reaches the desired equilibrium.Vctrl =2.8V ±0.1VVpdDropperResistorsEmitterFollowerVcc = 3.0V to 6.0VTR1CollectorCircuit &BaseFeedbackRFout+circuit which aside from the initial reference currentgeneration relies wholly on component ratios. Also, itwill be appreciated that the circuit offers good immunityto supply rail variation, since any such variation causesnear equal change in both sense and reference voltages.Vctrl =2.8V ±0.1VRxIref1IntermediateReferenceVoltageIntermediateSense VoltageIsense1RxMirrorTransistorVpdDropperResistorsEmitterFollowerMirrorTransistorActiveRFPowerCellCurrentSettingResistorIerrorFigure 11: Addition of a reference current generatorRFinFigure 9: Essential Elements for the exampleadvanced bias circuit discussionAs may be anticipated, the topology is beginning to looklike one of the “control circuit” types mentioned earlier,one missing element clearly being a reference signal ofsome sort. The desired control loop concept in this caseis summarised in Figure 10 below.The relative comparison and conversion to an errorsignal was the most difficult problem to overcome,although as often seems the case with circuit topologydevelopment, the solution actually appears quite simple.The function is achieved using a current mirror and onefurther transistor to provide a Vbe reference and DCamplification of the error. The loop is then closed, asshown in Figure 12 below.Vctrl =2.8V ±0.1VReferenceCurrentSenseCurrentMirrorTransistorVpdDropperResistorsEmitterFollowerThe final stage is to add a power down switch andadditional diode to block a leakage path. This completecircuit is shown in Figure 13 below. Despite theapparent large quantity of components, thisimplementation is very compact on chip, since most ofthe additional transistors are near to minimum size forprocess, and most of the resistors can be made verynarrow and short. Such resistors are more prone tomanufacturing spread, but since the circuit primarilydepends on ratios rather than absolute values, this canbe well tolerated.IerrorVctrl =2.8V ±0.1VVpdDropperResistorsFigure 10: Control Circuit ConceptA reference current generator can readily be designedusing another emitter follower as shown in Figure 11below. This sets up a reference current in the collector,determined by a single resistor in the emitter arm toground. The temperature coefficient of this resistor canoften be made equal and opposite to that of Vbe, suchthat the current produced is independent of temperatureand varies only with the regulation of the Vpd line.RxCurrentSettingResistorIntermediateReferenceVoltageIref1Isense2CurrentSubtractorRyx 1MirrorIntermediateSense VoltageRyIref2Isense1RxMirrorTransistorIref2-Isense2IerrorErrorAmplifierEmitterFollowerAddition of equal resistors in the collector arm of thistransistor, and the original mirror transistor, convertsthese sense and reference currents into voltages.Providing we can find a way to perform a relativecomparison between these levels, then we have a niceFigure 12: Addition of the differential currentcomparator and error amplifier.

Vctrl =2.8V ±0.1VCurrentSettingResistorRxIntermediateReferenceVoltageIref1Isense2CurrentSubtractorRyx 1MirrorIntermediateSense VoltageSwitchRyIref2Isense1MirrorTransistorIref2-Isense2RxVpdDropperResistorsIerrorErrorAmplifierVcc = 3.0V to 6.0V+TR1CollectorEmitter Circuit &Follower BaseFeedbackRFoutRFinActiveRFPowerCellSingle ModeBias Circuit forClass AB PAOn-chip Componentsshown. Minimum off-chipdecoupling caps alsorequiredFigure 13: Essentially complete circuit, providingbias for Class AB Power Amplification.All bias circuits tend to have some natural thermalslope, which causes a drift in quiescent bias level in onedirection with temperature. Generally, a positive slopeis desired to help achieve the same RF output power athigher temperature. The natural slope of this circuit isin the correct direction, and can actually be tailored asrequired. It was also found that parameters such asadjacent channel power ratio and 3 rd order intercept canbe optimised with minimal impact on other circuitparameters, which is an extremely useful feature.Finally to note that additional modifications are possibleto realise switched quiescent points, such as would berequired for a dual mode amplifier required to operatewith either linear or saturated modulation schemes.Altogether then, this circuit addressed and overcame allof the key issues, and with minimum additionalcapacitors off-chip can be made to work nicely as a biassolution for linear Class AB amplifiers.To remove the self biasing feature, a single capacitorcan be added across the base emitter junction of theemitter follower. This serves to make the emitterfollower a near open circuit to RF, and very linearamplification in Class A results.Overall this topology proved to be a great success, thefeatures and benefits being summarised as follows:• Configurability for deep Class AB through to ClassA. All configurations maximise RF performance,especially linearity.• Power down and other modes can be supported.• Ultra low current draw from control lines, typically80% lower than other industry solutions• Excellent process, supply and temperature tolerance– by design.• Excellent ‘designablility’ – single componentchanges largely affect one design parameter only.• Compact on-chip inductorless implementation• Inherently designed for high manufacturing yieldon any HBT process.• Excellent process transportabilitySUMMARYThe importance of good bias circuit design for HBTMMICs has been explained, and the key issues that needto be considered have been made clear, throughexamples of simple circuits. This basic knowledgeprimer is necessary for anyone wishing to design a moreadvanced topology.One such topology is the author’s patent pendingconfigurable bias circuit, and by way of example itsdevelopment has been described. This circuit wasshown to address the key issues raised, and can beconfigured for either Class A or deep Class AB. In allconfigurations the circuit offers very low process,temperature and supply rail sensitivity, giving improvedyield in final hardware, and improved ‘designablility’ atthe development stage, enabling 1 st pass design successfor challenging design specifications to be more readilyachieved, than would be possible with more primitivedesigns.REFERENCESThis paper refers to circuit and techniques as describedin the patent applications: GB0304053, GB0306405,PCT/GB03/01167, & PCT/GB03/01309.CAUTIONARY NOTEIt must be mentioned that anyone planning to release anHBT MMIC product, would be well advised to conducta thorough patent search in advance for aspects of thedesign, such as bias circuit topology.FURTHER INFORMATIONThe reader is invited to visit our website athttp://www.roke.co.uk for further information on HBTBias Circuits, and general MMIC and RF ASICactivities at Roke Manor. In particular, the followingdatasheets can be downloaded:• http://www.roke.co.uk/download/datasheets/hbt_mmic_design.pdf• http://www.roke.co.uk/download/datasheets/hbt_bias_circuit.pdf• http://www.roke.co.uk/download/datasheets/mmic_design_consultancy.pdfAlternatively please phone Technical Information on+44(0)1794 833000.© 01/10/03 - Roke Manor Research Ltd.