DDR4 DIMM Interposer - FuturePlus Systems

Accurate State AnalysisThe FS2501B DDR4 DIMM memory bus interposer brings bus signals to your Agilent logic analyzer viacontrolled impedance cables for an easy yprotocol analysis connection while maintaining signal fidelity.Accurate READ and WRITE State Capture at 2133DDR3 screen shots representing the DDR4 screen shots .The FS2501B protocol-decode softwaretranslates acquired signals into easilyunderstood bus transactions, at the full busspeed. The Agilent logic analyzer providesextensive triggering and store qualificationfeatures. Depending on the logic analyzer’sresources, the FS2501B interposer can beconfigured to perform State analysis of Reads orWrites, or both Reads and Writes, at 2133 MT/s.The DDR protocol decode software executes inthe logic analyzer and takes user input onsystem attributes such as Burst length, CAS andAdditive Latency, as well as Chip Selects todecode the key DDR bus signals and present adisplay that lists the transaction type, address,data and command conditions. The softwarealso supports user-defined symbols that can beeasily added to the state listing display. User-selectable post-processing filters allow theacquired data to display different types oftransactions indifferent colors.

Quick and Accurate SetupQuickly gain signal integrity insight with Agilent EyeScan technology. As timing and voltage marginscontinue to shrink, confidence in signal integrity becomes an increasingly vital requirement of thedesign verification process. EyeScan lets you quickly acquire comprehensive signal integrityinformation on the DDR4 bus in your design, and can provide measurements with 5 ps of resolution.DDR3 screen shots representing the DDR4 screen shots .

Demonstrated 2133 operationDDR4 READ Eyes from Eyescan Display on the FS2501B~200psRead eyes.U4154A requiresonly 100psDDR4 WRITE Eyes from Eyescan Display on the FS2501B~200psWrite eyes.U4154A requiresonly 100psDDR3 screen shots representing the DDR4 screen shots .

2133 State Capture VerifiedDDR4 READ operationDDR3 screen shots representing the DDR4 screen shots .State CaptureTiming CaptureDDR4 WRITE operationTiming CaptureState Capture

Ordering InformationFS2501B – DDR4 Interposer for use with Agilent Logic AnalyzersSoftware included with the FS2501B:Configuration files for the Agilent logic analyzerProtocol Decoder software, runs on the Agilent logic analyzerThe FS2501B requires- 1 ea M9502A two-slot AXIe chassis- 2 ea U4154A 136-channel Logic Analyzer ModulesAgilent Logic Analyzer RequirementsU4154AM9502AFuturePlus Systems CorporationP.O. Box 88155Colorado Springs, CO 80909-81558155Tel: 719 278 3540Fax: 719 278-9586Website: www.futureplus.comFuturePlus Systems does not assume any responsibility for use of any circuitry described, and reserves the right to change circuitry and specifications at any time without notice.FuturePlus® is a registered trademark of FuturePlus Systems Corporation.7/10/2012