Introduction to Digital Integrated Circuit Design Aims and Objectives ...

Routing a Standard Cell-based ICStandard Cell LibrariesUse a design kit from the IC vendorBuy an IC-vendor library from a library vendorBuild your own cell libraryRouting a CBIC (cell-based IC)• A “wall” of standard cells forms a flexible block• metal2 may be used in a feedthrough cell to cross over cell rows that usemetal1 for wiring• Other wiring cells: spacer cells, row-end cells, and power cellsIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 25Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 26Macrocell-Based DesignMacrocell-Based Design ExampleMacrocellInterconnect BusSRAMRouting ChannelSRAMRouting ChannelData pathsStandard cellsVideo-encoder chip[Brodersen92]Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 27Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 28

Gate-Array–Based ICsGate-Array–Based ICs (con’t)A gate array, masked gate array, MGA, or prediffused array usesmacros (books) to reduce turnaround time and comprises a basearray made from a base cell or primitive cell. There are three types:• Channeled gate arrays• Channelless gate arrays• Structured gate arraysA channelless gate array (channelfreegate array, sea-of-gates array,or SOG array)• Routing uses rows of unusedtransistorsA channeled gate array• The interconnect uses predefinedspaces between rows of base cellsAn embedded gate array orstructured gate array (mastersliceor masterimage)• Either channeled or channelless• Custom blocks (the same for eachdesign) can be embeddedIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 29Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 30Gate Array Approach - ExamplePrewired ArrayspolysiliconIn1 In2 In3 In4 Categories of prewired arrays (or field-programmabledevices):V DDGNDmetalpossiblecontact• Fuse-based (program-once)• Non-volatile EPROM basedOut• RAM basedUncommitedCellCommittedCell(4-input NOR)Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 31Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 32

Programmable Logic DevicesEPLD Block DiagramPrimary inputsMacrocellPLA PROM PALCourtesy Altera Corp.Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 33Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 34Field-Programmable Gate Arrays Fuse-basedInterconnectI/O BuffersProgrammed interconnectionInput/output pinProgram/Test/DiagnosticsVertical routesCellI/O BuffersI/O BuffersStandard-cell likefloorplanAntifuseHorizontaltracksRows of logic modulesRouting channelsI/O BuffersVertical tracksProgramming interconnect using anti-fusesIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 35Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 36

Field-Programmable Gate Arrays RAM-basedRAM-based FPGA Basic Cell (CLB)Combinational logicStorage elementsHorizontalroutingchannelCLBCLBswitching matrixInterconnect pointAB/Q1/Q2C/Q1/Q2DAB/Q1/Q2C/Q1/Q2DAny function of up t o4 variablesAny function of up to4 variablesRD inFGFGFGRD Q1CERD Q2CEGFCLBCLBEClockCEVertical routing channelCourtesy of XilinxIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 37Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 38OutlineDesign Abstraction LevelsHistorySYSTEMImplementation methodologiesDesign flow+MODULETechnology scalingGATEVLSI/IC economicsCIRCUITFuture trendsDEVICESn+GDn+Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 39Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 40

ASIC Design FlowASIC Design Flow (con’t)A design flow is a sequence of steps to design an ASIC• Design entry.• Logic synthesis.• Pre-layout simulation.• Floorplanning.• Placement.• Routing.• Extraction.• Postlayout simulation.Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 41Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 42OutlineMoore’s LawHistoryImplementation methodologiesDesign flowTechnology scalingVLSI/IC economics In 1965, Gordon Moore, co-founder of Intel, predicted the exponential growth of thenumber of transistors on an IC (number of transistors per square inch in ICs todouble every year) Predicted > 65,000 transistors by 1975! In subsequent years, the pace slowed down a bit, but density has doubledapproximately every 18 months, and this is the current definition of Moore's Law. Growth limited by power Most experts, including Moore himself, expectMoore's Law to hold for at least another twodecadesFuture trendsIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 43Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 44

Moore’s Law – Intel MicroprocessorsEvolution in ComplexitySource: IntelIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 45Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 46Why ?Scaling Why more transistors per IC?• Smaller transistors• Larger dice Why faster computers?• Smaller, faster transistors• Better microarchitecture• Fewer gate delays per cycle The only constant in VLSI/IC design is constant change Feature size shrinks by 30% every 2-3 years• Transistors become smaller, faster, less power hungry, cheaper tomanufacture• Noise, reliability issues1010• Current density goes up63• Wires do not improve1.5(and may get worse)S = 2• Typically• Technology nodes Scale factor SFeature Size (μm)10.11 0.80.60.350.250.180.130.091965 1970 1975 1980 1985 1990 1995 2000 2005YearIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 47Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 48

Scaling ImplicationsPerformance Improvement Improved Performance10,000 Improved Cost1,00040048008 Interconnect Woes Power WoesClock Speed (MHz)100108080808680286Intel386Intel486PentiumPentium Pro/II/III Productivity Challenges1Pentium 4 Physical Limits1970 1975 1980 1985 1990 1995 2000 2005YearIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 49Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 50Cost ImprovementInterconnect WoesIn 2003, $0.01 bought you 100,000 transistors SIA made a gloomy forecast in 1997• Delay would reach minimum at 250 – 180 nm, then get worsebecause of wires But…• Misleading scale• Global wires 100 kgate blocks okIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 51Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 52

Reachable RadiusDynamic PowerWe can’t send a signal across a large fast chip in one cycle anymoreBut the microarchitect can plan around this• Just as off-chip memory latencies were toleratedChip sizeScaling ofreachable radiusIntel VP Patrick Gelsinger(ISSCC 2001)• If scaling continues atpresent pace, by 2005,high speed processorswould have powerdensity of nuclearreactor, by 2010, arocket nozzle, and by2015, surface of sun.• “Business as usual willnot work in the future.”Intel stock dropped 8% onthe next dayBut attention to power isincreasingIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 53Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 54Static PowerProductivityV DD decreases• Save dynamic power• Protect thin gate oxides and short channels• No point in high value because of velocity sat.V t must decrease tomaintain device performanceBut this causes exponentialincrease in OFF leakageMajor future challenge Transistor count is increasing faster than designerproductivity (gates / week)• Bigger design teams Up to 500 for a high-end microprocessor• More expensive design cost• Pressure to raise productivity Rely on synthesis, IP blocks• Need for good engineering managersIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 55Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 56

Very Few Companies Can Design High-End ICsLess First Silicon Success and the Changing Rate of Failures10,0001,000Logic transistors per 100chip10(in millions) 10.10.010.001Design productivity gapIC capacityproductivity198119831985198719891991199319951997199920012003200520072009 Designer productivity growing at slower rate1981: 100 designer months ~$1M2002: 30,000 designer months ~$300MGap100,00010,0001000100 Productivity(K) Trans./Staff-Mo.1010.1Source: ITRS’990.01Trends are IncreasingLogic/FunctionalNoise / SIPow er ConsumptionClockingFast PathSlow PathAnalog TuningIR DropsYield / ReliabilityFirmw areMixed-SignalInterf aceOtherRET10%28%8%22%13%18%17%16%23%14%9%14%12%10%14%5%4%3%0%45%2003200162% First silicon success rates Betterdeclining• Functional Verification• First Silicon OK48%Noisein/2000SI• 39% Clocking200234% in 2003• IR Drops• Third Silicon OK Worse>90% in 2000• >70% Analog in Tuning 2002•>60%Mixed-Signalin 2003Interface• DFM (RET)Collett International Research:2000, 2002 Functional Verification Studies;2003 Design Closure Study, 01/04Trends are Decreasing0% 10% 20% 30% 40% 50% 60% 70%Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 57Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 58Physical LimitsOutlineWill Moore’s Law run out of steam?• Can’t build transistors smaller than an atom…Many reasons have been predicted for end of scaling• Dynamic power• Subthreshold leakage, tunneling• Short channel effects• Fabrication costs• Electromigration• Interconnect delayRumors of demise have been exaggeratedHistoryImplementation methodologiesDesign flowTechnology scalingVLSI/IC economicsFuture trendsIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 59Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 60

Selling price S total• S total = C total / (1-m) m = profit marginIntegrated Circuits Economics C total = total cost• Nonrecurring engineering cost (NRE)• Recurring cost• Fixed costNon-Recurring Engineering Costs (NRE) Engineering cost• Depends on size of design team• Include benefits, training, computers• CAD tools:Digital front end: $10KAnalog front end: $100KDigital back end: $1M Prototype manufacturing• Mask costs: $500k – 1M in 130 nm process• Test fixture and package toolingIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 61Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 62Recurring CostsFixed Cost Fabrication• Wafer cost / (Dice per wafer * Yield)• Wafer cost: $500 - $3000• Dice per wafer:2r 2rN = π ⎡⎢ −⎤• Yield: Y = e -ADA⎥⎣ 2A⎦For small A, Y ≈ 1, cost proportional to areaFor large A, Y → 0, cost increases exponentially Data sheets and application notes Marketing and advertising Yield analysis Packaging TestIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 63Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 64

New IC Design is Fairly Capital IntensiveCost BreakdownEstimated capital to start a company to design a wireless communication IC Digital designers (7):• $70k salary• $30k overhead• $10k computer• $10k CAD tools• Total: $120k * 7 = $840k Analog designers (3)• $100k salary• $30k overhead• $10k computer• $100k CAD tools• Total: $240k * 3 = $720k Support staff (5)• $45k salary• $20k overhead• $5k computer• Total: $70k * 5 = $350k Fabrication• Back-end tools: $1M• Masks: $1M• Total: $2M / year Summary• 2 years @ $3.91M / year• $8M design & prototypefabbackend tools25%25%salary26%11%9%4%overheadcomputerentry toolsIntroduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 65Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 66OutlineEvolution of Intel Microprocessors History Implementation methodologies Design flow Technology scaling VLSI/IC economics Future trendsIntel Intel Intel Intel Pentium IntelIntel Itanium 8080 4004 486Pentium 286III2IVTransistor Transistor Transistor Transistor count count count count = count = 3,200,000= 221,000,00028,000,000 7,500,000 1,200,000 = 6,000 2,300 = 134,000 42,000,0001971974 198219891993199719992000 2002Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 67Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 68

Intel Microprocessors SummarySilicon in 201010 4 increase in transistor count, clock frequency over 30 years!Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology:0.07 μmDensity Access Time(Gbits/cm2) (ns)DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5Density Max. Ave. Power Clock Rate(Mgates/cm2) (W/cm2) (GHz)Custom 25 54 3Std. Cell 10 27 1.5Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7FPGA 0.4 4.5 0.25Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 69Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 70ITRSSummarySemiconductor Industry Association forecast• Intl. Technology Roadmap for SemiconductorsIntegrated circuits are the faster growing technology the last 45 yearsDifferent implementation methodologies• Trade-off: design and turn around time vs design density and performanceAbstraction is the basis of design flows and toolsThe only constant in VLSI design is scaling• Moore’s Law and implicationsThe development of integrated circuits requires large investment 32nm in 2013, what next ?Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 71Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 72

Journals and ConferencesFurther ReadingIEEE Journal of Solid State CircuitsIEICE Transactions on Electronics (Japan)IEEE Transactions on VLSI SystemsOriginal article by MooreArticle on Moore’s LawInternational Solid-State and Circuits Conference (ISSCC)VLSI Circuits SymposiumCustom Integrated Circuits Conference (CICC)European Solid-State Circuits Conference (ESSCIRC)International ASIC ConferenceInternational Technology Roadmap for Semiconductors (2003 Edition,2004 Update)Assignment: Analysis of ITRS 2003 Edition (or 2004 update)Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 73Introduction & TrendsIntroduction to Digital Integrated Circuit DesignTopic 1 - 74