4-BIT MAGNITUDE COMPARATOR SN54/74LS85

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SN54/74LS85LOGIC DIAGRAMA3(15)B3(1)(5)OA>B(13)A2B2(14)(2)AB(12)A1B1(11)(6)OA=B(7)OAB IAB OAB3 X X X X X X H L LA3B2 X X X X X H L LA3=B3 A2B1 X X X X H L LA3=B3 A2=B2 A1B0 X X X H L LA3=B3 A2=B2 A1=B1 A0
SN54/74LS85A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3A n3A n2A n1A nB n3B n2B n1B nLLHA 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3 A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3I A > BO A > BI A > BO A > BI A SN54/74LS85 O A < BI A SN54/74LS85 O A < BI A = BO A = BI A = BO A = BL = LOW LEVELH = HIGH LEVELFigure 1. Comparing Two n-Bit WordsA > BA < BA = BAPPLICATIONSFigure 2 shows a high speed method of comparing two 24-bit words with only two levels of device delay. With the techniqueshown in Figure 1, six levels of device delay result when comparing two 24-bit words. The parallel technique can be expandedto any number of bits, see Table 1.WORD LENGTHTable 1NUMBER OF PKGS.1–4 Bits 15–24 Bits 2–625–120 Bits 8–31NOTE:The SN54/74LS85 can be used as a 5-bit comparatoronly when the outputs are used to drive the A 0 –A 3 andB 0 –B 3 inputs of another SN54/74LS85 as shown inFigure 2 in positions #1, 2, 3, and 4.INPUTS(LSB)A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3(MSB)A 20 A 21 A 22 A 23 B 20 B 21 B 22 B 23LLA 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3I A > BO A > BI A BO A > BI A < B #1 O A < BHI A = BO A = BLI A = BO A = BNCINPUTSA 10 A 11 A 12 B 13A 15 A 16 B 18B 4A 5 A 6 A 7 A 8 B 5 B 6 B 7 B 8A 13 B 10 B 11 B 12A 17 A 18 B 15 B 16 B 17I A < B#4 O A < BB 9 I A < B#3 O A < BB 14I A < B#2 O A < BA 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3A 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3A 4 I A > BO A > BA 9 I A > BO A > BA 14 I A > BO A > BL I A = BO A = B NCL I A = BO A = B NCL I A = BO A = BNCA 0 A 1 A 2 A 3 B 0 B 1 B 2 B 3I A > BI A < BI A = B#6O A > BO A < BO A = BOUTPUTSMSB = MOST SIGNIFICANT BITLSB = LEAST SIGNIFICANT BITL = LOW LEVELH = HIGH LEVELNC = NO CONNECTIONFigure 2. Comparison of Two 24-Bit WordsFAST AND LS TTL DATA5-3
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4-BIT MAGNITUDE COMPARATOR SN54/74LS85

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