Roadmap of SiGe BiCMOS Technologies - Avsusergroups.org

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0.18 µm SiGe BiCMOS Process IntegrationBaseSiGe NPNEmitterCollectorNFET and PFETDrainGateSourceN+ Buried LayerPwellNwellDeep TrenchP- Substrate
SiGe BiCMOS: Buried Layer IntegrationEpi-Based1. N+ Buried Layer Implant2. Buried Layer Drive3. N- EpitaxyEpi-Less1. High energy N+ Buried Layer ImplantN+P-N-N+P-Lower Collector ResistanceLower CostLower Collector Substrate Capacitance
Page 3 and 4: Continued dominance of bipolar in R
Page 6 and 7: Technology cost comparisonsRelative
Page 8 and 9: Wireless: 3G System Block DiagramDi
Page 10 and 11: Outline• Device Design for 200 GH
Page 12 and 13: Device Design for 200 GHz Ft and Fm
Page 14 and 15: SiGe Emitter Resistance1/Ft ~ (Re +
Page 16 and 17: SiGe Base Width1/Ft ~ (Re + kT/Ic)
Page 18 and 19: SiGe Base WidthPeak Ft (GHz)-25% Wb
Page 20 and 21: SiGe BiCMOS Landscape (Dec ‘01)Ft
Page 24 and 25: SiGe BiCMOS: IsolationDeep TrenchJu
Page 26 and 27: SiGe BiCMOS: Gate FormationGatePock
Page 28 and 29: SiGe BiCMOS: CMOS / SilicideCo Sili
Page 30: Conclusions• The bipolar device h

Roadmap of SiGe BiCMOS Technologies - Avsusergroups.org

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