Single Event Effects in Advanced SRAM and Logic ... - Sematech

Single Event Effects inAdvanced SRAM and LogicComponentsRobert BaumannDistinguished Member Technical StaffTexas Instruments, Inc.Dallas, TexasTRC: Oct 25-27, 2004

The 3 Radiation MechanismsT.C. May and M.H. Woods, IEEE Trans. Elec. Dev., 26, pp. 2-9, 1979Alpha ParticlesWere dominant, but minimized duringtechnology development by ultra-lowbackground alpha detection to verifyall materials meet ULA spec.4HeLow Energy NeutronsWere dominant, but eliminated when TIdiscovered effect and removed BPSGfrom C05 technology and beyond.R.C. Baumann et al., IEEE IRPS, p. 299, 1995High Energy Neutronsn (> 1 MeV)J.F. Ziegler and W.A. Lanford, Science,vol. 206, p.776, 1979.Cannot easily be shielded. Increases withaltitude. High charge generation efficiency.This is the dominant mechanism in TI products.n (< 100 eV)28Si, 16 O10B12/16/2004 • j://stdpres/template.pot • Slide 2

NomenclatureSEESingle eventeffectsSETSingle eventtransientSingle bit upsetSBUMultiple bit upsetMBUSingle event func.interuptSEFISingle event latch-upSELUSingle event gaterupture/BurnoutSEGR/SEBSEUSingleeventupsetSoftErrorHardError12/16/2004 • j://stdpres/template.pot • Slide 3

DRAM SER (a.u.)DRAM SER Scaling Trend1010.10.010.001SystemSERbit SERV dd1 10 100 1000DRAM Generation (Mbits)5.04.03.02.01.0Voltage (V)12/16/2004 • j://stdpres/template.pot • Slide 4

SER (A.U.)SRAM Bit SER Trend100101Based on embedded high-performance SRAM0.7µm0.35µm0.5µm0.25µm0.18µmw BPSG0.13µm0.09µm20.10.1 1 10 100 1SRAM Integration Level (Mbits)543Voltage (V)12/16/2004 • j://stdpres/template.pot • Slide 5

SRAM System SER TrendSER (A.U.)1000Based on embedded highperformanceSRAM1001010.5µm0.25µm0.35µmw BPSG0.18µm0.09µm0.13µm5432Voltage (V)0.7µm0.110.1 1 10 100SRAM Integration Level (Mbits)12/16/2004 • j://stdpres/template.pot • Slide 6

6T SRAM SER – Physics LimitedSoft Error FIT Rate/Mbit10000100010010* From Paul Dodd et al. IEEE 2003 IEDM,TI 6T Bulk CMOS(65nm - 0.25um)Sandia 6T CMOSSOI (Non-radhardversion)FIT Rate in NYC10.0 1.0 2.0 3.0 4.0 5.0 6.0Power Supply (V)4 vendors of6T BulkCMOS SRAM12/16/2004 • j://stdpres/template.pot • Slide 7

SER (A.U.)Logic SER Trend1010.10.010.0010.00010.25um0.18umSRAM bit SER (DC)Flip-flop/Latch SER (DC)Simulated FF/Latch SERSRAM bit SER (w ECC)0.13um 0.09um0.000011 10 100SRAM Integration Level (Mbits)0.065umNot derated forAC effects,logical masking.12/16/2004 • j://stdpres/template.pot • Slide 8

Latchup FIT Rate/Mbit100010010* From PaulDodd et al.IEEE 2003IRPS, p. 51-55ASELU Test ResultsVendor C: 3.3-V V 0.25-µm 6TSRAMs SELU rate 1000 FIT/MbitPower Supply (V)Vendor C25 o C85 o C125 o C11.0 1.5 2.0 2.5 3.0 3.5 4.0Latchup FIT Rate/Mbit100101Vendor A: 1.5-V V 0.16-µm 6T SRAMsShow Low SELU Rate (1-10 10 FIT/Mbit)25 o C125 o C0.11.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4HUGE SELU variation fromvendor-to-vendorPower Supply (V)12/16/2004 • j://stdpres/template.pot • Slide 9

More SELU dataNon-SEU Fail-Rate (FIT/Mbit)1010.10.010.00140C (24.1 Mbit SRAM)detection limit0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2Core Voltage (V)No fails seen at 0.9-1.3V.Limit of detection was0.0044 FIT/Mbit12/16/2004 • j://stdpres/template.pot • Slide 10

Critical Width for PropagationTechnologyf max500 Mhz1 Ghz2.5 Ghz5 GhzFrom P.E. Dodd, et al., “Production andPropagation of Single-Event Transientsin High-Speed Digital Logic ICs,” IEEENSREC, 2004100 Ghz12/16/2004 • j://stdpres/template.pot • Slide 11

Alternate Memories• FRAM• MRAM• Chalcogenide/phase change• These Memory elements are virtually immune in storage mode sincethey do not use charge storage but a ferroelectric/magnetic bistablestate or phase change to store information. The standard CMOSsupport circuitry IS however sensitive to SEE so sensitivity is definedby SEU of conventional circuit as well as access frequency.12/16/2004 • j://stdpres/template.pot • Slide 12

SOI vs. Bulk SEUNormalized alpha SER/Mb100101P. Roche et al., IEEE Trans. Nucl. Sci., 50(6), pp. 2046-2054 Dec. 2003.5xBulk 130nm 10SOI 130nm11.0 1.2 1.4 1.6Supply Voltage (V)Normalized neutron SER/Mb1005xBulk devicesSOI devices0.8 1.0 1.2 1.4 1.6 1.8Supply Voltage (V)12/16/2004 • j://stdpres/template.pot • Slide 13

Device Technology SolutionsModification Costs/Performance impact SER ImprovementVoltage/Temp scaling GOI, FET reliability, Power 5x (less for nSER)Node Cap. Scaling Extra mask, chip area, speed, power 1.5x - 5xSOI (Part. Dep.) Substrate cost, yield, layout complex. 0.1x – 5xMulti-well/buried layers Process complexity, yield, cost ~ 2 - 3xSOI (fully-depeleted)* Substrate cost, yield, layout complex. 3x – 50x* Not a production technology at this moment12/16/2004 • j://stdpres/template.pot • Slide 14

Design/Layout SolutionsModification Costs/Performance impact SER ImprovementNode Capacitance extra loads (gates), parasitics 1.3x - 3xResistive Hardening poly R/extra masks/delay*/no extra area 10x – 200xState Redundancy 2-3x chip area & power/no delay 10x - 1000xParity < 5% chip area, several gate delays > 1000xEDAC/ECC ~ 10-30% area increase (efficiency > 1000ximproves with width) several gate delaysTriple Mod. Redund. +3x chip area, small (voting) delay > 1000x12/16/2004 • j://stdpres/template.pot • Slide 15

Software/System SolutionsModification Cost/Performance ImprovementSoftware ECC Extra code uses available memory, > 1000xsystem throughput is slowed sinceprocessor must execute ECC code withevery fetch of protected words. Goodfor protecting program code.Multiprocessor Redun. Multiple processors running same code > 1000xFault Tolerant OS Assumes multi-processors > 1000x12/16/2004 • j://stdpres/template.pot • Slide 16