Mainframe Boot Camp Part 1 (pdf for Printing 4/page)

Robert RannieMilica KozomaraNorthern Illinois University - DeKalb, ILTexas Instruments - Dallas, TXAbout this SeriesMainframe OperatingSystems “Boot Camp”The General Purpose Computer and InterruptsPart 1Session #2895SHARE 112 in Austin, March 20091These sessions are derived from the System Programming course atNIU. This course makes extensive use of the ASSIST program (John R.Mashey, The Pennsylvania State University) and the extension of ASSISTto create ASSIST-V, An Environmental Simulator for IBM 360 SystemsSoftware Development (Charles E. Hughes & Charles E. Pfleeger,University of Tennessee).Both of these programs are available in the public domain. Thanks toMichael Stack they may be found at:http://www.kcats.org/assist/ and http://www.kcats.org/assist-v/2About this Series• Student Operating System (SOS) and otherassignments• Assist-V emulation environment• Comparative programs: emulation & MVS• XDAP/EXCP Channel Program:MVS DASDOur Agenda for the Week#2895 - Part 1: The General Purpose Computer and! ! ! Interrupts#2896 - Part 2: From IPL to Running Programs#2897 - Part 3: SVCs and More SVCs#2898 - Part 4: Program Interrupts! ! ! (You Want An Exit With That?)#2899 - Part 5: FLIH: I/O INTERRUPTS#2894 - Mainframe Operating System Boot Camp:! ! ! Highlights34

“Tell ‘em what you’re gonna tell ‘em”Basic Instruction Fetch (BIF) loop• Basic Instruction Fetch (BIF) Loop• The Interrupt Process• The Software Phase of Interrupt Processing• Operates in a loop• Depends on / is controlled by PSW• Acquires and processes every instruction tobe executed by CPU• Handles interrupts (if any) prior to everyinstruction fetch• Consists of 6 steps56Basic Instruction Fetch (BIF) loopStep 1 of 6 (Top of the Loop)1. While ( “processable” interrupts pending )2. ! {! Process highest priority Interrupt! }3. Proceed to Step 2Note: To better introduce the BIF loop, we begin byassuming there are no Interrupts to be processed and wereview the other parts of the loop.Basic Instruction Fetch (BIF) loopStep 2 of 6 (Instruction Fetch)1. Obtain address ofinstruction to be fetchedfrom PSW2. Determine length ofinstruction:• Examine first twobits pointed to byPSW (Op. Code)bits 0 & 1 ofinstructionlength ofinstruction0 0 2 bytes0 1, 1 0 4 bytes1 1 6 bytes78

Basic Instruction Fetch (BIF) loopStep 2 of 6 (Instruction Fetch)• Example 1 - Add• PSW points to instruction at X’000004’• We know machine code: 5A50C080Basic Instruction Fetch (BIF) loopStep 2 of 6 (Instruction Fetch)• Example 1 - Add• Op. Code X‘5A’ = B’01011010’• Implied length?bits 0 & 1 of instructionlength of instruction0 0 2 bytes0 1, 1 0 4 bytes1 1 6 bytes910Basic Instruction Fetch (BIF) loopStep 2 of 6 (Instruction Fetch)• Example 2 - 80 byte buffer• PSW points to “bogus” instruction atX’000016’• 80CL1’ ‘ = X’40404040...’Basic Instruction Fetch (BIF) loopStep 2 of 6 (Instruction Fetch)• Example 2 - 80 byte buffer• “Op. Code” X’40’ = B’01000000’• Implied Length?bits 0 & 1 of instructionlength of instruction0 0 2 bytes0 1, 1 0 4 bytes1 1 6 bytes1112

Basic Instruction Fetch (BIF) loopStep 2 of 6 (Instruction Fetch)• Example 2 - 80 byte buffer• X’40404040’ = STH 4,64(0,4)• Will be considered “valid” code• No SOC1 - may be executed• Debugging Problem - It’s all just bytesBasic Instruction Fetch (BIF) loopStep 3 of 6 (Set up ILC, Update PSW Address)1. Set Instruction Length Code (CODE) in PSW2. Increment address in PSW accordingly(2/4/6)bits 0 & 1 of ILC in PSWbytes (just fetched)0 0 n/a0 1 2 bytes1 0 4 bytes1 1 6 bytes1314Basic Instruction Fetch (BIF) loopStep 4 of 6 (Branching?)• Not covered in this sessionBasic Instruction Fetch (BIF) loopStep 5 of 6 (Executing the Instruction)• Probably most common place for ProgramCheck Interrupt• Confirms earlier point about PSW addressfield:If instruction fails where will PSW likely point?1516

Basic Instruction Fetch (BIF) loopStep 6 of 6 (Return to the Top of the BIF Loop)Please Note: The test for any pending interrupts will be madefollowing processing of each instruction AND interrupt. It willtherefore be made prior to the fetching and execution ofEVERY instruction processed by the CPU.Basic Instruction Fetch (BIF) loop• Let us now consider the BIF loop withInterrupt Processing:• Remember test for pending interrupts attop of BIF loop?• Let’s now assume there are pendinginterrupts to be processed1718Name ofInterruptExternalSupervisor CallProgram CheckMachine CheckInput/ OutputRestartThe Interrupt ProcessTypes of Interrupts (6)Example of this type of interruptSignal from an external processor. Expiration of a timeperiod.The executing program has issued an SVC X’xx’instruction (X’0Axx’).The executing program has caused a programinterruption (X’xxxx’).The executing program has encountered a hardwarefailure.An I/O operation has completed some portion(s) of itsoperation.A switch on the processor has been activated.The Interrupt Process• Composed of Hardware Component andSoftware Component• Hardware Component• 4 steps “hardwired” into CPU• Not programmable• First X’80’ bytes of memory• Known as PSW swap1920

The Interrupt ProcessThe Interrupt ProcessThe Four-Step Hardware Phase• Low Core• Memory location 0 - X’7F’• First 4K1. Current PSW is stored into appropriate oldPSW location2. Interrupt Code (IC) is stored into appropriate‘low core’ location• BC Mode: A(OLD PSW) + 2• Other Modes: refer to green cardfor fixed storage location2122The Interrupt ProcessThe Four-Step Hardware PhaseThe Interrupt ProcessFirst X’80’ Bytes of Memory3. If I/O interrupt - store Channel Status Wordinto X’40’4. Load current PSW from appropriate newPSW locationX’0’X’8’X’10’IPL PSWRestart New PSWIPL CCW1Restart Old PSWIPL CCW2A(MYCVT)X’18’X’20’X’28’X’30’X’38’External Old PSWSupervisor Call Old PSWProgram Check Old PSWMachine Check Old PSWInput/Output Old PSWX’58’X’60’X’68’X’70’X’78’External New PSWSupervisor Call New PSWProgram Check New PSWMachine Check New PSWInput/Output New PSWX’40’ Channel Status WordX’48’ CAW A(MYCVT)X’50’ CLOCK Trace Info2324

The Interrupt ProcessFirst Level Interrupt Handlers (FLIH)• New PSWs (normally) contain A(FLIH)• FLIH - set of instructions for handling theinterrupt• An FLIH for each interrupt type supported byCPUThe Interrupt ProcessFirst Level Interrupt Handlers (FLIH)• FLIH PSWs:• Masks - disabled for I/O and External• SVC, Restart and Program Check can’t bedisabled• Machine Check and Program MaskInterrupts Enabled• Key = 0; Supervisor State; Wait/Run = Run2526The Interrupt ProcessTo Process or Not?• “Masks” in PSW indicate whether or not toprocess a particular “class” of interrupts• Mask Bit = 1 - Allow/Accept Interrupts• referred to as “Masked On” / “Enabled”• Mask Bit = 0 - Don’t Allow/AcceptInterrupts• referred to as “Masked Off” / “Disabled”• Masks in PSWI/O ChannelsChannel Masks E PSW key c m w p Interruption Code0 7 8 12 16 31External MaskILC CC ProgrammaskThe Interrupt ProcessTo Process or Not?Machine Check MaskProgram Masks - S0C 8,A,D,EInstruction Address32 34 36 40 632728

The Interrupt ProcessTo Process or Not?• Handling sequence, from high priority (1) tolow priority (7)1. Exigent Machine Check 5. External2. Supervisor Call 6. I/O3. Program Check 7. Restart4. Repressible Machine CheckNote: After the processing of each one of the pending interrupts we return to thetop of the BIF loop for a new evaluation of all pending Interrupt.To Process or Not?• “Disposition” of interrupts which occur whilecorresponding type is masked offExternalSupervisor CallProgram CheckProgram MaskMachine CheckI/ORestartThe Interrupt ProcessRemain PendingN/A Cannot be masked offN/A (for those which cannot be masked off)Masked off are lost Applies to 8, A, D, EDepends on nature of machine checkRemain PendingN/A Cannot be masked off2930The Interrupt ProcessTo Process or Not?• New Concepts• PSW state => “Don’t run”, i.e. “Wait”• Privileged Instruction• Results in SOC2• Typically not encountered byApplication ProgrammersThe Software Phase of Interrupt ProcessingBeyond the PSW Swap: the “Essence” of a Program• What is the “Essence” of a Program?• Registers• PSW• Memory3132

The Software Phase of Interrupt Processing• Duties:Role of the First Level Interrupt Handler1. Save the Essence of the InterruptedProgram2. Direct execution to appropriate module3. Direct execution to code to restoreProgram from EssenceThe Software Phase of Interrupt ProcessingFundamental Control Blocks (CBs)• CBs involved in Essence saving• Communication Vector Table (CVT)• Task Control Block (TCB)• Request Block (RB)3334The Software Phase of Interrupt ProcessingFundamental Control Blocks (CBs)• Only 1 CVT• Address stored at X’10’ and X’4C’• TCB and RB for each unit of work• created in dynamically allocated memory• CVT, TCB and RB defined in DSECTs providedby IBM/RPR• Some points about SOSThe Software Phase of Interrupt ProcessingCharacteristics of Principal Control BlocksControl Block DSECT Name LocationCommunication Vector Table CVT Low CoreTCB Pointer also ‘TCBWORDS’ IEATCB Low CoreTask Control Block TCB DynamicRequest Block RB Dynamic3536

The Software Phase of Interrupt ProcessingControl Block LinkageMYCVT+0 A(TCBWORDS)TCBWORDS+4 A(current TCB)The Software Phase of Interrupt ProcessingHow the FLIH Saves the Essence• Register usage convention established for FLIHof SVCsTCB+0TCB+X’30’A(RB)A(TCBGRS)• Establish AddressabilityRB+X’10’A(RBOPSW)3738The Software Phase of Interrupt ProcessingHow the FLIH Saves the EssenceThe Software Phase of Interrupt ProcessingAfter Saving the Essence• FLIH transfers control to appropriate O/Smodule• Control returns to FLIH (normally)• FLIH restores program Essence3940

The Software Phase of Interrupt ProcessingHow to Restore the Essence• Reverse the process.• Assume R3 contains A(CVT)The Software Phase of Interrupt ProcessingA Small Problem• R3, R4, and R5 must be used to address CVT,TCB and RB:• What happened to original programvalues?• Stored in save area, maybe?• Then what about original value ofbase register used to address thatsave area?4142The Software Phase of Interrupt ProcessingAnswer: Low Core!• Why GPR 0 is ignored in D(X,B) and D(B):• Built-in feature• No register needed to address first 4K(0 through X’FFF’)• Now we have:The Software Phase of Interrupt ProcessingUtilizing Low Core• Any label in first 4K can be addressed implicitly• Generated machine code uses GPR 0 as base• Contents of GPR 0 ignored• Only displacement is used• Largest displacement is X’FFF’ = 40954344

The Software Phase of Interrupt ProcessingUtilizing Low Core45The Software Phase of Interrupt ProcessingUtilizing Low Core• No problem reloading FPRs from TCBFRS and GPRsfrom TCBGRS• Problem:• Addressability of RBOPSW is lost (R5 altered)• Can’t perform LPSW• Solution:• Move RBOPSW to Low Core location beforedestroying R546The Software Phase of Interrupt ProcessingSneak PreviewUtilizing Low CoreThe hardware feature that ignores the contents of GPR zeroin address calculations enables the saving of Registers andrestoring of PSWs that is ESSENTIAL to the operation of theGPC!• That’s why GPR zero is ignored in D(X,B) and D(B)addressing!Systems Programmers must understand the logic ofInterrupts on the GPC!Part 2: From IPL to Running Programs• What you need to RUN a program: (Basic O/S)• Initial Program Load (IPL)• Dispatcher• SVC-FLIH• SVC 1 (Wait), SVC 8 (Loader)• Master Scheduler4748

Questionsrrannie@cs.niu.edum-kozomara@ti.comwww.cs.niu.edu/~rrannie49