EE-364 Lab #3 VSC - Capitol College Faculty Pages

Procedure (Macrocode)Write a VSC (macro) program that computes and displays a Fibonacci sequence. AFbonacci sequence is generated by adding the two most recent sequence numberstogether, i.e., 1, 1, 1+1-2, 1+2=3, 2+3=5, 3+5=8, … The user will enter the number ofterms in the sequence to be displayed. Assemble this program using the VSC assembler(ASM), and simulate this program using the VSC simulator (SIM). Include a copy of thesource listing (SOURCE.DAT), the assembled listing (SLIST.DAT) and the simulationoutput in your lab report.Procedure (Microcode)In this lab you will design the hardware and write the microcode for the VSC. Attached isa block diagram for this hardware. The processor has a five-bit Program Counter (PC), afive-bit Memory Address Register (MAR), an eight-bit A-register, a three-bit instructionregister (IR) and a six-bit control address register (CAR). The six-bit control addressregister provides the input (the address) for the microcode ROM. The data output of themicrocode ROM is divided into two (main) groups: (1) a control output which enablesvarious data transfer operations within the CPU proper IRL, PCL, et al.), and (2) a nextmicroinstruction address output which (helps to) determine the address of the nextmicroinstruction. The next microinstruction address output consists of two three-bit fields;only one three-bit field is loaded into the CAR. Which three-bit field loaded into the CAR isdetermined by the output of the comparator:Comparator Output Three-bit Field Loadedhigh (=) #1 (D5 D4 D3)low () #2 (D2 D1 D0)The selected field provides the three least-significant bits of the control address. Themost-significant three bits of the control address are always equal to the instructionopcode.You will write the microcode for the instruction set using the attached sheets6