FDG901D Slew Rate Control Driver IC for P-Channel MOSFETs

FDG901DSlew Rate Control Driver IC for P-Channel MOSFETsApril 2002FDG901DGeneral DescriptionThe FDG901D is specifically designed to control theturn on of a P-Channel MOSFET in order to limit theinrush current in battery switching applications with highcapacitance loads. During turn-on the FDG901D drivesthe MOSFET’s gate low with a regulated currentsource, thereby controlling the MOSFET’s turn on. Forturn-off, the IC pulls the MOSFET gate up quickly, forefficient turn off.Features• Three Programmable slew rates• Reduces inrush current• Minimizes EMI• Normal turn-off speed• Low-Power CMOS operates over wide voltage rangeApplications• Power management• Battery Load switch• Compact industry standard SC70-5 surface mountpackageGATE15GNDpin 1SLEW2VDD34LOGIC INAbsolute Maximum RatingsTA=25 o C unless otherwise notedSymbol Parameter Ratings UnitsV DD Supply Voltage -0.5 to 10 VV IN DC Input Voltage (Logic Inputs) -0.7 to 6 VP D Power Dissipation for Single Operation @ 85°C 150 mWT J, T STG Operating and Storage Junction Temperature Range -65 to +150 °CRecommended Operating RangeV DD Supply Voltage 2.7 to 6.0 VT J Operating Temperature -40 to +125 °CThermal CharacteristicsR θJA Thermal Resistance, Junction-to-Ambient (Note 1) 425 °C/WPackage Marking and Ordering InformationDevice Marking Device Reel Size Tape width Quantity91 FDG901D 7’’ 8mm 3000 units©2002 Fairchild Semiconductor Corporation FDG901D rev. E (W)

Electrical CharacteristicsT A= 25°C unless otherwise notedSymbol Parameter Test Conditions Min Typ Max UnitsLogic LevelsV IH Logic HIGH Input Voltage V DD = 2.70V to 6.0 VV IL Logic LOW Input Voltage V DD = 2.70V to 6.0 V75%of V DD25%of V DDOFF CharacteristicsBV IN Logic Input Breakdown Voltage I IN = 10µA, V SLEW = 0 V 9 VBV SLEW Slew Input Breakdown Voltage I SLEW = 10µA, V IN = 0 V 9 VBV DG Supply Input Breakdown Voltage I DG = 10µA, V IN = 0 V, V SLEW = 0 V 9 VI RINLOGIC Input Leakage Current V IN = 8 V, V SLEW = 0 V 100 nAI RSLEW SLEW Input Leakage Current V SLEW = 8 V, V IN = 0 V 100 nAI RDG Supply Input Leakage Current V DG = 8 V, V IN = 0 V, V SLEW = 0 V 100 nAON CharacteristicsI G Gate Current V IN = 6V SLEW = OPEN 90 120 µAV GATE = 2V SLEW = GND 1 10 µASwitching Characteristicst don Output Turn-On Delay TimeSlew Pin = OPENt don Output Turn-On Delay TimeSlew Pin = GROUNDt don Output Turn-On Delay TimeSlew Pin = VDDt rise Output Rise TimeSlew Pin = OPENt rise Output Rise TimeSlew Pin = GROUNDt rise Output Rise TimeSlew Pin = VDDdv/dt Output Slew RateSlew Pin = OPENdv/dt Output Slew RateSlew Pin = GROUNDdv/dt Output Slew RateSlew Pin = VDDV Supply = 5.5 V, V DD = 5.5 V,Logic IN = 5.5 V,C LOAD = 510 pF, Test CircuitV Supply = 5.5 V, V DD = 5.5 V,Logic IN = 5.5 V,C LOAD = 510 pF, Test CircuitV Supply = 5.5 V, V DD = 5.5 V,Logic IN = 5.5 V,C LOAD = 510 pF, Test CircuitSLEW = V DD 10 50 nAVV8.3 µs0.6 ms2.2 ms28 µs1.8 ms11 ms162 V/ms2.6 V/ms0.3 V/msFDG901DNotes: R θJAis the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surfaceof the drain pins. R θJCis guaranteed by design while R θCAis determined by the user's board design.VDDV SUPPLY C LoadSLEW23LOGIC IN10%190%LOGIC IN45OUTPUT(Inverted)10%tdonTest CircuittriseSwitching WaveformsFDG901D rev. D (W)

Typical Characteristics10095Slew = OpenVdd=Vin=6V2.0Slew = GndVdd=Vin=6VFDG901D901.5Gate Current, (µA)858075Gate Current (µA)1.0700.56560-50 0 50 100 150Temperature, ( o C)0.0-50 0 50 100 150Temperature, ( o C)Figure 1. GATE Output current vs.Temperature. SLEW = OPENFigure 2. GATE Output current vs.Temperature. SLEW = GroundGate Current, (nA)14121086Slew = VddVdd=Vin=6VOutput Risetime, microseconds (µsec)100101Slew = OpenVdd=Vin=5.5V4-50 0 50 100 150Temperature, ( o C)0.11 10 100 1000Load Capacitance, picoFarad (pF)Figure 3. GATE Output current vs.Temperature. SLEW = V DDFigure 4. t rise vs. Load Capacitance.SLEW = OPENOutput Risetime, microseconds (µs)10000100010010Slew = GndVdd=Vin=5.5VOutput Risetime, milliseconds (ms)100101Slew = VddVdd=Vin=5.5V11 10 100 1000Load Capacitance, picoFarad (pF)0.11 10 100 1000Load Capacitance, picoFarad (pF)Figure 5. t rise vs. Load Capacitance.SLEW = GROUNDFigure 6. t rise vs. Load Capacitance.SLEW = V DDFDG901D rev. D (W)

ISourceDrainGateLoadLogicSignalSlew RateControl42VDD351IgApplication CircuitTypical ApplicationBattery powered systems make extensive usage of load switching, turning the power tosubsystems off, in order to extend battery life. Power MOSFETs are used to accomplish thistask. In PDA’s and Cell phones, these MOSFETs are usually low threshold P-Channels. Sincethe loads typically include bypass capacitor components (high capacitive component), a highinrush current can occur when the load is switched on. This inrush current can cause transientson the main power supply disturbing circuitry supplied by it.The simplest method of limiting the inrush current is to control the slew rate of the MOSFETswitch. This can be done with external R/C circuits, but this approach can occupy significant PCBarea, and involves other compromises in performance. The slew rate control driver IC FDG901Dis specifically designed to interface low voltage digital circuitry with power MOSFETs and reducethe rapid inrush current in load switch applications. The IC limits inrush current by controlling thecurrent, which drives the gate of the P-Channel MOSFET switch.The control input is a CMOS compatible input with a minimum high input voltage of 2.55V with apower rail voltage of 6V. Therefore, it is compatible with any CMOS logic voltages between2.55V and 5V and under these conditions there is no additional configuration required.FDG901D rev. D (W)

The Slew Rate Control Driver (FDG901D) is designed to give a programmed choice of one ofthree steady dv/dt states on the output during turn-on. To change the dv/dt value, the user needsto use the Slew Rate Control Pin (Pin 2). To utilize the smallest current setting (≈10 nA) from theIC, a voltage equal to Vdd must be applied to the Slew Rate Control Pin 2. To use the nexthigher current setting (≈1 µA) a voltage equal to Ground must be applied to Pin 2. To achieve thehighest current setting (≈ 80 µA) or obtain a faster switching speed, the Slew Rate Pin2 must beopen (floating). A higher value of capacitance will result in a slower switching rate. To determinethe switching times of each setting use the simple equation:Qt =Iwhere Q g is the Gate charge in nC for a given MOSFET and I G is the gate current controlled bythe slew rate pin.Below is a captured image from an oscilloscope depicting the device response. The FDG901Dwas connected to control an FDG258P P-Channel DMOS. The Slew Rate control pin was set toopen (floating state).gGTest Conditions:V DD = 5.5VV IN = 5.5VR LOAD = 1.5ΩV INV gate (inverted)V RLoadCircuit waveforms for an FDG901D controlling a P-Channel FDG258P MOSFET.FDG901D rev. D (W)

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