Verilator and SystemPerl - Veripool
Verilator and SystemPerl - Veripool
Verilator and SystemPerl - Veripool
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What <strong>Verilator</strong> Does• <strong>Verilator</strong> converts Synthesizable Verilog into C++– Always statements, wires, etc– No time delays ( a 10x slower!• Creates a "pure" SystemC wrapper around the design– Hides the internal signals <strong>and</strong> sensitivity lists from the user<strong>Verilator</strong> Environment, NASCUG June 2004. Copyright 2004 by Wilson Snyder; redistribution allowed as complete presentation.6
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