ccsds 131.0-b-2

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CCSDS RECOMMENDED STANDARD FOR TM SYNCHRONIZATION AND CHANNEL CODING– Forward connection vectors for rate 1/4 shall be G2 = 10101, G3 = 11111 (1stcomponent code); G1 = 11011 (2nd component code). No puncturing is donefor rate 1/4.3) Forward connection vectors for rate 1/6 shall be G1 = 11011, G2 = 10101, G3 =11111 (1st component code); G1 = 11011, G3 = 11111 (2nd component code). Nopuncturing shall done for rate 1/6.i) Turbo encoder operation:1) Each input frame of k information bits shall be held in a frame buffer, and the bitsin the buffer shall be read out in two different orders for the two componentencoders.2) The first component encoder (a in figure 6-2) shall operate on the bits inunpermuted order (‘in a’), while the second component encoder (b figure 6-2)shall receive the same bits permuted by the interleaver (‘in b’).NOTES1 The read-out addressing for ‘in a’ is a simple counter, while the addressing for‘in b’ is specified by the Turbo code permutation described in 6.3g).2 The recommended encoder block diagram is shown in figure 6-2.3 The component encoders are recursive convolutional encoders realized byfeedback shift registers as shown in figure 6-2. The circuits shown in thisfigure implement the backward connection vector, G0, and the forwardconnection vectors, G1, G2, G3, specified in 6.3h). A key difference betweenthese convolutional component encoders and the standalone convolutionalencoder recommended in section 3 is their recursiveness. In the figure this isindicated by the signal (corresponding to the backward connection vector G0)fed back into the leftmost adder of each component encoder.j) Turbo Codeword specification:1) Both component encoders (see figure 6-2) shall be initialized with ‘0’s in allregisters, and both shall run for a total of k+4 bit times, producing an outputCodeword of (k+4)/r encoded symbols, where r is the nominal code rate.2) For the first k bit times, the input switches shall be in the lower position (asindicated in figure 6-2) to receive input data.3) For the final four bit times, these switches shall move to the upper position toreceive feedback from the shift registers.CCSDS <strong>131.0</strong>-B-2 Page 6-6 August 2011
CCSDS RECOMMENDED STANDARD FOR TM SYNCHRONIZATION AND CHANNEL CODINGNOTE – This feedback cancels the same feedback sent (unswitched) to theleftmost adder and causes all four registers to become filled with zerosafter the final 4 bit times. Filling the registers with zeros is calledterminating the trellis.4) During trellis termination the encoder shall continue to output nonzero encodedsymbols. In particular, the ‘systematic uncoded’ output (line ‘out 0a’ in thefigure) shall include an extra four bits from the feedback line in addition to the kinformation bits.NOTE – In figure 6-2, the encoded symbols are multiplexed from top-to-bottom alongthe output line for the selected code rate to form the Turbo Codeword. Forthe rate 1/3 code, the output sequence is (out 0a, out 1a, out 1b); for rate 1/4,the sequence is (out 0a, out 2a, out 3a, out 1b); for rate 1/6, the sequence is(out 0a, out 1a, out 2a, out 3a, out 1b, out 3b). These sequences are repeatedfor (k+4) bit times. For the rate 1/2 code, the output sequence is (out 0a, out1a, out 0a, out 1b), repeated (k+4)/2 times. This pattern implies that out 1b isthe first to be punctured, out 1a is the second, and so forth. The TurboCodewords constructed from these output sequences are depicted in figure6-3 for the four nominal code rates.CCSDS <strong>131.0</strong>-B-2 Page 6-7 August 2011
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ccsds 131.0-b-2

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