Magazine - 1000 BiT

More documents

Recommendations

Info

NVAX-microprocessor VAX SystemsINSTRUCTION FETCH,DECODE, SPECIFIER €VAL,MEMORY REQUESTSO S1 52 S3 54 S5 S6VICREADINSTNPARSEOPERNDREADADDMEMREQTBP-CACHEINTEGER, LOGICALINSTRUCTION EXECUTIONFLOATING-POINTINSTRUCTION EXECUTIONKEY:SSPECIFIER EVALINSTNOPERNDMEMREQTBSEGMENTSPECIFIER EVALUATIONINSTRUCTIONOPERANDMEMORY REQUESTTRANSLATION BUFFERALUCSEXPON DlFFALIGN, FRMULTNORM, FRADDBYPASS ROUNDARITHMETIC LOGIC UNITCONTROL STOREEXPONENT DIFFERENCEALIGNMENT AND FRACTION MULTIPLYNORMALIZATION AND FRACTION ADDITIONRESULT ROUNDING AND BYPASSno stalls for results feecling directly into subsequentoperands. The M-box processing of memoryreferences initiated as a result of operand specifierprocessing by the I-bos is usually overlappetlwith tlie execut~on of the previous instruction inthe E-box, witli few or no stalls occurring onP-cache hit.Design Evolution and Trade-08sThe N\Wi and W !+ chips are tlie latest in a line ofCMOS VM microprocessors designed by Digital'sengineers and represent a continuing evolution ofarchitectural concepts from one irnp1ernent;ltionto the next. The preceding chip clesign was theCPrJ for the VAX 6000 Model 400 system.I2 To meettlie time-to-market ancl performance goals, wehad to modify the NV~U/NVAX+ design throughouttlie project.One of the early vehicles for making tlesigntrade-offs was the WAX performance model,which predicts CPIJ and system performanceand aids in quantifying the performance impactof various tlesign options. The performancemode.1 is a detailed, trace-clriven motlel which canbe easily configuretl by changing any of ;I varietyof input parameters. The modcl stimuli usedwere 15 generic timesharing ancl 22 benchmarkinstruction trace files that were captilredby running actual programs on existing VAXsystems.The followi~ig sections describe tlie evolutionof the chip design, including the number of chips,the pipelining technique used, and various cacheissues.N~~rnDer of CPU ChipsThe VLY 6000 Model 400 core CPIl in~l>lemenrationis a three-chip design: a processor chip, with asm;~ll on-chip primary cache; a floating-point chip;and a secondary cache controllel; with internalcache tags. The initial attempt at NVLY CPIJ definitionwas a two-chip design. One chip containedthe I-box (with a 410 VIC), the E-box. the F-box, andthe Mbos (witli a ~GKB, direct-mapped P-cache).The second chip held the C-box ant1 the B-cache tagarray. The project design goals, especially time-tomarket,let1 to a single-chip solution. rather thana two-chip design.To condense the design from two chips to one,we halved the sizes of the Wc; ant1 the P-cache andrnovecl the R-cache tags to external static UMs,leaving the B-cache controller on-chip. Later, wewere able to reduce the penalty of halving the sizeof the I-'-cache by making it two-way set associativerather than direct mapped. With these changes, theperformance moclel showed a performance loss ofless t11;1n 1.4 percent across all the traces, relativeto the two-chip design, with a worst-case pen~ltyof 3.9 percent.There ;Ire strong z~dvantages to the single-chipsolution.Designing a single chip takes less time.This design requires the production ancl maintenanceof only one design database and onemask set.Latency to the B-cache is shorter.An off-chip tag store provides more flexibility inH-cache configurations.
The WAX' and /WAX+ High-performance VAX 1~4icro,!1rocessorsMacropipeliningRun-time perfortnance is the product of the cycletime, the average time to execute an instruction(cycles per instruction [CHI) ant1 the number ofinstructions executed. CMOS process improvementsmade it possible to decrease the hViu;/N\iiU(+ cycle time with respect to the previous generationof ~a microprocessors, thus improving thefirst factor in run-time performance.The VM 6000 Model 400 CPU design uses traditionalmicroinstruction pipelining, i.e., micropipelining,to achieve some amount of overlap andto decrease the CPI. However, using micropipeliningtechniques would not reduce the WAX/N\IN(+
Page 2 and 3: Cover DesignThe WRX microprocessor
Page 4 and 5: I Editor's IntroductionJane C. Blak
Page 6 and 7: John F. Brown After receiving an 3.
Page 8 and 9: Thomas E. Kopec Principal engineer
Page 10 and 11: Rebecca L. Stamm Rebecca Stamm is a
Page 12 and 13: semiconductor process development s
Page 14 and 15: WAX-microprocessor VAX Systenls500,
Page 16 and 17: AROTATORMV$UTCHESFigure -3Block Dia
Page 19: The WAX on61 WAX+ Hi,q/3-l~erfor~nn
Page 23 and 24: X riizd NVAX+ ~ //R~-/I~~O~'II?L~IZ
Page 25 and 26: A. Dipace, C. Dobriansky, D. Donchi
Page 27 and 28: The NVAX CPU Chip: Ilesig~z Cl.alle
Page 29 and 30: The NVA X CPCI Chip: Design Challen
Page 31 and 32: areas were in tlesign. Since layout
Page 33 and 34: The NVAX CPU Chip: Design CL7alleng
Page 35 and 36: The W AX CPU Chip: Design Challenge
Page 37 and 38: The WXX CPU Chip: Design Challenges
Page 39 and 40: The NVAX CI'U Chq~: Design Challeng
Page 41 and 42: Lowical Verification of the lWAX CP
Page 43 and 44: Logicul Verijiccltion of the NVAX C
Page 45 and 46: Logical Vcrificntion of the WAX CPU
Page 47 and 48: Table 1 Bug Detection UsingVarious
Page 49 and 50: Lawrence Cbisvin&egg A. BouchardTho
Page 51 and 52: The VAX 6000 Model 600 Processorcon
Page 53 and 54: The VAX 6000 Model 600 Processorarb
Page 55 and 56: The VAX GOO0 Model 600 Processorat
Page 57 and 58: The V'AX 6000 Model 600 Processorcl
Page 59 and 60: The VAX 6000 Model 600 Processorpow
Page 61 and 62: The V M GO00 iModel600 ProcessorFig
Page 63 and 64: Design of the VRX 4000 iModel400,50
Page 65 and 66: Design ofthe V'AX 4000 Model 400, 5
Page 67 and 68: Design of the VAX 4000 Model 400, 5
Page 69 and 70: Design of the VRX 4000 Model 400,50
Page 71 and 72:
1;ltenc)i problem had to be solved
Page 73 and 74:
Design of the VAX 4000 Model 400,50
Page 75 and 76:
Jonathan C. CrotuellDavid W Maruska
Page 77 and 78:
The Design of the VAX 4000 rModel10
Page 79 and 80:
The Desigiz oJthe VAX 4000 ~Vlodel
Page 81 and 82:
711~ L)CS~.I(IZ of tlgc VM 4000 /Mo
Page 83 and 84:
Tl7e Desiyn of the VRY 4000 Model 1
Page 85 and 86:
The VAXstation 4000 Model 90availab
Page 87 and 88:
Table 1Model 90 Component SourceCor
Page 89 and 90:
110 1/0 pins of a 160-pin I'oFI'. T
Page 91 and 92:
CEACCHlPSQWFCHlPNVAX I10ADAPTER (NC
Page 93 and 94:
Table 5 PLB Graphics Performance Co
Page 95 and 96:
VAX 6000 Error Hundlitzg: A Prugmat
Page 97 and 98:
VAX GOO0 Ewor Handlin~: A Pra~matic
Page 99 and 100:
VAX 6000 Crror H~~tzdll~lg A PIZI~I
Page 101 and 102:
MX 6000 Error Hun~llil-zg: A l'ragm
Page 103 and 104:
VAX 6000 I:',-ror F1~117dli1 IS: A
Page 105 and 106:
VAX 6000 El-/.or HLI lz~/lit?~: A P
Page 107:
ISSN 0898-90 1 X
show all

Magazine - 1000 BiT

Create successful ePaper yourself

Delete template?

Save as template?