4-STAGE PRESETTABLE RIPPLE COUNTERS SN54/74LS196 ...

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SN54/74LS196 • SN54/74LS197LOGIC DIAGRAMMRPL131P0 P1 P2 P3410311CP08J S D QJ S D QJ S D QJ S D QK C D QK C D QK C D QK C D QCP165 9212Q0 Q1 Q2 Q3LS196MRPL131P0 P1 P2 P3410311CP08J S D QJ S D QJ S D QJ S D QK C D QK C D QK C D QK C D QCP165 9212Q0 Q1 Q2 Q3LS197VCC = PIN 14GND = PIN 7= PIN NUMBERSFAST AND LS TTL DATA5-2
SN54/74LS196 • SN54/74LS197FUNCTIONAL DESCRIPTIONThe LS196 and LS197 are asynchronously presettable decadeand binary ripple counters. The LS196 Decade Counteris partitioned into divide-by-two and divide-by-five sectionswhile the LS197 is partitioned into divide-by-two and divideby-eightsections, with all sections having a separate Clock input.In the counting modes, state changes are initiated by theHIGH to LOW transition of the clock signals. State changes ofthe Q outputs, however, do not occur simultaneously becauseof the internal ripple delays. When using external logic to decodethe Q outputs, designers should bear in mind that the unequaldelays can lead to decoding spikes and thus a decodedsignal should not be used as a clock or strobe. The CP0 inputserves the Q0 flip-flop in both circuit types while the CP1 inputserves the divide-by-five or divide-by-eight section. The Q0output is designed and specified to drive the rated fan-out plusthe CP1 input. With the input frequency connected to CP0 andQ0 driving CP1, the LS197 forms a straightforward module-16counter, with Q0 the least significant output and Q3 the mostsignificant output.The LS196 Decade Counter can be connected up to operatein two different count sequences, as indicated in the tablesof Figure 2. With the input frequency connected to CP0 andwith Q0 driving CP1, the circuit counts in the BCD (8, 4, 2, 1)sequence. With the input frequency connected to CP1 and Q3driving CP0, Q0 becomes the low frequency output and has a50% duty cycle waveform. Note that the maximum countingrate is reduced in the latter (bi-quinary) configuration becauseof the interstage gating delay within the divide-by-five section.The LS196 and LS197 have an asynchronous active LOWMaster Reset input (MR) which overrides all other inputs andforces all outputs LOW. The counters are also asynchronouslypresettable. A LOW on the Parallel Load input (PL) overridesthe clock inputs and loads the data from Parallel Data (P0–P3)inputs into the flip-flops. While PL is LOW, the counters act astransparent latches and any change in the Pn inputs will be reflectedin the outputs.Figure 2. LS196 COUNT SEQUENCESDECADE (NOTE 1) BI-QUINARY (NOTE 2)COUNT Q3 Q2 Q1 Q0 COUNT Q0 Q3 Q2 Q10 L L L L 0 L L L L1 L L L H 1 L L L H2 L L H L 2 L L H L3 L L H H 3 L L H H4 L H L L 4 L H L L5 L H L H 5 H L L L6 L H H L 6 H L L H7 L H H H 7 H L H L8 H L L L 8 H L H H9 H L L H 9 H H L LNOTES:1. Signal applied to CP 0 , Q 0 connected to CP 1 .2. Signal applied to CP 1 , Q 3 connected to CP 0 .MODE SELECT TABLEINPUTSMR PL CPRESPONSEL X X Reset (Clear)H L X Parallel LoadH H CountH = HIGH Voltage LevelL = LOW Voltage LevelX = Don’t Care= HIGH to Low Clock TransitionFAST AND LS TTL DATA5-3
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4-STAGE PRESETTABLE RIPPLE COUNTERS SN54/74LS196 ...

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