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4-STAGE PRESETTABLE RIPPLE COUNTERS SN54/74LS196 ...

4-STAGE PRESETTABLE RIPPLE COUNTERS SN54/74LS196 ...

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<strong>SN54</strong>/<strong>74LS196</strong> • <strong>SN54</strong>/74LS197AC CHARACTERISTICS (TA = 25°C)LS196LimitsLS197Symbol Parameter Min Typ Max Min Typ Max Unit Test ConditionsifMAX Maximum Clock Frequency 30 40 30 40 MHztPLHtPHLCP0 Input toQ0 Output8.01315208.0141521nstPLHtPHLCP1 Input toQ1 Output1622243312231935nstPLHtPHLtPLHtPHLCP1 Input toQ2 OutputCP1 Input toQ3 Output38411230576218453442556351637895nsnsVCC = 5.0 VCL = 15 pFtPLHtPHLData to Output2029304418292744nstPLHtPHLPL Input toAny Output2730414526303945nstPHL MR Input to Any Output 34 51 34 51 nsAC SETUP REQUIREMENTS (TA = 25°C)LimitsLS196LS197Symbol Parameter Min Typ Max Min Typ Max Unit Test ConditionsitW CP0 Pulse Width 20 20 nstW CP1 Pulse Width 30 30 nstW PL Pulse Width 20 20 nstW MR Pulse Width 15 15 nsts Data Input Setup Time — HIGH 10 10 ns VCC = 5.0 Vts Data Input Setup Time — LOW 15 15 nsth Data Hold Time — HIGH 10 10 nsth Data Hold Time — LOW 10 10 nstrec Recovery Time 30 30 nsDEFINITIONS OF TERMSSETUP TIME (ts) — is defined as the minimum time requiredfor the correct logic level to be present at the logic input prior tothe clock transition from HIGH to LOW in order to be recognizedand transferred to the outputs.HOLD TIME (th) — is defined as the minimum time followingthe clock transition from HIGH to LOW that the logic level mustbe maintained at the input in order to ensure continued recognition.A negative HOLD TIME indicates that the correct logiclevel may be released prior to the clock transition from HIGH toLOW and still be recognized.RECOVERY TIME (trec) — is defined as the minimum timerequired between the end of the reset pulse and the clocktransition from HIGH to LOW in order to recognize and transferLOW Data to the Q outputs.FAST AND LS TTL DATA5-5

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