Md Ishfaqur Raza, PhD - East West University

Teaching Workshops:- On my own initiative, I (along with another faculty member) have conducted 2 workshops onteaching, for the faculty of science and engineering, attended by 30+ faculty members, senior(professors) and junior teachers.o Topic 1: College teaching using active learning techniques (fall 2007)o Topic 2: Understanding the meta role of a university professor (spring 2008)- I have offered several workshops for students on Matlab and Spice.Employment Details(4/1997-4/2007): Staff Engineer, Intel Corporation, DuPont, Washington, USAObservability Debug: Current & future generation memory technology probing/debug solutions.• Designed on-die debug hooks in buffer chip for a next generation memory technology (FB-DIMM2) running at greater than 4.8 GTs. The design was done to create a stand-alone trace toolfor resolving complex bugs and ultimately save on costly test and measurement instrumentation.This design will be implemented by several companies.• Defined the electrical and control architecture of logic analyzer probes for the new memorytechnology called FB-DIMM. The designs were done to make probes work with different systemconfigurations. A new protocol was defined to ensure probe and system BIOS worked seamlessly.The protocol is being made a standard via JEDEC.• Detail simulation analysis was done to measure impact of probing high speed (3.2-6 GTs)pt-pt differential buses. The result of this simulation caused a new paradigm to evolve; movingaway from direct probing to repeater based probing. The analysis modeled different signalconditioning techniques such as equalization. Parametric variations were also investigated usingDOE statistical simulation technique.• Provided technical leadership to four different companies (Agilent, FP, Nexus, andTektronix) and help design, manufacture, and validate their logic analyzer probes. The probeshave been successfully used at different Intel labs validating different systems.Signal integrity, power delivery, and EMI, Server microprocessor division.Designed the on-board power delivery and decoupling system for the Pentium IIImicroprocessors, Intel’s flagship server processor, XEON. These make the backbone of Intel’sprocessor suites in high performance server machines. This demanded new design methodologiesand state of the art simulation tools (HFSS, Hspice, Q3D, etc).Supervised a team to validate Intel Corporation’s flagship Pentium IV microprocessor powerdelivery to ensure it compliance with design specifications before the processor is cleared forrelease as a new high frequency and high performance Intel product.Mentored junior engineers and interns and guide them through projects and technicalissues. Mentored engineers and taught tools of the trade, in particular new memory technology,power delivery design, and probe architectures.Research and Investigation: Work on cutting edge technology for performance• Supervised a research investigation between Intel Corporation and several vendors to develop anew passive buried resistor technology for use in next generation high speed bus probes. Wereviewed manufacturing and design issues and worked to develop the technology.• Coordinated an inter-departmental R&D effort to develop an EMI containment strategy for nextgeneration processors as CPU speed were hitting close to 1 GHz. The investigation resulted in afaraday cage solution that was implemented on several generations Intel microprocessors.