High-Speed SiGe BiCMOS Technologies - University of Toronto

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esult of this is a step-by-step roadmap aiming at the bestcombination between CMOS density and HBTperformance. This roadmap will go on as long as Si/SiGeCHBT performances can be pushed forward (withsignificant advantages over CMOS) and applications toever increasing frequencies carry on.Advanced developments are in progress to furtherimprove device characteristics, always having theBiCMOS integration as a target. Since HBT performanceis not directly linked to a CMOS node, the improvementcan be made inside a node (cf. BiCMOS9 /BiCMOS9MW) or from one node to another.Nevertheless, FEOL (front-end of line) and BEOLprocessing, overall thermal budget, and available designrules have an impact on the HBT performance through thevertical profile and/or the lateral dimensions. f T is indeedmainly determined by the vertical profile while lateraldimensions have considerable impact on f max , NF min andpower consumption.Fig. 9. Schematic comparison of the BEOL cross-sections ofBiCMOS9 and BiCMOS9MW technologies (both feature 6copper metal layers but with twofold height difference).III. END-OF-ROADMAP CHALLENGESA. The BiCMOS roadmapBiCMOS roadmap does not follow Moore’s law, whosedriver is the shrink of digital functions. The move fromone CMOS node to the next can be motivated by theincrease of gate density. Then, HBT performance mayremain unchanged if operation frequency of the targetedapplication does not change (e.g. cellular phonetransceivers). This roadmap is likely to end with thedramatic increase of HF performances of advanced CMOStechnologies.On the contrary, high-speed BiCMOS roadmap is drivenby, on one hand the increase of the opticalcommunications data rate, and on the other hand theemergence of applications towards higher frequencies. TheB. From 120 nm to 65 nm…and 45 nm to the end of theroadmapFrom the current 120-nm node to the next 90-nm and65-nm nodes, the main limitations are first, the final annealperformed for CMOS junctions activation (~1100°C: only~30°C reduction in 65 nm compared to 120 nm and90 nm) and second, the BEOL design rules that are not infavor of the high current densities needed by the HBT. It isindeed important to notice that raising the collector dopingto delay the onset of the Kirk effect, which is an efficientway to improve f T , leads to an increase of the collectorcurrent density at peak f T (cf. Fig. 10). The limits of ourpresent bipolar architecture, with the integration scheme inuse (HBT between polygate deposition and final anneal),is probably close to 300-GHz f T for a CMOS spike annealof ~1100°C: 280-GHz f T and 300-GHz f max has indeedbeen achieved while the extracted intrinsic cut-offfrequencies of this device are 380-GHz f T and 350-GHzf max (cf. Fig. 11). Cryogenic measurements have shownthat this architecture can potentially reach higherperformances (at room temperature, with a differentintegration scheme) since ~ 400-GHz f T and 440-GHz f maxhave been measured at 50 K (cf. Fig. 12). This is thehighest f max ever reported for a SiGe:C HBT since thedevice reported in [12] features a relatively low f max thatdoes not increase significantly at low temperature. Circuitresults have indeed shown that f max must not be sacrificedfor f T [7]. Architecture changes are currently beinginvestigated to approach cryogenic performances at roomtemperature, without changing the integration scheme andkeeping the 1100°C spike anneal.
f T(GHz)3002802602402202001801608 12 16 20J C@ peak f T(mA/µm 2 )dopant activation with nearly no diffusion. This isfavorable for realizing narrow neutral base widths but callsfor the development of new materials for the extrinsic baseand for the emitter: For example, arsenic has to bereplaced by phosphorus for the in-situ doping of thepolyemitter. A TEM cross-section of a first device using aboron in-situ doped polybase, a phosphorus-doped emitterand nickel silicide is shown in Fig. 13. Beyond 45 nm, theuse of very thin SOI substrates that could belong to themainstream CMOS will exacerbate the BiCMOSintegration challenge [13].Fig. 10. Evolution trend of the current gain cut-off frequency f Twith the collector current density J C .5040h 21intrinsic h 21U intrinsic UA E= 0.13 x 3.5 µm²V CB= 0.5 VV BE= 0.9 Vh 21,U (dB)302020dB/decf T= 380GHz / f max= 350GHz10f T= 280GHz / f max= 300GHz01 10 100Frequency (GHz)500Fig. 11. HF gains vs. frequency characteristics of a 280-GHz f T– 300-GHz f max HBT. Intrinsic device, extracted by removingextrinsic components, features 380-GHz f T and 350-GHz f max .f T& f max(GHz)500450400350300250200150100500T=295K: f Tf max/ T=48K: f Tf maxA E= 0.15x3.6 µm²V CB= 0.5 V0.01 0.1 1 10 100J C(mA/µm 2 )Fig. 12. f T & f max vs. J C curves of a Si/SiGeC HBT at 295 K and48 K. Peak f T and f max increase from 250 GHz / 280 GHz at295 K to 400 GHz / 440 GHz at 48 K.From the 45-nm CMOS node to the end of the roadmap,the situation is reversed for the thermal budget since spikeannealing is replaced by laser annealing, which allowsFig. 13. TEM cross-section of a FSA Si/SiGeC HBT(W E ~ 100nm) with boron in-situ doped polybase, phosphorusdoped emitter and nickel silicide.C. Levering up the HBT limitsRaising the transistor speed requests the increase of boththe doping level of the neutral regions of the HBT and theabruptness of the junctions, which are conflicting targets.Tunneling currents may appear [11] due to this scalingand, more classically, BV CEO decreases for increasing f T .Therefore, the main hurdle to maintaining a significantadvantage over CMOS is to break up the classical tradeoffbetween BV CEO and f T . A significant improvement hasbeen achieved in the past years with the introduction ofcarbon in the base to reduce boron diffusion.Solutions currently investigated to increase BV CEOwithout affecting f T focus on the increase on the basecurrent [14]-[15]-[16]. Results of recent investigations,summarized in Fig. 14, have shown an encouragingprogress of more than 50 GHz.V of the f T × BV CEO productby increasing the base current through base [15] orthrough emitter [16] engineering. This last solution,relying on a ‘metallic’ emitter transistor, can be obtainedin a robust way by using an original process of polyreplacement through contact holes (Fig. 15).Nevertheless, high-power / high-frequency circuitsshould still require III-V technologies, in whichbreakdown voltages benefit from larger bandgap materials.
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High-Speed SiGe BiCMOS Technologies - University of Toronto

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