MC8121 - abov.co.kr

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MC8121SDASTARTSLAVE ADDRESS W A REGISTER ADDRESS A WRITE BYTE 0 A WRITE BYTE N A STOPSDA INSDA OUTSCL1 9 1 9 1 9 19Figure 2-5 I2C Write Protocol2.1.6.2 READ PROTOCOL (MASTER RECEIVER)The master transmits a start condition(S), slave address and Write bit. If the high 7-bits of addresspacket equal to the device’s slave address, the MC8121 acknowledges by pulling down the SDA lineat the 9 th SCL clock period. After address packet and acknowledge bit, the master transmits a datawhich is used for base address accessing internal memory or register of the device. To initiate readoperations, the master sends repeated start condition and slave address with Read bit. After thisaddress packet, the master reads data bytes until it does not acknowledges. Note that to send a stopcondition after receiving last data byte, the master must generate a NACK(not acknowledging) on thelast data byte received. Like Write Protocol, the read address increases by 1 after every read byte.Note that the transfer direction changes in this protocol.SDASSLAVE ADDRESS W A REGISTER ADDRESS A SrSLAVE ADDRESS R A READ BYTE 0 A BYTE 1SDA INSDA OUTSCL1 9 1 9 1 9 1 9 1Figure 2-6 I2C Read Protocol2.2 REGISTERS2.2.1 OVERVIEWThe MC8121 is controlled and monitored by 17 registers. These registers provide a variety of controlfunctions and can be read to determine results of the ADC conversions.16 May 2013 REV1.61
MC81212.2.2 REGISTER MAPName Address Dir Default DescriptionADDRSET - W - Address Set RegisterCONTROL 00 H R/W 00 H Control RegisterINTR 01 H R/W 80 H Interrupt Control RegisterATIME0 02 H R/W FF H ALS CH0 Integration Time RegisterATIME1 03 H R/W FF H ALS CH1 Integration Time RegisterWTIME 04 H R/W 01 H Wait Time RegisterAILTL 05 H R/W FF H ALS CH0 Interrupt Low Threshold Low RegisterAILTH 06 H R/W 03 H ALS CH0 Interrupt Low Threshold High RegisterAIHTL 07 H R/W FF H ALS CH0 Interrupt High Threshold Low RegisterAIHTH 08 H R/W BF H ALS CH0 Interrupt High Threshold High RegisterPERSIST 0D H R/W 00 H ALS Interrupt Persistence RegisterADATA0L 0E H R FF H ALS CH0 ADC Data Low RegisterADATA0H 0F H R FF H ALS CH0 ADC Data High RegisterADATA1L 10 H R FF H ALS CH1 ADC Data Low RegisterADATA1H 11 H R BF H ALS CH1 ADC Data High RegisterID 12 H R A1 H ID Register NOTEAGC0 14 H R/W 01 H ADC Gain control 0 RegisterAGC1 15 H R/W 99 H ADC Gain control 1 RegisterTable 2-1 Registers of MC8121Caution : Do not alter registers addressed 1D H to 1F H . Writing to these registers may result inunexpected function.NOTEDefault value is A1 H for MC8121.2.2.3 REGISTER DESCRIPTIONADDRSET (Address Set Register)-- H7 6 5 4 3 2 1 0- - - ADDR4 ADDR3 ADDR2 ADDR1 ADDR0- - - W W W W WInitial value : 00 HADDR[4:0]Base address for subsequent register access. When the I2C masterinitiates a write protocol with start bit and slave address transfer, thesecond byte is used to configure register address.CONTROL (Control Register)00 H7 6 5 4 3 2 1 0ONESHOT SOFTRST - NOTE1 - NOTE1 MODE2 MODE1 MODE0 POWERR/W R/W - - R/W R/W R/W R/WInitial value : 00 HONESHOTStops ADC integration on completion of one integration cycle.0 Continuous operation.1 Once an integration cycle is over, ALS ADC will automaticallyMay 2013 REV1.61 17
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Page 6 and 7: MC8121MC8121Digital Ambient Light S
Page 8 and 9: MC81211.6 PIN CONFIGURATIONSTOP VIE
Page 10 and 11: MC81211.10.2 RECOMMENDED OPERATING
Page 12 and 13: MC8121Spectrum of MC8121 is the bel
Page 14 and 15: MC8121START and STOP conditions are
Page 18 and 19: MC8121stop and also the MODE[1:0] b
Page 20 and 21: MC812100000001 4.5ms 18ms00000010 9
Page 22 and 23: MC8121ADATA1H (ALS CH1 ADC Data Hig
Page 24 and 25: MC8121ALS InterruptAn ALS interrupt
Page 26 and 27: MC81212.4 APPLICATION INFORMATION :
Page 28: MC8121S Slave Address 0 A Word Addr

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