MC80F7708 - abov.co.kr

ABOV SEMICONDUCTOR Co. Ltd.8-BIT SINGLE-CHIP MICROCONTROLLERSMC80F7708User’s Manual (Ver. 1.21)

REVISION HISTORYVERSION 1.21 (December 03, 2012) This BookABOV logo is renewed on this book.Single and Gang writer are updated in "1.3 Development Tools" on page 3.VERSION 1.2 (March 17, 2009)Modify Timer capture mode description in “Figure12-10 / Figure 12-11/Figure 12-15 8bit/16bit capture mode”.VERSION 1.1 (February 2, 2009)Modify BIRR description in “Figure24-1 Block Diagram of BIR (Built-In Reset)”.Modify Port structures(R43, R42 ,R20/AN0~R23/AN3, R24/AN4~R25/AN5)VERSION 1.0 (April 1, 2008)Corrected PSW(NVGBHIZC) for “INC A” instruction from N-----ZC to N-----Z- at " Arithmetic / Logic Operation" on page iv.VERSION 0.7 (OCT 17, 2007)Modify CTR(Contrast Controller Level Selection ) in Figure 18-3 LCD Bias ControlVERSION 0.6 (MAY 02, 2007)Modify FLASH memory endurance : 1000 cycles to 100 cycles (page 1).VERSION 0.5 (APR 09, 2007)Remove P-MOS protection diode of LCD SEG or COM pin(R50~R57, R60~R67, R70~ R77) in page 13.Add R7, R4, R4IO, R4OD and R4PU registers to “Table 8-1 Control Registers”. (page 27, 28)Fix reset value of R4OD and R4PUfrom 00-0--0-B to -000000-B and 0000000-B. (page 37)Change R6IO(0CDh) to R7IO(0B4h) and add R74 ~ R75 in R7 port decribing Figure(page 38)Version 1.21Published byFAE Team©2007 ABOV Semiconductor Co., Ltd. All rights reserved.Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors.ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice.The information, diagrams and other data in this manual are correct and reliable; however, ABOV Semiconductor is in noway responsible for any violations of patents or other rights of the third party generated by the use of this manual.

MC80F7708Table of Contents1. OVERVIEW .........................................................1Description .........................................................1Features .............................................................1Development Tools ............................................3Ordering Information ........................................52. BLOCK DIAGRAM .............................................63. PIN ASSIGNMENT .............................................74. PACKAGE DIAGRAM ........................................85. PIN FUNCTION ...................................................96. PORT STRUCTURES .......................................127. ELECTRICAL CHARACTERISTICS ................15Absolute Maximum Ratings .............................15Recommended Operating Conditions ..............15DC Electrical Characteristics ...........................16LCD Characteristics .........................................17A/D Converter Characteristics .........................17AC Characteristics ...........................................18Typical Characteristics .....................................208. MEMORY ORGANIZATION .............................21Registers ..........................................................21Program Memory .............................................24Data Memory ...................................................27Addressing Mode .............................................319. I/O PORTS ........................................................35Registers for Ports ...........................................35I/O Ports Configuration ....................................3610. CLOCK GENERATOR ...................................4011. BASIC INTERVAL TIMER ..............................4212. TIMER / COUNTER ........................................448-Bit Timer/Counter Mode ................................4816 Bit Timer/Counter Mode ..............................508-Bit Capture Mode ..........................................5216-bit Capture Mode ........................................568-Bit (16-Bit) Compare Output Mode ...............57PWM Mode ......................................................5713. WATCH TIMER ...............................................6014. WATCH DOG TIMER .....................................6215. ANALOG TO DIGITAL CONVERTER ............6416. BUZZER OUTPUT FUNCTION ......................6717. INTERRUPTS .................................................69Interrupt Sequence .......................................... 72BRK Interrupt .................................................. 73Multi Interrupt .................................................. 73External Interrupt ............................................. 7518. LCD DRIVER ................................................. 76Control of LCD Driver Circuit ........................... 77LCD BIAS Control ........................................... 79LCD Display Memory ...................................... 80Control Method of LCD Driver ......................... 81Duty and Bias Selection of LCD Driver ........... 8319. UNIVERSAL ASYNCHRONOUS SERIAL IN-TERFACE ............................................................ 84Asynchronous Serial Interface Configuration .. 85Relationship between main clock and baud rate .8820. OPERATION MODE ...................................... 89Operation Mode Switching .............................. 8921. POWER DOWN OPERATION ....................... 90SLEEP Mode ................................................... 90STOP Mode .................................................... 9122. OSCILLATOR CIRCUIT ................................ 9523. RESET ........................................................... 96External Reset Input ........................................ 96Power On Reset .............................................. 97Built In Reset ................................................... 97Watchdog Timer Reset ................................... 9724. Butil In Reset (BIR) ....................................... 9825. Osillation Noise Protector ......................... 10026. FLASH PROGRAMMING SPEC. ................ 102FLASH Configuration Byte ............................ 102FLASH Programming .................................... 10227. EMULATOR EVA. BOARD SETTING ......... 10428. IN-SYSTEM PROGRAMMING ..................... 105Getting Started / Installation .......................... 105Basic ISP S/W Information ............................ 106Hardware Conditions to Enter the ISP Mode 107Sequence to enter ISP mode/user mode ...... 108Difference between auto baud rate and ACKmode ............................................................. 108Reference ISP Circuit Diagram and ABOV SuppliedISP Board ............................................. 109A. INSTRUCTION .................................................. iiDecember 3, 2012 Ver 1.21 1

MC80F7708Terminology List ................................................. iiInstruction Map ................................................. iiiInstruction Set ...................................................iv2 December 3, 2012 Ver 1.21

MC80F77081. OVERVIEW1.1 DescriptionMC80F7708CMOS SINGLE-CHIP 8-BIT MICROCONTROLLERWITH LCD CONTROLLER/DRIVERThe MC80F7708 are an advanced CMOS 8-bit microcontroller with 8K bytes of FLASH ROM(MTP). This device is one ofthe MC800 family and a powerful microcontroller which provides a high flexibility and cost effective solution to many LCDapplications. The MC80F7708 provide the following standard features: 8K bytes of FLASH ROM, 256 bytes of RAM, 20bytes of segment LCD display RAM, 8/16-bit timer/counter, 10-bit A/D converter, 7-bit watch dog timer, 21-bit watch timerwith 7-bit auto reload counter, 8-bit UART, on-chip oscillator and clock circuitry. In addition, this device supports powersaving modes to reduce power consumption. So the MC80F7708 is the best controller solution in system which uses charateredLCD display and ADC.Device nameMemory(Bytes) ADC PWM UART I/O LCDROMRAMOperatingVoltagePackageMC80F7708Q 8K 256 6ch. 1ch. 1ch. 42MC80F7708K 8K 256 4ch. 1ch. 1ch. 4016SEG x 8COM(20SEG x 4COM)16SEG x 8COM(20SEG x 4COM)2.2 ~ 5.5V 44MQFP2.2 ~ 5.5V 42SDIP1.2 Features• 8K Bytes On-chip FLASH ROM (MTP)•FLASH Memory- Endurance : 100 cycles- Data Retention : 10 years• 256 Bytes On-chip Data RAM• 20 bytes Display RAM• Instruction Cycle Time:- 333ns at 12MHz (2 cycle NOP instruction)• LCD display/controller- 1/4 Duty Mode (20Seg × 4Com, 1/3 Bias)- 1/8 Duty Mode (16Seg × 8Com, 1/4 Bias)• Four 8-bit Timer/Counter(They can be used as two 16-bit Timer/Counter)• One 7-bit Watch Dog Timer• One 21-bit Watch Timer- 1 minute interrupt available• One 8-bit Basic Interval Timer• One 6-bit Buzzer Driving Port• Dual Clock Operation- Main Clock : 400kHz ~ 12MHz- Sub Clock : 32.768kHz• Main Clock Oscillation- Crystal- Ceramic Resonator- Internal Oscillation : 8MHz/4MHz/2MHz• Operating Temperature : -40~85 °C• Built-in Noise Immunity Circuit- Noise Filter- BIR (Built-in Reset)• Power Down Mode- Main Clock : STOP, SLEEP mode• 400kHz to 12MHz Wide Operating Frequency• On-Chip POR (Power On Reset)December 3, 2012 Ver 1.21 1

MC80F7708• Internal Resistor for LCD Bias• 42/40 Programmable I/O PinsMC80F7708QMC80F7708K• 6/4-channel 10-bit On-chip A/D ConverterMC80F7708QMC80F7708KI/O: 17I : 1I/O with SEG/COM:24I/O: 15I : 1I/O with SEG/COM:246-channel ADC4-channel ADC• 14 Interrupt sources- External Interrupt : 4- Timer : 4- UART : 2- ADC, WDT, WT, BIT• One Universal Asynchronous Receiver/Transmitter(UART) at FLASH MCU• 2.2V to 5.5V Wide Operating Voltage Range• 44MQFP, 42SDIP Package Types- Available Pb free packageMC80F7708QMC80F7708K44MQFP42SDIP• One 10-bit High Speed PWM Output2 December 3, 2012 Ver 1.21

MC80F77081.3 Development ToolsThe MC80F7708 are supported by a full-featured macroassembler, an in-circuit emulator CHOICE-Dr. TM andOTP programmers. There are two different type of programmerssuch as single type and gang type. For mode detail,Macro assembler operates under the MS-Windows 95and upversioned Windows OS. And HMS800C compileronly operates under the MS-Windows 2000 and upversionedWindows OS.Please contact sales part of ABOV semiconductor.SoftwareHardware(Emulator)POD NameFLASH Writer- MS-Windows based assembler- MS-Windows based Debugger- MC800 C compiler- CHOICE-Dr.- CHOICE-Dr. EVA80F77 B/D Rev1.0- CHPOD80C77D-42SD- POD80C77D-44MQ-1010- PGM Plus USB (Single writer)- Stand Alone PGM Plus (Single writer)- Standalone GANG4/8 USB(Gang writer)- UART ISP B/DPGMplus USB (Single Writer)Stand Alone PGMplus (Single Writer)Choice-Dr. (Emulator)December 3, 2012 Ver 1.21 3

MC80F7708Stand Alone Gang4 USB (Gang Writer)UART ISP B/DStand Along Gang8 (Gang Writer)4 December 3, 2012 Ver 1.21

MC80F77081.4 Ordering InformationDevice name ROM Size RAM size PackageMC80F7708QMC80F7708K8K bytes FLASH8K bytes FLASH256 bytes256 bytes44MQFP42SDIP- Pb free package;The “P” suffix will be added at original part number.For example; MC80F7708Q(Normal package), MC80F7708Q P(Pb free package)December 3, 2012 Ver 1.21 5

MC80F77082. BLOCK DIAGRAMCommon Drive OutputCOM0 ~ COM7(COM0 ~ COM3)Segment Drive OutputSEG0 ~ SEG15(SEG0 ~ SEG19)BIAS Selection circuitInternal Resistorfor LCD BiasLCD Controller/Driver (LCDC)V DDV SSPowerSupplyPowerSupplyCircuitPSWALU Accumulator Stack PointerDataMemoryPCInterrupt ControllerLCDDisplayMemoryProgramMemoryRESETSystem controllerSystemClock Controller8-bit BasicInterval TimerData TableTiming generatorX INX OUTSX INSX OUTHigh freq.ClockLow freq.GeneratorWatch/Watch DogTimerUART08-bit A/DConverterPWM8/16-bitTimer/CounterPCPOR&BIRR7 R6 R4R5 R2R1R08 8 78 4/6 14BuzzerDriverR70R71R72R73R74R75R76R77R60R61R62R63R64R65R66R67R41/INT2R42R43R44/INT3R45R46R47R50/RX0R51/TX0R52/ACKR53R54R55R56R57R20 / AN0R21 / AN1R22 / AN2R23 / AN3R24 / AN4R25 / AN5R10 / PWM1 / T2OR01 / EC0R04 / BUZOR06 / INT0R07 / INT1*R24/AN3 and R25/AN5 are not supported in MC80F7708K(42pin).MC80F7708Q : R20/AN0 ~ R25/AN5MC80F7708K : R20/AN0 ~ R23/AN36 December 3, 2012 Ver 1.21

MC80F77083. PIN ASSIGNMENT44MQFP(Top View)R73 / SEG19 / COM4R72 / SEG18 / COM5R71 / SEG17 / COM6R70 / SEG16 / COM7R67 / SEG15R66 / SEG14R65 / SEG13R64 / SEG12R63 / SEG11R62 / SEG10R61 / SEG9R74 / COM3R75 / COM2R76 / COM1R77 / COM0R25 / AN5R24 / AN4R23 / AN3R22 / AN2R21 / AN1R20 / AN0R01 / EC034353637383940414243443332313029282726252423MC80F7708Q2221201918171615141312R60 / SEG8R57 / SEG7R56 / SEG6R55 / SEG5R54 / SEG4R53 / SEG3R52 / SEG2 / ACKR51 / SEG1 / TX0R50 / SEG0 / RX0R10 / PWM1 / T2OR07 / INT1R06 / INT0R04 / BUZOVDDVSSR41 / INT2XOUT / R42XIN / R43R44 / INT3SXIN / R45SXOUT / R46RESET / R47123456789101142SDIP(Top View)R23 / AN3R22 / AN2R21 / AN1R20 / AN0R01 / EC0R06 / INT0R04 / BUZOV DDV SSR41 / INT2X OUT / R42X IN / R43R44 / INT3SX IN / R45SX OUT / R46RESET / R47R07/INT1R10 / PWM1 / T2OR50 / SEG0 / RX0R51 / SEG1 / TX0R52 / SEG2 / ACK123456789101112131415161718192021MC80F7708K424140393837363534333231302928272625242322R77 / COM0R76 / COM1R75 / COM2R74 / COM3R73 / SEG19 / COM4R72 / SEG18 / COM5R71 / SEG17 / COM6R70 / SEG16 / COM7R67 / SEG15R66 / SEG14R65 / SEG13R64 / SEG12R63 / SEG11R62 / SEG10R61 / SEG9R60 / SEG8R57 / SEG7R56 / SEG6R55 / SEG5R54 / SEG4R53 / SEG3*R24/AN3 and R25/AN5 are not not supported in MC80F7708K(42pin).December 3, 2012 Ver 1.21 7

MC80F77084. PACKAGE DIAGRAM44MQFP13.4512.9510.109.90UNIT: MM2.101.9513.4512.9510.109.90SEE DETAIL “A”0-7°0.230.132.35 max.0.450.300.80 Typ.0.250.101.60Typ.DETAIL “A”1.030.7342SDIPUNIT: INCH1.4701.4500.190 max.min. 0.0150.600 Typ.0.5500.5300.0200.0180.0450.0350.070 Typ.0.1400.1200-15°0.0120.0088 December 3, 2012 Ver 1.21

MC80F77085. PIN FUNCTIONV DD : Supply Voltage.V SS : Circuit ground.RESET: Reset the MCU Reset.X IN : Input to the inverting oscillator amplifier and input tothe internal main clock operating circuit.X OUT : Output from the inverting oscillator amplifier.SX IN : Input to the internal sub system clock operating circuit.SX OUT : Output from the inverting subsystem oscillatoramplifier.SEG0~SEG19: Segment signal output pins for the LCDdisplay. See "18. LCD DRIVER" on page 76 for details.Also SEG0~SEG19 are shared with normal I/O ports andSEG16~19 are multiplexed with COM7~COM4.COM0~COM7: Common signal output pins for the LCDdisplay. See "18. LCD DRIVER" on page 76 for details.Also COM0~SEG7 are shared with normal I/O ports andCOM4~COM7 are multiplexed with SEG19~SEG16.COM4~COM7 and SEG19~SEG16 are selected byLCDD0 of the LCR register.LCDD001R01, R04, R06, R07: R0 is a 4-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Registercan be used as outputs or inputs. Also, pull-up resistors andopen-drain outputs can be assigned by software.In addition, R0 serves the functions of the various followingspecial features.Port pinR01R04R06R07COM4~COM7 / SEG19~SEG16COM4 ~ COM7SEG19 ~ SEG16Alternate functionEC0 (Timer 0 Event Count Input)BUZO (Buzzer Output)INT0 (External Interrupt 0 Request Input)INT1 (External Interrupt 1 Request input)R10 : R1 is an 1-bit CMOS bidirectional I/O port. R1 pins1 or 0 written to the Port Direction Register can be used asoutputs or inputs or schmitt trigger inputs. Also, pull-up resistorsand open-drain outputs can be assigned by software.In addition, R1 serves the function of the following specialfeature.Port pinR10R20~R25: R2 is a 4/6-bit CMOS bidirectional I/O port.Each pins 1 or 0 written to the Port Direction Register canbe used as outputs or inputs. Also, pull-up resistors andopen-drain outputs can be assigned by software.In addition, R2 serves the functions of the various followingspecial features.Port pinR20R21R22R23R24R25Alternate functionPWM1/T2O(Timer3 PWM Output / Timer2 Output)Note: R24/AN3 and R25/AN5 are not not supported inMC80F7708K(42pin).R41~R47: R4 is a 7-bit CMOS bidirectional I/O port. Eachpins 1 or 0 written to the Port Direction Register can beused as outputs or inputs. Also, pull-up resistors and opendrainoutputs can be assigned by software.In addition, R4 serves the functions of the various followingspecial features.Port pinR41R42R43R44R45R46R47Alternate functionAN0 (Analog Input Port0)AN1 (Analog Input Port1)AN2 (Analog Input Port2)AN3 (Analog Input Port3)AN4 (Analog Input Port4)AN5 (Analog Input Port5)Alternate functionINT2 (External Interrupt 2 Request input)X OUTX ININT3 (External Interrupt 3 Request input)SX INSX OUTRESETR50~R57: R5 is an 8-bit CMOS bidirectional I/O port orLCD segment output. Each pins 1 or 0 written to the PortDirection Register can be used as outputs or inputs. Andeach pins can also be set in segment output mode in 1-bitDecember 3, 2012 Ver 1.21 9

MC80F7708units by R5PSR Register.Port pinR50R51R52R53R54R55R56R57R60~R67: R6 is an 8-bit CMOS bidirectional I/O port orLCD segment output. Each pins 1 or 0 written to the PortDirection Register can be used as outputs or inputs. Andeach pins can also be set in segment output mode in 1-bitunits by R6PSR Register.Port pinR60R61R62R63R64R65R66R67Alternate functionSEG0 (Segment Output 0) / RX0SEG1 (Segment Output 1) / TX0SEG2 (Segment Output 2) / ACKSEG3 (Segment Output 3)SEG4 (Segment Output 4)SEG5 (Segment Output 5)SEG6 (Segment Output 6)SEG7 (Segment Output 7)Alternate functionSEG8 (Segment Output 8)SEG9 (Segment Output 9)SEG10 (Segment Output 10)SEG11 (Segment Output 11)SEG12 (Segment Output 12)SEG13 (Segment Output 13)SEG14 (Segment Output 14)SEG15 (Segment Output 15)R70~R77: R7 is a 4-bit CMOS input port or LCD segmentoutput. Each pins can be set in digital input or segment outputmode in 1-bit units by R7PSR Register.Port pinR70R71R72R73R74R75R76R77Alternate functionSEG16 (Segment Output 0) /COM7 (Common Output 7) /SEG17 (Segment Output 1) /COM6 (Common Output 6) /SEG18 (Segment Output 2) /COM5 (Common Output 5) /SEG19 (Segment Output 3) /COM4 (Common Output 4)COM3 (Common Output 3)COM2 (Common Output 2)COM1 (Common Output 1)COM0 (Common Output 0)10 December 3, 2012 Ver 1.21

MC80F7708PIN NAMEPin No.Primary FunctionSecondaryFunctionMC80F7708Q MC80F7708K I/O Description I/O DescriptionState@ ResetState@ STOPV DD 3 8 - Supply Voltage - - - -V SS 4 9 - Circuit Ground - - - -RESET / R47 11 16 I Reset (low active) - - ‘L’ input ‘H’ inputX IN /R43,X OUT /R42SX IN /R45,SX OUT /R46R53/SEG3 ~R57/SEG7R60/SEG8 ~R67/SEG15R70/SEG16/COM7 ~R73/SEG19/COM4R74/COM3 ~R77/COM07,6 12,11 I,OMain clock oscillator- - Oscillation ‘L’, ‘H’9,10 14,15 I,O Sub clock oscillator - - Oscillation17~21 22~26 I/O General I/O port O22~29 27~34 I/O General I/O port O30~33 35~38 I/O General I/O ports O34~37 39~42 I/O General I/O ports OGeneral I/O port13 18 I/O OLCD segmentoutputLCD segmentoutputLCD segmentoutputLCD commonoutputLCD commonoutputR01/EC0 44 5 I/OIEvent CounterInputR04/BUZO 2 7 I/O O Buzzer OutputR06/INT0 1 6 I/O I Interrupt InputR07/INT1 12 17 I/O I Interrupt InputR10/PWM1/T2OR20/AN0 ~R23/AN3R24/AN4 ~R25/AN543~40 4~1 I/O I39,38 - I/O IR50/SEG0/RX0 14 19 I/O General I/O portsR51/SEG1/TX0 15 20 I/O General I/O ports OR52/SEG2/ACK 16 21 I/O General I/O ports OTable 5-1 Port Function DescriptionOITimer3 PWMOutputTimer2 OutputA/D ConverterAnalog InputA/D ConverterAnalog InputLCD SegmentOutputUART0 DataInputLCD SegmentOutputUART0 DataOutputLCD SegmentOutputUART0 externalclock intputInput portState ofbeforeSTOPDecember 3, 2012 Ver 1.21 11

MC80F77086. PORT STRUCTURESR01/EC0, R06/INT0, R07/INT1, R41/IN2, R44/INT3R20/AN0~R23/AN3, R24/AN4~R25/AN5Pull upReg.Open DrainReg.Data Reg.Dir. Reg.Sub Func.Input DataSub Func.Input Enable0MUX1NoiseCancellerRDV DDV SSV DDPull-up Tr.V DDPinV SSData BusData Reg.Dir. Reg.AN0 ~ AN5Pull upReg.Open DrainReg.ADC EnableChannel Selection0MUX1RDV DDV SSPull-up Tr.PinR04/BUZO, R10/PWM1/T2OPull upReg.V DDPull-up Tr.Note: R24/AN4 and R25/AN5 are available toMC80F7708Q.V DDOpen DrainReg.V DDRESET(R47)Data BusData Reg.Sub Func.Output DataDir. Reg.0MUX1V SSV SSPinPull upReg.RDV DDPull-up Tr.Sub Func.Output Enable0MUX1RDInternal RESETIRESET Disable(Configurationoption bit)V SSPin12 December 3, 2012 Ver 1.21

MC80F7708R43 (X IN ), R42 (X OUT )X IN , X OUT (Crystal or Ceramic resonator)SX IN , SX OUTV DDMAINCLOCKPull-upReg.X OUTOpen DrainV SSReg.V DDData Reg.DirectionX INReg.STOPV SSX IN , X OUT (@RC, R)Data BusIN8MCLKV DDIN4MCLKIN2MCLKf XIN ÷ 4(‘H’ Output@STOP)IN8MCLKXOIN4MCLKXOIN2MCLKXOX OUTCLOCK option(ConfigurationV SSoption bit)IN8MCLKV DDIN4MCLKIN2MCLKV DDMain Clock(to ONP Block)STOPPull-upX INReg.Open DrainMainClockV SSReg.÷2Data Reg.DirectionReg.MUXRDV DDV SSV DDPull-upTr.V DDV SSV DDPull-upTr.V DDV SSV DDV SSX IN/ R43X OUT/ R42V DDV DDData BusMUXPOWER=V REGRDSX INSX OUTSystem Clock ÷ 4V SSDIASBLEV SSLEVELSHIFTV SSSUBCLOCKIN8MCLKXOIN4MCLKCOIN2MCLKXOCLOCK option(Configuration option bit)December 3, 2012 Ver 1.21 13

MC80F7708R53/SEG3~R57/SEG7, R60/SEG8~R67/SEG15R70/SEG16/COM7~R70/SEG19/COM4R74/COM3~R77/COM0R50/SEG0/RX0, R52/SEG2/ACKVCL3 or VCL2 or VCL1LCD DataReg.FrameCounterVCL3 or VCL2 or VCL1PinLCD DataReg.FrameCounterLCD ControlData BusLCD ControlPSRVCL0 or V SSV DDV SSPSRReg.VCL0 or V SSV SSData Reg.Data BusDir. Reg.V DD0MUX1RDV SSData Reg.Dir. Reg.R51/SEG1/TX0VCL3 or VCL2 or VCL10MUX1RDV SSLCD DataReg.FrameCounterLCD ControlSub Func.Input DataSub Func.Input EnableNoiseCancellerPSRReg.VCL0 or V SSV SSData BusV DDData Reg.0MUX1Sub Func.Output DataDir. Reg.V SSSub Func.Output Enable0MUX1RD14 December 3, 2012 Ver 1.21

MC80F77087. ELECTRICAL CHARACTERISTICS7.1 Absolute Maximum RatingsSupply voltage........................................... -0.3 to +6.0 VStorage Temperature ................................-45 to +125 °CVoltage on any pin with respect to Ground (V SS )............................................................... -0.3 to V DD +0.3Maximum current sunk by (I OL per I/O Pin) ........20 mAMaximum output current sourced by (I OH per I/O Pin)...............................................................................15 mAMaximum current (ΣI OL ) ....................................100 mAMaximum current (ΣI OH )...................................... 60 mANote: Stresses above those listed under “Absolute MaximumRatings” may cause permanent damage to the device.This is a stress rating only and functional operation ofthe device at any other conditions above those indicated inthe operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extendedperiods may affect device reliability.7.2 Recommended Operating ConditionsParameter Symbol ConditionMin.SpecificationsTyp. Max.UnitSupply Voltage V DD f MAIN =4MHz 2.2 - 5.5 VMain Operating Frequency f MAINV 1 DD =2.2~5.5V0.4 - 4.0V DD =4.5~5.5V 0.4 - 12.0MHzSub Operating Frequency f SUB V DD =V DD - 32.768 - kHzOperating Temperature T OPR -40 - 85 °C1. FLASH MCU Operating Voltage.December 3, 2012 Ver 1.21 15

MC80F77087.3 DC Electrical Characteristics(T A = -40~85°C, V DD =2.2~5.5V, V SS =0V)Parameter Symbol Pin / ConditionInput High VoltageSpecificationsMin. Typ. Max.V IH1 R0~R7 0.7V DD - V DD +0.3V IH2 RESET, X IN , SX IN , INT0~3, EC0 0.8V DD - V DD +0.3UnitVInput Low VoltageOutput High VoltageOutput Low VoltageInput HighLeakage CurrentV IL1 R0~R7 -0.3 - 0.3V DDVV IL2 RESET, X IN , SX IN , INT0~3, EC0 -0.3 - 0.2V DDV OH1 R0~R4 (V DD =4.5V, I OH1 =-1.6mA) V DD -0.3 - -V OH2 R5~R7 (V DD =4.5V, I OH2 =-1.6mA) V DD -1.0 - -V OH31SEG0~19, COM0~3(V DD =4.5V, VCL3~0=3V, I OH3 =-15μA)VCL3-0.4 - -V OL1 R0~R4 (V DD =4.5V, I OL1 =1.6mA) - - 0.35V OL2 R5~R7 (V DD =4.5V, I OL2 =1.6mA) 0.4V OL32SEG0~19, COM0~3(V DD =4.5V, VCL3~0=3V, I OL3 =15μA)I IH All input pins including R5~R7 (V IN =V DD ) - - 1Input LowLeakage CurrentI IL All input pins including R5~R7 (V IN =V ss ) -1 - -Built in Reset V BIR V DD (TRM=00) TBD TBD TBDPOR(Power onReset) LevelV POR V DD (T A =25°C) 2.1 2.4 2.7 VPOR Start Voltage 3 V START V DD (T A =25°C) 1.8 VPOR Rising Time 3 T POR V DD (T A =25°C) 40 ms/VVDD rising Time 3 T VDD V DD (T A =25°C) 40 ms/VHysteresisVT+ ~VT-RESET, INT0~3, EC0 (V DD =5V) 0.2V DD - 0.8V DD VPull-up Current I PU R0~R4 (V DD =3.0V, V PIN =0V) 20 - 60 μACurrent dissipation inactive mode 4I DD V DD ( f MAIN =8MHz, V DD= 5.5V, f SUB =0 ) - 6 15Current dissipation insleep mode 5Current dissipation instop modeInternal 8MHz OscillationFrequencyInternal 4MHz OscillationFrequencyI SLEEP V DD ( f MAIN =8MHz, V DD= 5.5V, f SUB =0 ) - 2 4I STOP f MAIN =off, V DD= 5.5V, f SUB =0 - 3 7 μAI SUB f MAIN =off, V DD= 5.5V, f SUB =32.768kHz 10 TBD uAf IN8M VDD=5V, T A =25°C TBD 8 TBD MHzf IN4M VDD=5V, T A =25°C TBD 4 TBD MHz1. V OH3 is the voltage when VCL3, VCL2, VCL1 and VCL0 are supplied at pads.2. V OL3 is the voltage when V SS is supplied at pad.3. These parameters are presented for design guidance only and not tested or guaranteed.4. Current dissipation is proportioned according to operation voltage and frequency.5. In sleep mode, oscillation continues and peripherals are operated normally but internal CPU clock stops.0.12VVμAmA16 December 3, 2012 Ver 1.21

MC80F77087.4 LCD Characteristics(T A = -40~85°C, V DD =2.2~5.5V, V SS =0V)LCD CommonOutput CurrentLCD SegmentOutput CurrentParameter Symbol ConditionSpecificationsMin. Typ. Max.I COM Output Voltage Deviation=0.2V 30 - -I SEG Output Voltage Deviation=0.2V 5 - −UnitμA7.5 A/D Converter Characteristics(TA=25°C, V DD =3.072V@f XIN =4MHz, V DD =5.12V@f XIN =8MHz, V SS =0V)Parameter Symbol Pin/ConditionSpecificationsMin. Typ. Max.Conversion Current I CON - - TBD - mAAnalog Power Supply Input Voltage Range AV 1 DD V DD 2.7 - 5.5Analog Input Voltage Range V AIN AN0 ~ AN5 V SS -0.3 - V DD +0.3VResolution N R - 10 BitInput Impedance IN[7:0] AN0 ~ AN5 1 - - MΩOverall Accuracy N ACC - - − ±3.0Non Linearity Error N NLE - - − ±3.0Differential Non Linearity Error N DNLE - - − ±3.0Zero Offset Error N ZOE - - − ±3.0Full Scale Error N FSE - - − ±3.0f XIN = 8MHz 26 - -Conversion Time T CONVf XIN = 4MHz 26 - -1. AVDD input current is measured to V DD pin when all blocks except ADC are disabled.UnitLSBμSDecember 3, 2012 Ver 1.21 17

MC80F77087.6 AC Characteristics(TA=25°C, V DD =4V, AV DD =4V, V SS =AV SS =0V)Parameter Symbol PinsSpecificationsMin. Typ. Max.Main Operating Frequency f MCP X IN 0.4 - 12 MHzSub Operating Frequency f SCP SX IN 30 32.768 35 kHzSystem Clock Frequency 1 t SYS - 166 - 5000 nSMain OscillationStabilization Time (4MHz)t MST X IN , X OUT - - 20 mSSub OscillationStabilization Timet SST SX IN , SX OUT - 1 2 SExternal Clockt MCPW X IN 35 - - nS“H” or “L” Pulse Widtht SCPW SX IN 5 - - μSExternal Clock Transition Time t RCP , t FCP X IN - - 20 nSInterrupt Pulse Width t IW INT0, INT1, INT2, IN3 2 - - t SYSRESET Input Pulse “L” Width t RST RESET 8 - - t SYSEvent Counter Input“H” or “L” Pulse WidthUnitt ECW EC0 2 - - t SYSEvent Counter Transition Time tREC, tFEC EC0 - - 20 nS1.SCMR=XXXX000X B that is f MAIN ÷218 December 3, 2012 Ver 1.21

MC80F77081/f MCPt MCPW t MCPWX IN0.1V DD0.9V DDt RCPSX IN0.1V DD0.2V DDt FCPt SYS1/f SCPt SCPW tSCPW0.9V DD0.8V DDINT0INT1t IWt IWRESETEC0t RSTt ECWTBDt ECW0.2V DD0.2V DD0.8V DDFigure 7-1 AC Timing ChartDecember 3, 2012 Ver 1.21 19

MC80F77087.7 Typical CharacteristicsThese graphs and tables are for design guidance only andare not tested or guaranteed.In some graphs or tables, the data presented are outsidespecified operating range (e.g. outside specifiedV DD range). This is for information only and devicesare guaranteed to operate properly only within thespecified range.The data is a statistical summary of data collected on unitsfrom different lots over a period of time. “Typical” representsthe mean of the distribution while “max” or “min”represents (mean + 3σ) and (mean − 3σ) respectivelywhere σ is standard deviation20 December 3, 2012 Ver 1.21

MC80F77088. MEMORY ORGANIZATION8.1 RegistersThis device has six registers that are the Program Counter(PC), a Accumulator (A), two index registers (X, Y), theStack Pointer (SP), and the Program Status Word (PSW).The Program Counter consists of 16-bit register.PCHAXYSPPCLPSWACCUMULATORX REGISTERY REGISTERSTACK POINTERPROGRAM COUNTERPROGRAM STATUSWORDThe have separate address spaces for Program memory,Data Memory and Display memory. Program memory canonly be read, not written to. It can be up to 8K bytes of Programmemory. Data memory can be read and written to upto 1024 bytes including the stack area. Display memoryhas prepared 27 nibbles for LCD.Generally, SP is automatically updated when a subroutinecall is executed or an interrupt is accepted. However, if itis used in excess of the stack area permitted by the datamemory allocating configuration, the user-processed datamay be lost.The stack can be located at any position within 100 H to15F H of the internal data memory. The SP is not initializedby hardware, requiring to write the initial value (the locationwith which the use of the stack starts) by using the initializationroutine. Normally, the initial value of “15F H” isused.Stack Address (100 H ~ 15F H )15 8 701SPFigure 8-1 Configuration of RegistersAccumulator: The Accumulator is the 8-bit general purposeregister, used for data operation such as transfer, temporarysaving, and conditional judgement, etc.The Accumulator can be used as a 16-bit register with YRegister as shown below.Hardware fixedCaution:The Stack Pointer must be initialized by software becauseits value is undefined after RESET.Example: To initialize the SPYYALDX #05FH ;TXSP;SP ← 05F HATwo 8-bit Registers can be used as a “YA” 16-bit RegisterFigure 8-2 Configuration of YA 16-bit RegisterX, Y Registers: In the addressing mode which uses theseindex registers, the register contents are added to the specifiedaddress, which becomes the actual address. Thesemodes are extremely effective for referencing subroutinetables and memory tables. The index registers also have increment,decrement, comparison and data transfer functions,and they can be used as simple accumulators.Stack Pointer: The Stack Pointer is an 8-bit register usedfor occurrence interrupts and calling out subroutines. StackPointer identifies the location in the stack to be accessed(save or restore).Program Counter: The Program Counter is a 16-bit widewhich consists of two 8-bit registers, PCH and PCL. Thiscounter indicates the address of the next instruction to beexecuted. In reset state, the program counter has reset routineaddress (PC H :0FF H , PC L :0FE H ).Program Status Word: The Program Status Word (PSW)contains several bits that reflect the current state of theCPU. The PSW is described in Figure 8-3. It contains theNegative flag, the Overflow flag, the Break flag the HalfCarry (for BCD operation), the Interrupt enable flag, theZero flag, and the Carry flag.[Carry flag C]This flag stores any carry or borrow from the ALU of CPUafter an arithmetic operation and is also changed by theShift Instruction or Rotate Instruction.December 3, 2012 Ver 1.21 21

MC80F7708[Zero flag Z]This flag is set when the result of an arithmetic operationor data transfer is “0” and is cleared by any other result.PSWMSBNLSBV G B H I Z CRESET VALUE : 00 HNEGATIVE FLAGCARRY FLAG RECEIVESCARRY OUTOVERFLOW FLAGZERO FLAGSELECT DIRECT PAGEwhen g=1, page is addressed by RPRINTERRUPT ENABLE FLAGBRK FLAGHALF CARRY FLAG RECEIVESCARRY OUT FROM BIT 1 OFADDITION OPERLANDSFigure 8-3 PSW (Program Status Word) Register[Interrupt disable flag I]This flag enables/disables all interrupts except interruptcaused by Reset or software BRK instruction. All interruptsare disabled when cleared to “0”. This flag immediatelybecomes “0” when an interrupt is served. It is set bythe EI instruction and cleared by the DI instruction.[Half carry flag H]After operation, this is set when there is a carry from bit 3of ALU or there is no borrow from bit 4 of ALU. This bitcan not be set or cleared except CLRV instruction withOverflow flag (V).[Break flag B]This flag is set by software BRK instruction to distinguishBRK from TCALL instruction with the same vector address.[Direct page flag G]This flag assigns RAM page for direct addressing mode. Inthe direct addressing mode, addressing area is from zeropage 00 H to 0FF H when this flag is "0". If it is set to "1",addressing area is assigned by RPR register (address0F3 H ). It is set by SETG instruction and cleared by CLRG.[Overflow flag V]This flag is set to “1” when an overflow occurs as the resultof an arithmetic operation involving signs. An overflowoccurs when the result of an addition or subtraction exceeds+127 (7F H ) or −128 (80 H ). The CLRV instructionclears the overflow flag. There is no set instruction. Whenthe BIT instruction is executed, bit 6 of memory is copiedto this flag.[Negative flag N]This flag is set to match the sign bit (bit 7) status of the resultof a data or arithmetic operation. When the BIT instructionis executed, bit 7 of memory is copied to this flag.22 December 3, 2012 Ver 1.21

MC80F7708At execution of aCALL/TCALL/PCALLAt acceptanceof interruptAt executionof RET instructionAt executionof RETI instruction015C015D015E015FPCLPCHPushdown015C015D015E015FPSWPCLPCHPushdown015C015D015E015FPCLPCHPopup015C015D015E015FPSWPCLPCHPopupSP beforeexecution015F015F015D015CSP afterexecution015D015C015F015FAt executionof PUSH instructionPUSH A (X,Y,PSW)At executionof POP instructionPOP A (X,Y,PSW)015C015D015E015FAPushdown015C015D015E015FAPopup0100 H015F HStackdepthSP beforeexecution015F015ESP afterexecution015E015FFigure 8-4 Stack OperationDecember 3, 2012 Ver 1.21 23

MC80F77088.2 Program MemoryA 16-bit program counter is capable of addressing up to64K bytes, but this device has 8K bytes program memoryspace only physically implemented. Accessing a locationabove FFFF H will cause a wrap-around to 0000 H .Figure 8-5 shows a map of Program Memory. After reset,the CPU begins execution from reset vector which is storedin address FFFE H and FFFF H as shown in Figure 8-6.As shown in Figure 8-5, each area is assigned a fixed locationin Program Memory. Program Memory area containsthe user program.E000 HExample: Usage of TCALLLDA #5TCALL 0FH ;1BYTE INSTRUCTION: ;INSTEAD OF 2 BYTES: ;NORMAL CALL;;TABLE CALL ROUTINE;FUNC_A: LDA LRG0RET;FUNC_B: LDARETLRG1 2 1;;TABLE CALL ADD. AREA;ORG 0FFC0H ;TCALL ADDRESS AREADW FUNC_ADW FUNC_BFEFF HFF00 HFFC0 HFFDF HFFE0 HFFFF HTCALL areaInterruptVector AreaFigure 8-5 Program Memory MapPage Call (PCALL) area contains subroutine program toreduce program byte length by using 2 bytes PCALL insteadof 3 bytes CALL instruction. If it is frequently called,it is more useful to save program byte length.Table Call (TCALL) causes the CPU to jump to eachTCALL address, where it commences the execution of theservice routine. The Table Call service area spaces 2-bytefor every TCALL: 0FFC0 H for TCALL15, 0FFC2 H forTCALL14, etc., as shown in Figure 8-7.PCALL area8K MTPThe interrupt causes the CPU to jump to specific location,where it commences the execution of the service routine.The External interrupt 0, for example, is assigned to location0FFFA H . The interrupt service locations spaces 2-byteinterval: 0FFF8 H and 0FFF9 H for External Interrupt 1,0FFFA H and 0FFFB H for External Interrupt 0, etc.Any area from 0FF00 H to 0FFFF H , if it is not going to beused, its service location is available as general purposeProgram Memory.Address0FFE0 HE2E4E6E8EAECEEF0F2F4F6F8FAFCFEVector Area MemoryWatch Timer interrupt Vector AreaWatch dog timer interrupt VectorBasic Interval Timer Interrupt Vector AreaAD Converter Interrupt Vector Area-Timer/Counter 3 Interrupt Vector AreaTimer/Counter 2 Interrupt Vector AreaTimer/Counter 1 Interrupt Vector AreaTimer/Counter 0 Interrupt Vector Area-UART TX0 Interrupt Vector AreaUART RX0 Interrupt Vector AreaExternal Interrupt 3 Vector AreaExternal Interrupt 2 Vector AreaExternal Interrupt 1 Vector AreaExternal Interrupt 0 Vector Area-Reset Interrupt Vector AreaFigure 8-6 Interrupt Vector Area24 December 3, 2012 Ver 1.21

MC80F7708AddressProgram Memory0FFC0 HC1TCALL 15Address0FF00 H0FFFF HPCALL Area MemoryPCALL Area(256 Bytes)C2C3C4C5C6C7C8C9CACBCCCDCECFD0D1D2D3D4D5D6D7D8D9DADBDCDDDEDFTCALL 14TCALL 13TCALL 12TCALL 11TCALL 10TCALL 9TCALL 8TCALL 7TCALL 6TCALL 5TCALL 4TCALL 3TCALL 2TCALL 1TCALL 0 / BRK *NOTE:* means that the BRK software interrupt is usingsame address with TCALL0.Figure 8-7 PCALL and TCALL Memory AreaPCALL→ relTCALL→ n4F35 PCALL 35 H 4A TCALL 44F4A35~ ~~ ~01001010Reverse11111111 11010110PC:0FFFF H 0FFD6 H 250D125 H NEXTF H F H D H 6 H0FF00 H0FF35 H NEXT0FF00 H320FFD7 H D110FFFF HDecember 3, 2012 Ver 1.21 25

MC80F7708Example: The usage software example of Vector address and the initialize part.ORG0FFE0H; Device : MC807708DW WT_INT ; Watch Timer / Watch Dog TimerDW BIT_INT; Basic Interval TimerDW AD_Con; AD converterDW NOT_USED; Not UsedDW TMR3_INT ; Timer-3DW TMR2_INT; Timer-2DW TMR1_INT; Timer-1DW TMR0_INT; Timer-0DW NOT_USED; Not UsedDW UART0_INT; UART TX0, RX0DW EX3_INT; INT.3DW EX2_INT; INT.2DW EX1_INT; Int.1DW EX0_INT; Int.0DW NOT_USED; Not usedDW RESET; Reset;********************************************; MAIN PROGRAM *;********************************************ORG0E000HRESET: DI ;Disable All InterruptsCLRGLDX #0LDA #0RAM_CLR1:STA {X}+;Page0 RAM Clear(!0000 H ->!009F H )CMPX #0A0HBNE RAM_CLR1LDM RPR,#0000_0001B;Page1 RAM Clear(!0100 H ->!00FF H )SETGLDX #0LDA #0RAM_CLR2:STA {X}+CMPX #060HBNE RAM_CLR2CLRGLDX #05FH;Stack Pointer InitializeTXSPLDMRPR,#0000_0000B;Page0 selectionCALL LCD_CLR;Clear LCD display memoryLDM R0, #0;Normal Port 0LDM R0IO,#1000_0010B;Normal Port DirectionLDM R0PU,#1000_0010B;Pull Up Selection SetLDM R0OD,#0000_0001B;R0 port Open Drain control::LDM SCMR,#1111_0000B;System clock control::26 December 3, 2012 Ver 1.21

MC80F77088.3 Data MemoryFigure 8-8 shows the internal Data Memory space available.Data Memory is divided into four groups, a user RAM,control registers, Stack, and LCD memory.0000 HUSER MEMORY(160 Bytes)PAGE0009F H00A0 HPERIPHERAL CONTROLREGISTERS00FF H0100 H USER MEMORY(Including Stack Area) PAGE1(96 Bytes )RPR (RAM Page Selection Register)MSB---RPR[2:0] (RAM Page Selection)--ADDRESS: 0CF HINITIAL VALUE: ----_-001 BLSBR/W R/W R/WRPR2 RPR1 RPR0RPR2 RPR1 RPR0 RAM Page Selection0 0 0 PAGE 00 0 1 PAGE 10 1 0 -0 1 1 -015F HPage 0Unimplemented0460 HLCD DISPLAY MEMORY(20 Bytes)0473 HPAGE41 0 0 PAGE 41 0 1 -1 1 0 -1 1 1 -Caution1 : After setting RPR, be sure to execute SETG instruction.Caution2 : When executing CLRG instruction,be selected PAGE0 regardless of RPR.Figure 8-10 RAM Page Selection RegisterFigure 8-8 Data Memory MapUser MemoryThe MC80F7708 have 256 × 8 bits for the user data memory(RAM). There are three pages internal RAM. Page isselected by G-flag and RAM page selection register RPR.When G-flag is cleared to “0”, always page 0 is selected regardlessof RPR value. If G-flag is set to “1”, page will beselected according to RPR value.RPR=0, G=0Page 1RPR=1, G=1RPR=4, G=1Page 0: 000 H ~09F HPage 1: 100 H ~15F H--Page 4: 460 H ~473 HPage 4Figure 8-9 RAM page configurationControl RegistersThe control registers are used by the CPU and Peripheralfunction blocks for controlling the desired operation of thedevice. Therefore these registers contain control and statusbits for the interrupt system, the timer/counters, analog todigital converters and I/O ports. The control registers are inaddress range of 0A0 H to 0FF H .Note that unoccupied addresses may not be implementedon the chip. Read accesses to these addresses will in generalreturn random data, and write accesses will have an indeterminateeffect.More detailed informations of each register are explainedin each peripheral section.Note: Write only registers can not be accessed by bit manipulationinstruction. Do not use read-modify-write instruction.Use byte manipulation instruction.Example; To write at CKCTLRLDM CKCTLR,#05H ;Divide ratio ÷8Stack AreaThe stack provides the area where the return address issaved before a jump is performed during the processingDecember 3, 2012 Ver 1.21 27

MC80F7708routine at the execution of a subroutine call instruction orthe acceptance of an interrupt.When returning from the processing routine, executing thesubroutine return instruction [RET] restores the contents ofthe program counter from the stack; executing the interruptreturn instruction [RETI] restores the contents of the programcounter and flags.The save/restore locations in the stack are determined bythe stack pointer (SP). The SP is automatically decreasedafter the saving, and increased before the restoring. Thismeans the value of the SP indicates the stack locationnumber for the next save. Refer to Figure 8-4 on page 23.LCD Display MemoryLCD display data area is handled in LCD section.See "18.3 LCD Display Memory" on page 80.Address Register Name Symbol R/WInitial Value7 6 5 4 3 2 1 0AddressingMode00A0H R0 Open Drain Control Register R0OD W 0 0 - 0 - - 0 - byte 100A1H R1 Open Drain Control Register R1OD W - - - - - - - 0 byte00A2H R2Open Drain Control Register R2OD W - -000000 byte00A4H R4Open Drain Control Register R4OD W - 0 0 0 0 0 0 - byte00A5H R0 Pull-up Register R0PU W 0 0 - 0 0 0 0 - byte00A6H R1 Pull-up Register R1PU W - - - - - - - 0 byte00A7H R2 Pull-up Register R2PU W - -000000 byte00A9H R4 Pull-up Register R2PU W 0000000- byte00AAH Port Selection Register 0 PSR0 W 0 0 - 0 0 0 0 - byte00ABH Port Selection Register 1 PSR1 W - - - - - - - 0 byte00ACH R5 Port Selection Register R5PSR R / W 11111111 byte, bit 200ADH R6 Port Selection Register R6PSR R / W 11111111 byte, bit00AEH R7 Port Selection Register R7PSR R / W 11111111 byte, bit00B0H R7 Data Register R7 R / W 00000000 byte00B2H LCD Control Register LCR R / W 00000000 byte, bit00B3H LCD BIAS Control Register LBCR R / W 01111000 byte, bit00B4H R7 Direction Register R7IO W 00000000 byte00B8H Asynchronous Serial Mode Register0 ASIMR0 R / W 0000-00- byte, bit00B9H Asynchronous Serial Status Register0 ASISR0 R - - - - - 0 0 0 byte00BAH Baud Rate Generator Control Register0 BRGCR0 R / W -0010000 byte, bit00BBHReceive Buffer Register0 RXBR0 R 00000000 byteTransmit Shift Register0 TXSR0 W 11111111 byte00C0H R0 port data register R0 R / W 0 0 - 0 - - 0 - byte, bit00C1H R0 Direction Register R0IO W 0 0 - 0 - - 0 - byte00C2H R1 port data register R1 R / W - - - - - - - 0 byte, bit00C3H R1 Direction Register R1IO W - - - - - - - 0 byte00C4H R2 port data register R2 R / W - -000000 byte, bit00C5H R2 Direction Register R2IO W - -000000 byte00C8H R4 port data register R2 R / W - 0 0 0 0 0 0 - byte, bitTable 8-1 Control Registers28 December 3, 2012 Ver 1.21

MC80F7708Address Register Name Symbol R/W00C9H R4 Direction Register R4IO W - 0 0 0 0 0 0 - byte00CAH R5 port data register R5 R/W 00000000 byte, bit00CBH R5 Direction Register R5IO W 00000000 byte00CCH R6 port data register R6 R/W 00000000 byte, bit00CDH R6 Direction Register R6IO W 00000000 byte00CEH Buzzer Driver Register BUZR W 11111111 byte00CFH Ram Page Selection Register RPR R / W - - - - - 0 0 1 byte, bit00D0H Timer 0 Mode Control Register TM0 R / W - -000000 byte, bitTimer 0 Register T0 R 00000000 byte00D1H Timer 0 Data Register TDR0 W 11111111 byteTimer 0 Capture Data Register CDR0 R 00000000 byte00D2 Timer 1 Mode Control Register TM1 R / W 00-00000 byte, bit00D3H Timer 1 Data Register TDR1 W 11111111 byteTimer 1 Register T1 R 00000000 byte00D4HTimer 1 Capture Data Register CDR1 R 00000000 byte00D6H Timer 2 Mode Control Register TM2 R / W - -000000 byte, bitTimer 2 Register T2 R 00000000 byte00D7H Timer 2 Data Register TDR2 W 11111111 byteTimer 2 Capture data Register CDR2 R 00000000 byte00D8H Timer 3 Mode Control Register TM3 R / W 00000000 byte, bit00D9HInitial Value7 6 5 4 3 2 1 0AddressingModeTimer 3 Data Register TDR3 W 11111111 byteTimer 3 PWM Period Register T3PPR W 11111111 byteTimer 3 Register T3 R 00000000 byte00DAH Timer 3 PWM Duty Register T3PDR R / W 00000000 byte, bitTimer 3 Capture Data Register CDR3 R 00000000 byte00DBH Timer 3 PWM High Register T3PWHR W - - - - 0000 byte00E2H 10bit A/D Converter Mode Control Register ADCM 3 R / W 00000001 byte, bit00E3H 10bit A/D Converter Result Register Low ADCRL R Undefined byte00E4H 10bit A/D Converter Result Register High ADCRH W, R 0 1 0 - - - X X byte, bit00E5H BIR Control Register BIRR R / W 00000000 byte, bitBasic Interval Timer Register BITR R Undefined byte00E6HClock Control Register CKCTLR W - -010111 byte00E7H System Clock Mode Register SCMR R / W - - - - - 0 0 0 byteWatch Dog Timer Register WDTR W 01111111 byte00E8H Watch Dog Timer Data Register WDTDR R Undefined byteWatch Timer Register WTR W 01111111 byte00E9H Stop & Sleep Mode Control Register SSCR W 00000000 byteTable 8-1 Control RegistersDecember 3, 2012 Ver 1.21 29

MC80F7708Address Register Name Symbol R/WInitial Value7 6 5 4 3 2 1 0AddressingMode00EAH Watch Timer Mode Register WTMR R / W 00- -0000 byte, bit00F4H Interrupt Generation Flag Register High INTFH R / W - - - - 0 0 - - byte, bit00F5H Interrupt Generation Flag Register Low INTFL R / W - - - - - - 0 0 byte, bit00F6H Interrupt Enable Register High IENH R / W - 0 0 0 0 0 - - byte, bit00F7H Interrupt Enable Register Middle IENM R / W 0000- - -0 byte, bit00F8H Interrupt Enable Register Low IENL R / W - 0 0 0 0 - - - byte, bit00F9H Interrupt Request Register High IRQH R / W - 0 0 0 0 0 - - byte, bit00FAH Interrupt Request Register Middle IRQM R / W 0000- - -0 byte, bit00FBH Interrupt Request Register Low IRQL R / W - 0 0 0 0 - - - byte, bit00FCH Interrupt Edge Selection Register IEDS R / W 00000000 byte, bitTable 8-1 Control Registers1. “byte”, “bit” means that register can be addressed by not only bit but byte manipulation instruction.2. “byte” means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-writeinstruction such as bit manipulation.3. bit 0 of ADCM is read only.30 December 3, 2012 Ver 1.21

MC80F77088.4 Addressing Mode2The MC80F7708 use six addressing modes;(3) Direct Page Addressing → dpExample: G=1, RPR=01 H0F035 H data2E45535 LDM 35 H ,#55 H• Register addressing• Immediate addressingIn this mode, a address is specified within direct page.Example; G=0• Direct page addressingC535 LDA 35 H ;A ←RAM[35 H ]• Absolute addressing• Indexed addressing35• Register-indirect addressingH data(1) Register Addressing0E550 H C5~ ~ 1data → ARegister addressing accesses the A, X, Y, C and PSW.(2) Immediate Addressing → #immIn this mode, second byte (operand) is accessed as a dataimmediately.0E551 H 35Example:(4) Absolute Addressing → !abs0435 ADC #35 HAbsolute addressing sets corresponding memory data toData, i.e. second byte (Operand I) of command becomeslower level address and third byte (Operand II) becomesMEMORYupper level address.With 3 bytes command, it is possible to access to whole04memory area.A+35 H +C → A35ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX,LDY, OR, SBC, STA, STX, STYExample;0735F0 ADC !0F035 H ;A ←ROM[0F035 H ]When G-flag is 1, then RAM address is defined by 16-bitaddress which is composed of 8-bit RAM paging register(RPR) and 8-bit immediate data.datadata ← 55 H0F100 H~ ~070F101 H 350F102 H F01A+data+C → Aaddress: 0F0350135 H10F100 H E40F101 H 550F102 H 35~ ~December 3, 2012 Ver 1.21 31

MC80F7708The operation within data memory (RAM)ASL, BIT, DEC, INC, LSR, ROL, RORExample; Addressing accesses the address 0135 H regardlessof G-flag and RPR.981501 INC !0115 H ;A ←ROM[115 H ]X indexed direct page, auto increment→ {X}+In this mode, a address is specified within direct page bythe X register and the content of X is increased by 1.LDA, STAExample; G=0, X=35 HDB LDA {X}+data115 H980F101 H 150F102 H 010F100 H~ ~23data+1 → data1address: 011535 H datadata → A~ ~DB1236H → X(5) Indexed AddressingX indexed direct page (no offset) → {X}In this mode, a address is specified by the X register.ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMAExample; X=15 H , G=1, RPR=01 HD4 LDA {X} ;ACC←RAM[X].X indexed direct page (8 bit offset) → dp+XThis address value is the second byte (Operand) of commandplus the data of X-register. And it assigns the memoryin Direct page.ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STASTY, XMA, ASL, DEC, INC, LSR, ROL, RORExample; G=0, X=0F5 HC645 LDA 45 H +X115 Hdata20E550 H~ ~D41data → A3A H data0E550 H~ ~ 21C60E551 H 4545 H +0F5 H =13A H3data → A32 December 3, 2012 Ver 1.21

MC80F7708Y indexed direct page (8 bit offset) → dp+YThis address value is the second byte (Operand) of commandplus the data of Y-register, which assigns Memory inDirect page.This is same with above. Use Y register instead of X.Y indexed absolute → !abs+YSets the value of 16-bit absolute address plus Y-registerdata as Memory. This addressing mode can specify memoryin whole area.3F35 JMP [35 H ]35 H 0A36 H E32 jump to address 0E30A H~ ~0E30A H NEXT~ ~ 13FExample; Y=55 HD500FA LDA !0FA00 H +Y0FA00 H350F100 H D510F101 H 000F102 H FA0FA00 H +55 H =0FA55 H0FA55 H~ ~data32data → AX indexed indirect → [dp+X]Processes memory data as Data, assigned by 16-bit pairmemory which is determined by pair data[dp+X+1][dp+X] Operand plus X-register data in Directpage.ADC, AND, CMP, EOR, LDA, OR, SBC, STAExample; G=0, X=10 H1625 ADC [25 H +X](6) Indirect AddressingDirect page indirect → [dp]Assigns data address to use for accomplishing commandwhich sets memory data (or pair memory) by Operand.Also index can be used with Index register X,Y.JMP, CALLExample; G=035 H 0536 H E0~~0E005 H data~~162 0E005 H125 + X(10) = 35 H0FA00 H253A + data + C → ADecember 3, 2012 Ver 1.21 33

MC80F7708Y indexed indirect → [dp]+YProcesses memory data as Data, assigned by the data[dp+1][dp] of 16-bit pair memory paired by Operand in Directpage plus Y-register data.ADC, AND, CMP, EOR, LDA, OR, SBC, STAExample; G=0, Y=10 H1725 ADC [25 H ]+YAbsolute indirect → [!abs]The program jumps to address specified by 16-bit absoluteaddress.JMPExample; G=01F25E0 JMP [!0E025 H ]PROGRAM MEMORY25 H0E005 H + Y(10) = 0E015 H05E0~ ~20E025 H 25E7~ ~2jump toaddress 0E725 H0E015 Hdata110E725 HNEXT~ ~~ ~0FA00 H26 H170E026 H250FA00 H1F253A + data + C → AE034 December 3, 2012 Ver 1.21

MC80F77089. I/O PORTSThe MC80F7708 have seven I/O ports, LCD segment ports(R0, R1, R2, R4, R50/SEG0/RX0 ~ R73/SEG19/COM4)and LCD common ports (R77/COM0 ~ R74/COM3, R73/SEG19/COM4 ~ R70/SEG16/COM7).These ports pins may be multiplexed with an alternatefunction for the peripheral features on the device.9.1 Registers for PortsPort Data RegistersThe Port Data Registers are represented as a D-Type flipflop,which will clock in a value from the internal bus in responseto a “write to data register” signal from the CPU.The Q output of the flip-flop is placed on the internal busin response to a “read data register” signal from the CPU.The level of the port pin itself is placed on the internal busin response to “read data register” signal from the CPU.Some instructions that read a port activating the “read register”signal, and others activating the “read pin” signal.Port Direction RegistersAll pins have data direction registers which can definethese ports as output or input. A “1” in the port directionregister configure the corresponding port pin as output.Conversely, write “0” to the corresponding bit to specify itas input pin. For example, to use the even numbered bit ofR0 as output ports and the odd numbered bits as inputports, write “55 H ” to address 0C1 H (R0 port direction register)during initial setting as shown in Figure 9-1.All the port direction registers in the MC80F7708 have 0written to them by reset function. Therefore, its initial statusis input.pull-up port. It is connected or disconnected by Pull-upControl register (RnPU). The value of that resistor is typically100kΩ. Refer to DC characteristics for more details.When a port is used as key input, input logic is firmly eitherlow or high, therefore external pull-down or pull-upresisters are required practically. The MC80F7708 haveinternal pull-up, it can be logic high by pull-up that can beable to configure either connect or disconnect individuallyby pull-up control registers RnPU.When ports are configured as inputs and pull-up resistor isselected by software, they are pulled to high.VDDGNDVDDPULL-UP RESISTORPORT PINPull-up control bit0: Disconnect1: ConnectWRITE “55 H ” TO PORT R0 DIRECTION REGISTER0C0 H R0 DATA0 1 0 1 0 1 0 10C1 H0CC H0CD HR0 DIRECTIONR6 DATAR7 DIRECTION7I76O65-54O43-32-21I10-0~ ~I : INPUT PORTO : OUTPUT PORTBITPORTFigure 9-2 Pull-up Port StructureOpen drain port RegistersThe R0, R1, R2 and R4 ports have open drain port resistorsR0OD~R4OD.Figure 9-3 shows an open drain port configuration by controlregister. It is selected as either push-pull port or opendrainport by R0OD, R1OD, R2OD and R4OD.PORT PINFigure 9-1 Example of port I/O assignmentGNDOpen drain port selection bit0: Push-pull1: Open drainPull-up Control RegistersThe R0, R1, R2 and R4 ports have internal pull-up resistors.Figure 9-2 shows a functional diagram of a typicalFigure 9-3 Open-drain Port StructureDecember 3, 2012 Ver 1.21 35

MC80F77089.2 I/O Ports ConfigurationR0 PortR0 is a 4-bit CMOS bidirectional I/O port (address 0C0 H ).Each I/O pin can independently used as an input or an outputthrough the R0IO register (address 0C1 H ).R0 has internal pull-ups that is independently connected ordisconnected by R0PU. The control registers for R0 areshown below.In addition, Port R0 is multiplexed with various specialfeatures. The control register PSR0 (address 0AA H ) controlsthe selection of alternate function. After reset, thisvalue is “0”, port may be used as normal I/O port.To use alternate function such as External Interrupt ratherthan normal I/O, write “1” in the corresponding bit ofPSR0.Port PinR01--R04R06R07Alternate FunctionEC0 (Timer0 Event Input)TX0 (TX0 Output)RX0 (RX0 Input)BUZO (Buzzer Output)INT0 (External Interrupt 0)INT1 (External Interrupt 1)Note: R0IO, R0PU, P0OD and PSR0 are write-only registers.They can not be read and can not be accessed by bitmanipulation instruction. Do not use read or read-modifywriteinstruction. Use byte manipulation instruction.R0 Data RegisterR0ADDRESS : 0C0 HRESET VALUE : 00-0--0- BR07 R06 - R04 - - R01 -R0 Direction RegisterR0IOR0 Pull-upSelection RegisterR0PUR0 Open DrainSelection RegisterR0ODPortSelection Register 0PSR0ADDRESS : 0C1 HRESET VALUE : 00-0--0- B- - - -Port Direction0: Input1: OutputADDRESS :0A5 HRESET VALUE : 00-0--0- B- - --Pull-up select0: Without pull-up1: With pull-upADDRESS :0A0 HRESET VALUE : 00-0--0- B- - - -Open Drain select0: No Open Drain1: Open DrainADDRESS :0AA HRESET VALUE : 00-0000- BINT1I INT0I - BUZO RX0I TX0O EC0I -R1 PortsR1 is an 1-bit CMOS bidirectional I/O port (address0C2 H ). Each I/O pin can independently used as an input oran output through the R1IO register (address 0C3 H ).R1 has internal pull-up that is independently connected ordisconnected by register R1PU. The control registers forR1 are shown below.Port R1 is multiplexed with two special features. The controlregister controls the selection of alternate function. Afterreset, this value is “0”, port may be used as normal I/Oport. The way to select alternate function such as PWM1or Timer Output Wave will be shown in each peripheralsection.Note: R1IO, R1PU, P1OD and PSR1 are write-only registers.They can not be read and can not be accessed by bitmanipulation instruction. Do not use read or read-modifywriteinstruction. Use byte manipulation instruction.INT1I (External Interrupt 1)0: R07 Port1: INT1BUZO (Buzzer Output)0: R04 Port1: BUZOTX0O (TX0 Output)0: -1: TX0INT0I (External Interrupt 0)0: R06 Port1: INT0RX0I (RX0 Input)0: -1: RX0EC0I (Timer0 Event Input)0: R01 Port1: EC036 December 3, 2012 Ver 1.21

MC80F7708R1 Data RegisterR1R1 Direction RegisterR1IOR1 Pull-upSelection RegisterR1PUR1 Open DrainSelection RegisterR1ODPortSelection Register 1PSR1- - - -- - - -- - - -- - - -- - - -INT2I (External Interrupt 2)0: R41 Port1: INT2INT3I (External Interrupt 3)0: R44 Port1: INT3ADDRESS : 0C2 HRESET VALUE : -------0 B- - -ADDRESS : 0C3 HRESET VALUE : -------0 B- - -Port Direction0: Input1: OutputR10ADDRESS : 0A6 HRESET VALUE : -------0 B- - -Pull-up select0: Without pull-up1: With pull-upADDRESS :0A1 HRESET VALUE : -------0 B- - -Open Drain select0: No Open Drain1: Open DrainADDRESS :0AB HRESET VALUE : -----000 B- INT3I INT2I PWM1OPWM1O (PWM1 Output)0: R10 Port1: PWM1/T2OR2 PortsR2 is a 6-bit CMOS bidirectional I/O port (address 0C4 H ).Each I/O pin can independently used as an input or an outputthrough the R2IO register (address 0C5 H ).R2 has internal pull-ups that are independently connectedor disconnected by R2PU (address 0A7 H ). The control registersfor R2 are shown as below.Note: R2IO, R2PU and P2OD are write-only registers.They can not be read and can not be accessed by bit manipulationinstruction. Do not use read or read-modify-writeinstruction. Use byte manipulation instruction.Note: The R24 and R25 are not supported in theMC80F7708K.R2 Data RegisterR2R2 Direction RegisterR2IOR2 Pull-upSelection RegisterR2PUR2 Open DrainSelection RegisterR2ODA/D ConverterMode RegisterADCM- -- -- -- --ADDRESS: 0C4 HRESET VALUE: --000000 BR25 R24 R23 R22 R21 R20ADDRESS : 0C5 HRESET VALUE : --000000 BPort Direction0: Input1: OutputADDRESS : 0A7 HRESET VALUE : --000000 BPull-up select0: Without pull-up1: With pull-upADDRESS : 0A2 HRESET VALUE : --000000 BOpen Drain select0: No Open Drain1: Open DrainADDRESS : 0E2 HRESET VALUE : -0-00001 BADEN ADS3 ADS2 ADS1 ADS0 ADST ADFAnalog input of A/Dconverter is selectedby ADS0~ADS2R4 PortR4 is a 7-bit CMOS bidirectional I/O port (address 0C8 H ).Each I/O pin can independently used as an input or an outputthrough the R4IO register (address 0C9 H ).R4 has internal pull-ups that is independently connected ordisconnected by R4PU. The control registers for R4 areshown below.December 3, 2012 Ver 1.21 37

MC80F7708R4 Data RegisterR4ADDRESS : 0C8 HRESET VALUE : -000000- BR47 R46 R45 R44 R43 R42 R41 -R4 Direction RegisterR4IOR4 Pull-upSelection RegisterR4PUR4 Open DrainSelection RegisterR0ODADDRESS : 0C9 HRESET VALUE : -000000- BPort Direction0: Input1: OutputADDRESS :0A9 HRESET VALUE : 0000000- BPull-up select0: Without pull-up1: With pull-upADDRESS :0A4 HRESET VALUE : -000000- B- -Open Drain select0: No Open Drain1: Open DrainPortSelection Register 1PSR1LCR-ADDRESS :0AB HRESET VALUE : -----000 B- - - - - INT3I INT2IINT2I (External Interrupt 2)0: R41Port1: INT2INT3I (External Interrupt 3)0: R41Port1: INT3LCD Control RegisterPWM1O (PWM1 Output)0: R10 Port1: PWM1/T2OIn addition, Port R4 is multiplexed with oscillation input/output, reset and interrupt input pins. The control registerPSR1 (address 0AB H ) controls the selection of alternatefunction. After reset, this value is “0”, port may be used asnormal I/O port. To use alternate function such as ExternalInterrupt rather than normal I/O, write “1” in the correspondingbit of PSR1.Main oscillation input/output and reset pin can be used asnormal I/O ports (R43/R42) and normal input port(R47) byselecting configuration options in flash writing. Sub oscillationinput/output pin can be used as normal I/O ports bywriting “1” to the SCKD bit of the LCR register--PWM1OADDRESS :0B2 HRESET VALUE : 00000000 BSCKD 1 LCDEN 0 1 LCDD0 LCK1SCKD (Sub Clock Disable)0: Sub Clock Oscillation Eaable (SXIN/SXOUT)1: Sub Clock Oscillation Disable (R45/R46)LCK0Port PinR41R42R43R44R45R46R47Alternate FunctionINT2 (External Interrupt 2)X OUT (Oscillation Output)X IN (Oscillation Input)INT3 (External Interrupt 3)SX IN (Subsystem Oscillation Input)SX OUT (Subsystem Oscillation Output)RESET (System Reset Input)Note: R4IO, R4PU, P4OD and PSR1 are write-only registers.They can not be read and can not be accessed by bitmanipulation instruction. Do not use read or read-modifywriteinstruction. Use byte manipulation instruction.R5 PortsR5 is an 8-bit CMOS bidirectional I/O port (address0CA H ). Each I/O pin can independently used as an input oran output through the R5IO register (address 0CB H ).R5 is multiplexed with LCD segment output(SEG0 ~SEG7), which can be selected by writing appropriate valueinto the R5PSR(address 0AC H ).R50, R1, R52 is also multiplxed with RX0, TX0 and ACK,which can be selected by writing appropriate value into theASIMR0(address 0B8 H ).R5 Data RegisterR5R5 Direction RegisterR5IOADDRESS: 0CA HRESET VALUE: 00000000 BR57 R56 R55 R54 R53 R52 R51 R50R5/LCD PortSelection RegisterR5PSRADDRESS : 0CB HRESET VALUE : 00000000 BPort Direction0: Input1: OutputADDRESS : 0AC HRESET VALUE : 11111111 BR5PS7 R5PS6 R5PS5 R5PS4 R5PS3 R5PS2 R5PS1 R5PS00: Seg Selection(seg7~seg0)1: Port SelectionNote: R5IO is write-only register. It can not be read andcan not be accessed by bit manipulation instruction. Do notuse read or read-modify-write instruction. Use byte manipulationinstruction.38 December 3, 2012 Ver 1.21

MC80F7708R6 PortsR6 is an 8-bit CMOS bidirectional I/O port (address0CC H ). Each I/O pin can independently used as an input oran output through the R6IO register (address 0CD H ).R6 is multiplexed with LCD segment output(SEG8 ~SEG15), which can be selected by writing appropriate valueinto the R6PSR(address 0AD H ).R7 is multiplexed with LCD common output (COM7 ~COM0) and segment output(SEG16 ~ SEG19), which canbe selected by writing appropriate value into theR7PSR(address 0AE H ) and LCR(address 0B2 H ).R7 Data RegisterR7ADDRESS: 0B0 HRESET VALUE: 00000000 BR77 R76 R75 R74 R73 R72 R71 R70R6 Data RegisterR6ADDRESS: 0CC HRESET VALUE: 00000000 BR67 R66 R65 R64 R63 R62 R61 R60R7 Direction RegisterR7IOADDRESS : 0B4 HRESET VALUE : 00000000 BR6 Direction RegisterR6IOR6/LCD PortSelection RegisterR6PSR0: Seg Selection(seg15~seg8)1: Port SelectionADDRESS : 0CD HRESET VALUE : 00000000 BPort Direction0: Input1: OutputADDRESS : 0AD HRESET VALUE : 11111111 BR6PS7 R6PS6 R6PS5 R6PS4 R6PS3 R6PS2 R6PS1 R6PS0Note: R6IO is write-only register. It can not be read andcan not be accessed by bit manipulation instruction. Do notuse read or read-modify-write instruction. Use byte manipulationinstruction.R7 PortsR7 is a 4-bit CMOS bidirectional I/O port (address 0B0 H ).Each I/O pin can independently used as an input or an outputthrough the R7IO register (address 0B4 H ).R7/LCD PortSelection RegisterR7PSRPort Direction0: Input1: OutputADDRESS : 0AE HRESET VALUE : 11111111 BR7PS7 R7PS6 R7PS5 R7PS4 R7PS3 R7PS2 R7PS1 R7PS00: Seg or COM Selection(seg16~seg19, COM7 ~ COM0)1: Port SelectionNote: R7IO is write-only register. It can not be read andcan not be accessed by bit manipulation instruction. Do notuse read or read-modify-write instruction. Use byte manipulationinstruction.SEG0~SEG19Segment signal output pins for the LCD display. See "18.LCD DRIVER" on page 76 for details.COM0~COM7Common signal output pins for the LCD display. See "18.LCD DRIVER" on page 76 for details.SEG16~SEG19 and COM7~COM4 are selected by LCDDof the LCR register.December 3, 2012 Ver 1.21 39

MC80F770810. CLOCK GENERATORAs shown in Figure 10-1, the clock generator produces thebasic clock pulses which provide the system clock to besupplied to the CPU and the peripheral hardware. It containstwo oscillators which are main-frequency clock oscillatorand a sub-frequency clock oscillator.The systemclock can also be obtained from the external oscillator.By setting configuration option, the internal 8MHz, 4MHz,2MHz can also be selected for system clock source.The clock generator produces the system clocks formingclock pulse, which are supplied to the CPU and the peripheralhardware.The internal system clock should be selected to main oscillationby setting bit1 and bit0 of the system clock moderegister (SCMR). The registers are shown in Figure 10-2.To the peripheral block, the clock among the not-dividedoriginal clocks, divided by 2, 4,..., up to 4096 can be provided.Peripheral clock is enabled or disabled by STOP instruction.The peripheral clock is controlled by clockcontrol register (CKCTLR). See "11. BASIC INTERVALTIMER" on page 42 for details.CS[1:0]X INOSCCIRCUIT01CLK[2:0](configuration option)Internal8MHzSYSTEM CLOCKGENERATORInternal System ClockInternal4MHzPRESCALERInternal2MHzPS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10PS11PS12÷1÷2 ÷4 ÷8 ÷16 ÷32 ÷64 ÷128 ÷256 ÷512 ÷1024÷2048 ÷4096Peripheral clockf MAIN (Hz) PS0 PS1 PS2 PS3PS4PS5 PS6 PS7PS8PS9PS10PS11PS124MFrequencyperiod4M 2M 1M 500K 250K 125K 62.5K 31.25K 15.63K 7.183K 3.906K250n 500n 1u 2u 4u 8u 16u 32u 64u 128u 256u1.953K 976512u 1.024mFigure 10-1 Block Diagram of Clock Generator40 December 3, 2012 Ver 1.21

MC80F7708The SCMR should be set to operate by main oscillation.Bit2, bit1 and bit0 of the SCMR should be set to “000” or“001” to select main oscillation.SCMR (System Clock Mode Register)MSBLSBR/W R/W R/WMCC CS1 CS0ADDRESS: 0E7 HINITIAL VALUE: -----000 BCS[1:0] (System clock selection)00: main clock01: main clock10: reserved11: Setting prohibitedMCC (Main Clock Oscillation Control)0: main clock oscillation possible1: main clock oscillation stoppedSCMR should be set to “-----000 B ” or “-----0001 B ”Figure 10-2 SCMR : System Clock Mode RegisterDecember 3, 2012 Ver 1.21 41

MC80F770811. BASIC INTERVAL TIMERThe MC80F7708 have one 8-bit Basic Interval Timer thatis free-run and can not stop. Block diagram is shown inFigure 11-1.The Basic Interval Timer Register (BITR) is increased everyinternal count pulse which is divided by prescaler.Since prescaler has division ratio from 8 to 1024, the countrate is 1/8 to 1/1024 of the oscillator frequency. After reset,the BCK bits are all set, so the longest oscillation stabilizationtime is obtained.It also provides a Basic interval timer interrupt (BITF).The count overflow of BITR from FF H to 00 H causes theinterrupt to be generated. The Basic Interval Timer is controlledby the clock control register (CKCTLR) shown inFigure 11-2.Source clock can be selected by lower 3 bits of CKCTLR.When write “1” to bit BCL of CKCTLR, BITR register iscleared to “0” and restart to count up. The bit BCL becomes“0” automatically after one machine cycle by hardware.BITR and CKCTLR are located at same address, and address0E6 H is read as a BITR, and written to CKCTLR.f SUBf MAIN ÷2 3f MAIN ÷2 4f MAIN ÷2 5f MAIN ÷2f MAIN ÷2 7f MAIN ÷2 8f MAIN ÷2 9f MAIN ÷2 10MUXsourceclock8-bit up-counter1BITR0[0E6 H ]SELSUB clearoverflowBITIFBasic Interval Timer InterruptSelect Input clock 3BCKf MAIN : main-clock frequencyf SUB : sub-clock frequency [0E6 H ]Basic Interval Timerclock control registerCKCTLRBCLInternal bus lineFigure 11-1 Block Diagram of Basic Interval TimerBCK000001010011100101110111Source clockSCMR[1:0] = 00 or 01Interrupt (overflow) PeriodAt f MAIN = 4MHzf MAIN ÷2 30.512 msf MAIN ÷2 41.024f MAIN ÷2 52.048f MAIN ÷2 64.096f MAIN ÷2 78.192f MAIN ÷2 816.384f MAIN ÷2 932.768f MAIN ÷2 10 65.536Table 11-1 Basic Interval Timer Interrupt Time42 December 3, 2012 Ver 1.21

MC80F7708CKCTLR7 6 5 4 3 2 1 0- - SELSUB WDTON BCL BCK2 BCK1 BCK0ADDRESS: 0E6 HINITIAL VALUE: --010111 BCaution:SUB Clock Selection0 : Deselect Sub Clock1 : Select Sub ClockWatch Dog Timer Enable0 : Operates as a 7-bit Timer1 : Enable Watchdog TimerBoth register are in same address,when write, to be a CKCTLR,when read, to be a BITR.Basic Interval Timer source clock select000: f MAIN ÷2 3001: f MAIN ÷2 4010: f MAIN ÷2 5f MAIN : main-clock frequency011: f MAIN ÷2 6100: f MAIN ÷2 7101: f MAIN ÷2 8110: f MAIN ÷2 9111: f MAIN ÷2 10Clear bit0: Normal operation (free-run)1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automaticallyafter one machine cycle.BITR7 6 5 4 3 2 1 08-BIT BINARY COUNTERADDRESS: 0E6 HINITIAL VALUE: 00 HExample 1:Interrupt request flag is generated every 8.192ms at 4MHz.:LDM CKCTLR,#0CHSET1 BITEEI:Figure 11-2 BITR: Basic Interval Timer Mode RegisterDecember 3, 2012 Ver 1.21 43

MC80F770812. TIMER / COUNTERTimer/Event Counter consists of prescaler, multiplexer, 8-bit timer data register, 8-bit counter register, mode register,input capture register and Comparator as shown in Figure12-4. And the PWM high register for PWM is consistedseparately.The timer/counter has seven operating modes.- 8 Bit Timer/Counter Mode- 8 Bit Capture Mode- 8 Bit Compare Output Mode- 16 Bit Timer/Counter Mode- 16 Bit Capture Mode- 16 Bit Compare Output Mode- PWM ModeIn the “timer” function, the register is increased every internalclock input. Thus, one can think of it as counting internalclock input. Since a least clock consists of 2 andmost clock consists of 2048 oscillator periods, the countrate is 1/2 to 1/2048 of the oscillator frequency in Timer0.And Timer1 can use the same clock source too. In addition,Timer1 has more fast clock source (1/1 to 1/8).In the “counter” function, the register is increased in responseto a 0-to-1 (rising edge) transition at its correspondingexternal input pin EC0 (Timer 0).In addition the “capture” function, the register is increasedin response external or internal clock interrupt same withtimer/counter function. When external interrupt edge input,the count register is captured into capture data registerTMx.Timer3 is shared with “PWM” function and Timer2 isshared with “Compare output” function.Example 1:Example 3:LDM IEDS,#XXXX_XX01BSET1 T0ELDM PSR0,#X1XX_XXXXB ;AS INT0EI:::SET1 T0E ;ENABLE TIMER 0SET1 INT0E ;ENABLE EXT. INT0EI:Timer 0 = 8-bit timer mode, 8ms interval at 4MHzTimer 1 = 8-bit timer mode, 4ms interval at 4MHzTimer0 = 8-bit event counterTimer2 = 8-bit capture mode, 2us sampling count.LDM SCMR,#0 ;Main clock modeLDM TDR0,#249LDM TDR0,#0FFH ;don’t careLDM TM0,#0001_0011BLDM TM0,#1FH ;event counterLDM TDR1,#124LDM R0IO,#1XXX_XX1XB ;R07, R01 inputLDM TM1,#0000_1111BLDM IEDS,#XXXX_01XXB ;FALLINGSET1 T0ELDM PSR0,#1XXX_XX1XB;INT1,EC0SET1 T1ELDM TDR2,#0FFHEILDM TM2,#0010_1011B ;2us:::SET1 T0E ;ENABLE TIMER 0SET1 T2E ;ENABLE TIMER 1SET1 INT1E;ENABLE INT1EI:X: don’t care.Example 2:Timer0 = 16-bit timer mode, 0.5s at 4MHzExample 4:Timer0 = 16-bit capture mode, 8us sampling count. at 4MHzLDM SCMR,#0 ;Main clock modeLDM TDR0,#23HLDM TDR0,#0FFHLDM TDR1,#0F4HLDM TDR1,#0FFHLDM TM0,#0FH ;F MAIN /32, 8usLDM TM0,#2FHLDM TM1,#5FHLDM TM1,#4CHX: don’t care.44 December 3, 2012 Ver 1.21

MC80F7708TM0, TM2 (Timer0, 2 Mode Control Register)TM0TM2R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0STR/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0- - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2STADDRESS: 0D0 H )INITIAL VALUE:--000000 BADDRESS: 0D6 HINITIAL VALUE:--000000 BCAP0,CAP2 (Capture Mode Selection Bit)0: Timer/Counter Mode1: Capture ModeT0CN,T2CN (Timer 0,2 Continue Start)0: Pause Counting1: Continue CountingT0ST,T2ST (Timer 0,2 Start Control)0: Stop Counting1: Clear the counter and Start counting againT0CK[2:0],T2CK[2:0] (Timer 0,2 Input Clock Selection)T0CK[2:0]T2CK[2:0]000: f MAIN ÷2000: f MAIN ÷2001: f MAIN ÷2 2001: f MAIN ÷2 2010: f MAIN ÷2 3010: f MAIN ÷2 4011: f MAIN ÷2 5011: f MAIN ÷2 6100: f MAIN ÷2 7100: f MAIN ÷2 8101: f MAIN ÷2 9101: f MAIN ÷2 10110: f MAIN ÷2 11110: f MAIN ÷2 12111: External Event clock EC0 111: Reservedf MAIN : main-clock frequencyTM1, TM3 (Timer1, 3 Mode Control Register)TM1TM3R/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0- 16BIT - - T1CK1 T1CK0 T1CN T1STR/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0POL 16BIT PWM1E - T3CK1 T3CK0 T3CN T3STADDRESS: 0D2 HINITIAL VALUE:-0--0000 BADDRESS: 0D8 HINITIAL VALUE:000-0000 BPOL (PWM Output Polarity Selection)0: Duty Active Low1: Duty Active High16BIT (16 Bit Mode Selection)0: 8-Bit Mode1: 16-Bit ModePWM1E (PWM Enable Bit)0: PWM1 Disable (T2O Enable)1: PWM1 Enable (T2O Disable)T1CK[1:0],T3CK[1:0] (Timer 1,3 Input Clock Selection)T1CK[1:0]00: f MAIN01: f MAIN ÷210: f MAIN ÷2 311: Timer0 ClockT3CK[1:0]00: f MAIN01: f MAIN ÷210: f MAIN ÷2 411: Timer2 ClockT1CN,T3CN (Timer 1,3 Continue Start)0: Stop Counting1: Start CountingT1ST,T3ST (Timer 1,3 Start Control)0: Stop counting1: Clear the counter and start count again**The counter will be cleared and restarted only when the TxST bit cleared and set again.If TxST bit set again when TxST bit is set, the counter can’t be cleared but only start again.T0CK2 T0CK1 T0CK0 4MHz 8MHz 10MHz0 0 0 (f MAIN ÷2) 500nS 250nS 200nS0 0 1 (f MAIN ÷2 2 ) 1uS 500nS 400nS0 1 0 (f MAIN ÷2 3 ) 2uS 1uS 800nS0 1 1 (f MAIN ÷2 5 ) 8uS 4uS 3.2uS1 0 0 (f MAIN ÷2 7 ) 32uS 16uS 12.8uS1 0 1 (f MAIN ÷2 9 ) 128uS 64uS 51.2uS1 1 0 (f MAIN ÷2 11 ) 512uS 256uS 204.8uSFigure 12-1 Timer0,1,2,3 RegistersDecember 3, 2012 Ver 1.21 45

MC80F7708T0 (Timer0 Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0T07 T06 T05 T04 T03 T02 T01 T00ADDRESS: 0D1 HINITIAL VALUE:00HCDR0 (Timer0 Input Capture Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00ADDRESS: 0D1 HINITIAL VALUE:00HIn Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.TDR0 (Timer 0 Data Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0TDR07 TDR06 TDR05 TDR04 TDR03 TDR02 TDR01 TDR00If the counter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.T1 (Timer1 Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0T17 T16 T15 T14 T13 T12 T11 T10ADDRESS: 0D1 HINITIAL VALUE:FF HADDRESS: 0D4 HINITIAL VALUE:00HCDR1 (Timer1 Input Capture Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10ADDRESS: 0D4 HINITIAL VALUE:00 HIn Timer mode, this register is the value of Timer 1 counter and in Capture mode, this register is the value of input capture.TDR1 (Timer1 Data Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10If the counter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.ADDRESS: 0D3 HINITIAL VALUE:FF HFigure 12-2 Related Registers with Timer/Counter0, 146 December 3, 2012 Ver 1.21

MC80F7708T2 (Timer2 Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0T27 T26 T25 T24 T23 T22 T21 T20ADDRESS: 0D7 HINITIAL VALUE:00HCDR2 (Timer2 Input Capture Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0CDR27 CDR26 CDR25 CDR24 CDR23 CDR22 CDR21 CDR20ADDRESS: 0D7 HINITIAL VALUE:00HIn Timer mode, this register is the value of Timer 2 counter and in Capture mode, this register is the value of input capture.TDR2 (Timer2 Data Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0TDR27 TDR26 TDR25 TDR24 TDR23 TDR22 TDR21 TDR20If the counter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.TDR3 (Timer3 Data Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0TDR37 TDR36 TDR35 TDR34 TDR33 TDR32 TDR31 TDR30If the counter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.T3PPR (Timer3 PWM Period Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0PWM1PR7 PWM1PR6 PWM1PR5 PWM1PR4 PWM1PR3 PWM1PR2 PWM1PR1 PWM1PR0The period is decided by PWM.T3 (Timer3 Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0T37 T36 T35 T34 T33 T32 T31 T30T3PDR (Timer3 PWM Duty Register)W/R W/R W/R W/R W/R W/R W/R W/RBit : 7 6 5 4 3 2 1 0PWM1DR7 PWM1DR6 PWM1DR5 PWM1DR4 PWM1DR3 PWM1DR2 PWM1DR1 PWM1DR0In PWM mode, decide the pulse duty.ADDRESS: 0D7 HINITIAL VALUE:FF HADDRESS: 0D9 HINITIAL VALUE:FF HADDRESS: 0D9 HINITIAL VALUE:FF HADDRESS: 0DA HINITIAL VALUE:00HADDRESS: 0DA HINITIAL VALUE:00 HCDR3 (Timer3 Input Capture Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0CDR37 CDR36 CDR35 CDR34 CDR33 CDR32 CDR31 CDR30ADDRESS: 0DA HINITIAL VALUE:00HIn Timer mode, this register is the value of Timer 2 counter and in Capture mode, this register is the value of input capture.T3PWHR (Timer3 High Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0- - - - PWM1HR3 PWM1HR2 PWM1HR1 PWM1HR0ADDRESS: 0DB HINITIAL VALUE:----00000 BFigure 12-3 Related Registers with Timer/Counter2, 3December 3, 2012 Ver 1.21 47

MC80F770816BIT CAP0 - T0CK[2:0] T1CK[1:0] Timer 0 Timer 10 0 - XXX XX 8 Bit Timer 8 Bit Timer0 0 - 111 XX 8 Bit Event Counter 8 Bit Timer0 1 - XXX XX 8 Bit Capture 8 Bit Compare Output1 0 - XXX 11 16 Bit Timer1 0 - 111 11 16 Bit Event Counter1 1 - XXX 11 16 Bit Capture1 0 - XXX 11 16 Bit Compare OutputTable 12-1 Operating Modes of Timer 0 and Timer 112.1 8-Bit Timer/Counter ModeThe MC80F7708 have four 8-bit Timer/Counters, Timer0,Timer1, Timer2 and Timer3 as shown in Figure 12-4.The “timer” or “counter” function is selected by mode registersTMx (x=0,1,2,3) as shown in Figure 12-1 and Table12-1. To use as an 8-bit timer/counter mode, bit CAPx ofTMx is cleared to “0” and bits 16BIT of TM1(3) should becleared to “0” (Table 12-1 ).TM0Bit : 7 6 5 4 3 2 1 0- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST0 X X X X XADDRESS : 0D0 HRESET VALUE : --000000 BTM1- 16BIT - CAP1 T1CK1 T1CK0 T1CN T1STX 0 0 0 X X X XADDRESS : 0D2 HRESET VALUE : -0-00000 BX : The value “0” or “1” corresponding your operation.EC0X IN0X1X2SCMR[1:0]Edge DetectorTM0÷2÷2 2÷2 3÷2 5÷2 7÷2 9÷2 11TM1÷1÷2÷2 3T0CK[2:0]MUXT1CK[1:0]MUX1T0CN1T1CNT0ST0 : Stop1 : Clear and StartT0 (8-bit)TDR0 (8-bit)T1 (8-bit)TDR1 (8-bit)CLEARCOMPARATORT1ST0 : Stop1 : Clear and StartCLEARCOMPARATORT1IFT0IFTIMER 0INTERRUPTTIMER 1INTERRUPTFigure 12-4 Block Diagram of Timer/Event Counter0,148 December 3, 2012 Ver 1.21

MC80F7708TM2Bit : 7 6 5 4 3 2 1 0- - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST0 X X X X XADDRESS : 0D6 HRESET VALUE : --000000 BX INTM30X1X2SCMR[1:0]POL 16BIT PWM1E - T3CK1 T3CK0 T3CN T3STX 0 0 X X X XADDRESS : 0D8 HRESET VALUE : 000-0000 BX : The value “0” or “1” corresponding your operation.T2CK[2:0]T2ST0 : StopReserved1 : Clear and Start1CLEARMUXT2 (8-bit)TM2÷2÷2 2T2IFTIMER 2INTERRUPT÷2 4T2CNCOMPARATOR÷2 6TDR2 (8-bit)÷2 8PWM1ER1FUNC.0F/FPWM1/T2O or R10÷2 10 T3CK[1:0]T3ST÷2 12 0 : StopT2O1 : Clear and Start0MUX1TM3CLEAR1MUXT3 (8-bit)PWM1(R10/PWM1/T2O)÷1÷2÷2 4T3CNTDR3 (8-bit)COMPARATORT3IFTIMER 3INTERRUPTFigure 12-5 Block Diagram of Timer 2,3These timers have each 8-bit count register and data register.The count register is increased by every internal or externalclock input. The internal clock has a prescaler divideratio option of 2, 4, 8, 32,128, 512, 2048 (selected by controlbits TxCK2, TxCK1 and TxCK0 of register TM0(2))and 1, 2, 8 (selected by control bits TxCK1 and TxCK0 ofregister TM1(3)).In the Timer, timer register Tx increases from 00 H until itmatches TxDR and then reset to 00 H . If the value of Tx isequal with TxDR, Timer x interrupt is occurred (latched inTxIF bit). TxDR and T0 register are in same address, sothis register is read from T0 and written to TDR0.In counter function, the counter is increased every 0-to 1(rising edge) transition of EC0 pin. In order to use counterfunction, the bit R01 of the R0 Direction Register (R0IO)should be set to “0” and the bit EC0E of Port SelectionRegister PSR0 should set to “1”. The Timer 0 can be usedas a counter by pin EC0 input, but other timers can not usedas a event counter.Note: The contents of TDR0, TDR1, TDR2 and TDR3must be initialized (by software) with the value between1 H and 0FF H , not 0 H .December 3, 2012 Ver 1.21 49

MC80F7708T0,1,2,3TDR0,TDR1,TDR2,TDR3nn-19876543210Interrupt period= P CP x (n+1)Timer 0,1,2,3 (T0IF,T1IF,T2IF,T3IF)InterruptOccur interrupt Occur interrupt Occur interrupt~up-count~P CP~TIMEFigure 12-6 Counting Example of Timer Data RegistersT0,1,2,3TDR0,TDR1,TDR2,TDR3disableenable~stopclear & start~up-countTIMETimer 0 (T0IF)InterruptT(0~3)STStart & StopT(0~3)CNControl countOccur interruptT(0~3)ST = 0 T(0~3)ST = 1Occur interruptT(0~3)CN = 0 T(0~3)CN = 1Figure 12-7 Timer Count Operation12.2 16 Bit Timer/Counter ModeThe Timer register is running with 16 bits. A 16-bit timer/counter register T0, T1 are increased from 0000 H until itmatches TDR0, TDR1 and then resets to 0000 H . Thematch output generates Timer 0 interrupt not Timer 1 interrupt.The clock source of the Timer 0 is selected either internalor external clock by bit T0CK2, T0CK1 and T0CK0.In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM150 December 3, 2012 Ver 1.21

MC80F7708should be set to “1” respectively.TM0TM1Bit : 7 6 5 4 3 2 1 0- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST0 X X X X X- 16BIT - - T1CK1 T1CK0 T1CN T1STX 1 0 0 1 1 X XADDRESS : 0D0 HRESET VALUE : --000000 BADDRESS : 0D2 HRESET VALUE : -0--0000 BX : The value “0” or “1” corresponding your operation.Edge DetectorT0CK[2:0]T0ST0 : Stop1 : Clear and StartEC0X IN0X1X2SCMR[1:0]TM0÷2÷2 2÷2 3÷2 5÷2 7÷2 9÷2 11MUX1T0CNT1 (8-bit)TDR1 (8-bit)T0 (8-bit)COMPARATORTDR0 (8-bit)CLEART0IFTIMER 0INTERRUPTFigure 12-8 16-bit Timer / Counter Mode 0TM2TM3Bit : 7 6 5 4 3 2 1 0- - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST0 X X X X XPOL 16BIT PWM1E - T3CK1 T3CK0 T3CN T3STX 1 0 0 1 1 X XADDRESS : 0D6 HRESET VALUE : --000000 BADDRESS : 0D8 HRESET VALUE : 000-0000 BX : The value “0” or “1” corresponding your operation.T2CK[2:0]T2ST0 : Stop1 : Clear and StartX IN0X1X2SCMR[1:0]ReservedTM2÷2÷2 2÷2 4÷2 6÷2 8÷2 10÷2 12MUX1T2CNT3 (8-bit)TDR3 (8-bit)T2 (8-bit)COMPARATORTDR2 (8-bit)CLEART0(2)IFF/F 0MUX1PWM1PWM1ETIMER 2INTERRUPT(R10/PWM1/T2O)PWM1O[R1FUNC.0]Figure 12-9 16-bit Timer / Counter Mode 2December 3, 2012 Ver 1.21 51

MC80F770812.3 8-Bit Capture ModeThe Timer 0 capture mode is set by bit CAP0 of timermode register TM0 (bit CAPx of timer mode register TMxfor Timer 1,2,3) as shown in Figure 12-10.As mentioned above, not only Timer 0 but Timer 1,2,3 canalso be used as a capture mode.The Timer/Counter register is increased in response internalor external input. This counting function is same withnormal timer mode, and Timer interrupt is generated whentimer register T0 (T1,2,3) increases and matches TDR0(TDR1,TDR2,TDR3).This timer interrupt in capture mode is very useful whenthe pulse width of captured signal is more wider than themaximum period of Timer.For example, in Figure 12-13, the pulse width of capturedsignal is wider than the timer data value (FF H ) over 2times. When external interrupt is occurred, the capturedvalue (13 H ) is more little than wanted value. It can be obtainedcorrect value by counting the number of timer overflowoccurrence.Timer/Counter still does the above, but with the added featurethat a edge transition at external input INTx pin causesthe current value in the Timer x register (T0,T1,T2,T3), tobe captured into registers CDRx (x=0,1,2,3), respectively.After captured, Timer x register is cleared and restarts byhardware.It has three transition modes: “falling edge”, “rising edge”,“both edge” which are selected by interrupt edge selectionregister IEDS (Refer to External interrupt section). In addition,the transition at INTx pin generate an interrupt.Note: The CDR0, TDR0 and T0 are in same address. Inthe capture mode, reading operation is to read theCDR0 and in timer mode, reading operation is readthe T0. TDR0 is only for writing operation.The CDR1, T1 are in same address, the TDR1 is locatedin different address. In the capture mode,reading operation is to read the CDR152 December 3, 2012 Ver 1.21

MC80F7708TM0Bit : 7 6 5 4 3 2 1 0- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST1 X X X X XADDRESS : 0D0 HRESET VALUE : --000000 BTM1- 16BIT - CAP1 T1CK1 T1CK0 T1CN T1STX 0 0 1 X X X XADDRESS : 0D2 HRESET VALUE : -0--0000 BEdge DetectorT0CK[2:0]T0ST0 : Stop1 : Clear and StartEC0X IN0X1X2SCMR[1:0]TM0÷2÷2 2÷2 3÷2 5÷2 7÷2 9÷2 11MUX1T0CNCAPTURECDR0 (8-bit)T0 (8-bit)TDR0 (8-bit)CLEARCOMPARATORT0IFTIMER 0INTERRUPTT1ST0 : Stop1 : Clear and StartTM1÷1÷2÷2 3MUXT1CK[1:0]1T1CNT1 (8-bit)CLEARCOMPARATORT1IFTIMER 1INTERRUPTCAPTURECDR1(8-bit)TDR1 (8-bit)INT 0INTERRUPTINT0INT0IFIEDS[1:0]Figure 12-10 8-bit Capture Mode (Timer0, Timer1)December 3, 2012 Ver 1.21 53

MC80F7708TM2Bit : 7 6 5 4 3 2 1 0- - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST1 X X X X XADDRESS : 0D6 HRESET VALUE : --000000 BTM3POL 16BIT PWM1E CAP3 T3CK1 T3CK0 T3CN T3STX 0 0 1 X X X XADDRESS : 0D8 HRESET VALUE : 000-0000 BT2CK[2:0]T2ST0 : Stop1 : Clear and StartX IN0X1X2SCMR[1:0]ReservedTM2÷2÷2 2÷2 4÷2 6÷2 8÷2 10÷2 12MUX1T2CNCAPTURECDR2 (8-bit)T2 (8-bit)TDR2 (8-bit)CLEARCOMPARATORT2IFTIMER 2INTERRUPTT3ST0 : Stop1 : Clear and StartTM3÷1÷2÷2 4MUXT3CK[1:0]1T3CNT3 (8-bit)CLEARCOMPARATORT3IFTIMER 3INTERRUPTCAPTURECDR3 (8-bit)TDR3 (8-bit)INT1INT1IFINT 1INTERRUPTIEDS[3:2]Figure 12-11 8-bit Capture Mode (Timer2, Timer3)54 December 3, 2012 Ver 1.21

MC80F7708T0,1,2,3nn-1This value is loaded to CDR0(1,2,3)~102up-count5436789~~TIMEExt. INT0(1,2,3) PinInterrupt Request(INT0F,INT1F)20ns5nsInterrupt Interval PeriodExt. INT0 PinInterrupt Request(INT0IF)20nsCapture(Timer Stop)5nsDelayClear & StartFigure 12-12 Input Capture OperationExt. INT0 PinInterrupt Request(INT0IF)Interrupt Interval Period =01 H + FF H + 01 H + FF H +01 H + 13 H = 214 HInterrupt Request(T0IF)FF HFFHT013 H00 H 00HFigure 12-13 Excess Timer Overflow in Capture ModeDecember 3, 2012 Ver 1.21 55

MC80F770812.4 16-bit Capture Mode16-bit capture mode is the same as 8-bit capture, exceptthat the Timer register is running with 16 bits.The clock source of the Timer 0,2 is selected either internalor external clock by bit TxCK2, TxCK1 and TxCK0.In 16-bit mode, the bits TxCK1,TxCK0 and 16BIT ofTM1,TM3 should be set to “1” respectively.TM0Bit : 7 6 5 4 3 2 1 0- - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST1 X X X X XADDRESS : 0D0 HRESET VALUE : --000000 BTM1- 16BIT - CAP1 T1CK1 T1CK0 T1CN T1STX 1 0 1 1 1 X XADDRESS : 0D2 HRESET VALUE : -0-00000 BX : The value “0” or “1” corresponding your operation.X INEC0INT00X1X2SCMR[1:0]Edge DetectorTM0÷2÷2 2÷2 3÷2 5÷2 7÷2 9÷2 11T0CK[2:0]MUX1T0CNT0ST0 : Stop1 : Clear and StartT0 + T1 (16-bit)CAPTURE CDR1 CDR0 TDR1 TDR0(8-bit) (8-bit) (8-bit) (8-bit)CLEARCOMPARATORT0IFTIMER 0INTERRUPTINT0 IF INT 0INTERRUPTIEDS[1:0]Figure 12-14 16-bit Capture Mode (Timer0,1)56 December 3, 2012 Ver 1.21

MC80F7708TM2Bit : 7 6 5 4 3 2 1 0- - CAP2 T2CK2 T2CK1 T2CK0 T2CN T2ST1 X X X X XADDRESS : 0D6 HRESET VALUE : --000000 BTM3POL 16BIT PWM1E - T1CK1 T1CK0 T1CN T1STX 1 0 X 1 1 X XADDRESS : 0D8 HRESET VALUE : 000-0000 BX : The value “0” or “1” corresponding your operation.T2CK[2:0]T2ST0 : Stop1 : Clear and StartX ININT10X1X2SCMR[1:0]ReservedTM0 , TM2÷2 , ÷2÷2 2 , ÷2 2÷2 3 , ÷2 4÷2 5 , ÷2 6÷2 7 , ÷2 8÷2 9 , ÷2 10÷2 11 , ÷2 12MUX1T2CNT2 + T3 (16-bit)CAPTURE CDR3 CDR2 TDR3 TDR2(8-bit) (8-bit) (8-bit) (8-bit)CLEARCOMPARATORT2IFTIMER 2INTERRUPTINT1 IF INT 1INTERRUPTIEDS[3:2]Figure 12-15 16-bit Capture Mode (Timer2,3)12.5 8-Bit (16-Bit) Compare Output ModeThe MC80F7708 have a function of Timer Compare Output.To pulse out, the timer match can goes to port pin(R10) as shown in Figure 12-4 and Figure 12-8. Thus,pulse out is generated by the timer match. These operationis implemented to pin, R10/PWM1/T2O.In this mode, the bit PWM1O of Port Mode RegisterR1FUNC should be set to “1”, and the bit PWM1E ofTimer3 Mode Register (TM3) should be cleared to “0”.12.6 PWM ModeThe MC80F7708 has one high speed PWM (Pulse WidthModulation) function which shared with Timer3. In PWMmode, the R10/PWM1 pins operate as a 10-bit resolutionPWM output port. For this mode, the bit PWM1O of PortMode Register (R1FUNC) and the bit PWM1E of timer3mode register (TM3) should be set to “1” respectively.The period of the PWM output is determined by theT3PPR (T3 PWM Period Register) and T3PWHR[3:2](bit3, 2 of T3 PWM High Register) and the duty of thePWM output is determined by the T3PDR (T3 PWM DutyIn addition, 16-bit Compare output mode is available, also.This pin output the signal having a 50: 50 duty squarewave, and output frequency is same as below equationff XINCOMP = --------------------------------------------------------------------------------------------2 × PrescalerValue × ( TDR + 1)Register) and T3PWHR[1:0] (bit1, 0 of T3PWM HighRegister).The user can use PWM data by writing the lower 8-bit periodvalue to the T3PPR and the higher 2-bit period valueto the T3PWHR[3:2]. And the duty value can be used withthe T3PDR and the T3PWHR[1:0] in the same way.The T3PDR is configured as a double buffering for glitchlessPWM output. In Figure 12-16, the duty data is transferredfrom the master to the slave when the period datamatched to the counted value. (i.e. at the beginning of nextDecember 3, 2012 Ver 1.21 57

MC80F7708duty cycle).The bit POL1 of TM3 decides the polarity of duty cycle.The duty value can be changed when the PWM outputs.However the changed duty value is output after the currentperiod is over. And it can be maintained the duty value atpresent output when changed only period value shown asFigure 12-18. As it were, the absolute duty time is notchanged in varying frequency.Note: If the user need to change mode from the Timer3mode to the PWM mode, the Timer3 should bestopped firstly, and then set period and duty registervalue. If user writes register values and changesmode to PWM mode while Timer3 is in operation,the PWM data would be different from expecteddata in the beginning.The relation of frequency and resolution is in inverse proportion.Table 12-2 shows the relation of PWM frequencyvs. resolution.PWM Period = [T3PWHR[3:2]T3PPR+1] X Source ClockPWM Duty = [T3PWHR[1:0]T3PDR+1] X Source ClockIf it needed more higher frequency of PWM, it should bereduced resolution.Note: If the duty value and the period value are same, thePWM output is determined by the bit POL1 (1: High,0: Low). And if the duty value is set to “00 H ”, thePWM output is determined by the bit POL1(1: Low,0: High). The period value must be same or morethan the duty value, and 00 H cannot be used as theperiod value.ResolutionT3CK[1:0]=00 (250nS)FrequencyT3CK[1:0]=01 (500nS)T3CK[1:0]=10 (2uS)10-bit 3.9kHz 1.95kHz 0.49kHz9-bit 7.8kHz 3.9kHz 0.98kHz8-bit 15.6kHz 7.8kHz 1.95kHz7-bit 31.2kHz 15.6kHz 3.90kHzTable 12-2 PWM Frequency vs. Resolution at 4MHzTM3Bit : 7 6 5 4 3 2 1 0POL 16BIT PWM1E - T3CK1 T3CK0 T3CN T3STX 0 1 0 X X X XADDRESS : 0D8 HRESET VALUE : 00 HT3PWHRADDRESS : 0DB H- - - - PWM1HR3PWM1HR2 PWM1HR1PWM1HR0 RESET VALUE : ----0000 BX X X X Bit Manipulation Not AvailablePeriod High Duty HighX : The value “0” or “1” corresponding your operation.T3PWHR[3:2]X INPWM1ET3STT3PPR (8-bit)T0 clock source 0 : StopCOMPARATORT2O1 : Clear and Start0 R10/PWM1/T2OMUXS Q1CLEAR1RMUXT3 (8-bit)PWM1O÷1, ÷10X[PSR1.0]÷2, ÷21XCOMPARATORPOL÷2 3 , ÷2 4 T3CN2T3CK[1:0]SCMR[1:0]Slave T3PDR (8-bit)T3PWHR[1:0]MasterT3PDR (8-bit)Figure 12-16 PWM Mode58 December 3, 2012 Ver 1.21

MC80F7708~~f MAINT1~ ~00 01 02 03 04 7F 80 81 3FF 00 01 02~ ~PWMPOL=1PWMPOL=0~~Duty Cycle [(80 H +1) x 200nS = 25.8uS]Period Cycle [(1+3FF H ) x 200nS = 204.8uS]~~T3CK[1:0] = 00 (200nS)T3PWHR = 0C HT3PPR = FF HT3PDR = 80 HPeriodDutyPWM1HR3 PWM1HR2T3PPR (8-bit)1 1 FF HPWM1HR1 PWM1HR0T3PDR (8-bit)0 0 80 HFigure 12-17 Example of PWM at 5MHzT3CK[1:0] = 10 (1.6uS)T3PWHR = 00 HT3PPR = 0E HT3PDR = 05 HWrite T1PPR to 0A HPeriod changedSourceclockT100 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03 04PWMPOL=1Duty Cycle[(05 H +1) x 1.6uS = 9.6uS]Duty Cycle[(05 H +1) x 1.6uS = 9.6uS]Duty Cycle[(05 H +1) x 1.6uS = 9.6uS]Period Cycle [(0E H +1) x 1.6uS = 24uS]Period Cycle [(0A H +1) x 1.6uS = 17.6uS]Figure 12-18 Example of Changing the Period in Absolute Duty Cycle (@5MHz)Example:Timer1 @4Mhz, 4kHz - 20% duty PWM modeLDM R1IO,#0000_XXX1B ;R00 outputLDM TM3,#0010_0000B ;pwm enableLDM T3PWHR,#0000_1100B ;20% dutyLDM T3PPR,#1110_0111B ;period 250uSLDM T3PDR,#1100_0111B ;duty 50uSLDM PSR1,#XXXX_XXX1B ;set pwm port.LDM TM3,#0010_0011B ;timer1 startX means don’t careDecember 3, 2012 Ver 1.21 59

MC80F770813. WATCH TIMERThe watch timer generates interrupt for watch operation.The watch timer consists of the clock selector, 21-bit binarycounter and watch timer mode register. It is a multi-purposetimer. It is generally used for watch design.The bit 0, 1, 2 of WTMR select the clock source of watchtimer among sub-clock, f MAIN ÷2 8 ,f MAIN ÷2 7 ,f MAIN orf MAIN ÷2 of main-clock and f MAIN of main-clock. Thef MAIN of main-clock is used usually for watch timer test, sogenerally it is not used for the clock source of watch timer.The f MAIN ÷2 7 or f MAIN ÷2 8 clock is used when the singleclock system is organized. If f MAIN ÷2 8 or f MAIN ÷2 7 clockis used as watch timer clock source, when the CPU entersinto stop mode, the main clock is stopped and then watchtimer is also stopped. If the sub-clock is used as the watchtimer source clock, the watch timer count cannot bestopped. Therefore, the sub-clock does not stop and continuesto oscillate even when the CPU is in the STOP mode.The timer counter consists of 21-bit binary counter and itcan count to max 60 seconds at sub-clock.The bit 3, 4 of WTMR select the interrupt request intervalof watch timer among 2Hz, 4Hz, 16Hz and 1/64Hz.Note: The Clock source of watch timer is also applied toLCD dirver clock source. When selecting LCD dirver clocksource, the WTCK[2:0] should be set to appropriate value.WTR (Watch Timer Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0WTCL WT6 WT5 WT4 WT3 WT2 WT1 WT0ADDRESS: 0E8 HINITIAL VALUE:0111_1111 BWTCL (WT Clear)0: Free Run1: WT Clear(Auto clear after 1cycle)WT[6:0] (WT Interrupt Interval Value)WT Interrupt Interval(IFWT) = (fwck/2 14 ) x (7bit WT Value+1)WTMR (Watch Timer Mode Register)R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0WTEN LOADEN - WTIN1 WTIN0 WTCK2 WTCK1 WTCK0ADDRESS: 0EA HINITIAL VALUE:00--_0000 BWTEN (Watch Timer Enable Bit)0: Watch Timer Disable1: Watch Timer EnableLOADEN (7bit reload Counter Write Enable Bit)0: Watch Dog Timer Write Enable1: Watch Timer Write EnableWTIN[1:0] (Watch Timer Interrupt Interval Selection)00: f wck / 2 11 [16Hz]*01: f wck / 2 13 [4Hz]*10: f wck / 2 14 [2Hz]*11: f wck / 2 14 x (7bit WT value+1) [2Hz x (7bit WT value+1)]** When f SUB = 32.768 kHz and f MAIN = 4.19 MHz( f MAIN ÷2 7 )WTCK[2:0] (Watch Timer Clock Source Selection) : f wck000: Sub. Clock (f SUB )001: Main Clock (f MAIN ÷2 8 )010: Main Clock (f MAIN ÷2 7 )011: Main Clock (f MAIN )111: Main Clock (f MAIN ÷2)Example:; 1 minute watch timer interrupt selectionLDM WTMR, #1101_1000BLDM WTR, #1111_0111B; T = 1/f SUB x 2 14 x (count+1); 080h + 119(count)Figure 13-1 Watch Timer Mode Register60 December 3, 2012 Ver 1.21

MC80F7708WTCK[2:0]f SUBf MAIN ÷2 8f MAIN ÷2 7f MAIN ÷2MUXf wckWTEN14 BITBinary Counter2HzTimer Counter(7bit auto reload counter)7 bit2Hz x (7bit WT value + 1)16 Hz4 Hz2 Hzwhen f wck =f SUB = 32.768 kHz orf wck = f MAIN ÷2 7 ( f MAIN =4.19MHz)WTIN[1:0]MUXWTIFWTEN-WTIN1WTIN0f MAINLOADEN WTCK1 WTCK0WTCK2WTMRLOADENData Writing Control bit for WDTR and WTR0 : Watchdog Timer Write Enable1: Watch Timer Write EnableWTCLWT6 WT5 WT4 WT3 WT2 WT1 WT0WTRFigure 13-2 Watch Timer Block DiagramUsage of Watch Timer in STOP ModeWhen the system is off and the watch should be kept working,follow the steps below.1. Set the clock source of watch timer to sub-clock.2. Enters into STOP mode.3. After released by watch timer interrupt, counts up timerand refreshes LCD Display. When performing count upand refresh the LCD, the CPU operates in main frequencymode.4. Enters into STOP mode again.5. Repeats 3 and 4.When using STOP mode, if the watch timer interrupt intervalis selected to 2Hz, the power consumption can be reducedconsiderably.December 3, 2012 Ver 1.21 61

MC80F770814. WATCH DOG TIMERThe watch dog timer (WDT) function is used for checkingprogram malfunction due to external noise or other causesand return the operation to the normal contion.The watchdog timer consists of 7-bit binary counter andthe watchdog timer register(WDTR). The source clock ofWDT is overflow of Basic Interval Timer. When the valueof 7-bit binary counter is equal to the lower 7-bits ofWDTR, the interrupt request flag is generated. This can beused as WDT interrupt or CPU reset signal in accordancewith the bit WDTON. When WDTCL is set, 7-bit counterof WDT is reset. After one cycle, it is cleared by hardware.When writing WDTR, the LOADEN bit of WTMR registershould be cleared to “0”.Note: WDTR and WTR has same address 0E8h. TheLOADEN bit is used to select WDTR or WTR. When LOAD-EN of watch timer mode register(WTMR) is set to “1”,WDTR can not be wrote and WTR is wrote.The LOADEN bit should be cleared to “0” when writing anyvalue to WDTR.Note: When using watch dog timer, don’t write WDT[6:0] to“0000000”.BIT OverflowWDT6 WDT5 WDT4 WDT3 WDT2 WDT1 WDT0ClearTo Reset CircuitComparatorWDTIFLOADENWriteWDTCL - WDT6 WDT5 WDT4 WDT3 WDT2Watch Dog Timer RegisterWDT1WDT0[0E8 H ]WDTONCKCTLR[0E6 H ]WDTR (Watch Dog Timer Register)W W W W W W WBit : 7 6 5 4 3 2 1 0WDTCL - WDT6 WDT5 WDT4 WDT3 WDT2 WDT1 WDT0WDTCL (WDT Clear)0: Free Run1: WDT Clear(Auto clear after 1cycle)ADDRESS: 0E8 HINITIAL VALUE:0111_1111 BWDT[6:0] (WDT Interrupt Value)WDT Interrupt Interval(IFWDT) = (BIT Interrupt Interval) x (WDT value)WTMR (Watch Timer Mode Register)R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0WTEN LOADEN - WTIN1 WTIN0 WTCK2 WTCK1 WTCK0ADDRESS: 0EA HINITIAL VALUE:00--_0000 BLOADEN (7bit reload Counter Write Enable Bit)0: Watch Dog Timer Write Enable1: Watch Timer Write EnableFigure 14-1 Block Diagram of Watch Dog Timer62 December 3, 2012 Ver 1.21

MC80F7708Sour ClockBIT OverflowBinaryCounter0 1 2 3 0 1 2 3 0 1 2WDTR[7:0]n 3CounterClearWDTIFInterruptWDTCLOccurWDTR

MC80F770815. ANALOG TO DIGITAL CONVERTERThe analog-to-digital(A/D) converter allows conversion ofan analog input signal to an corresponding 10-bit digitalvalue. The A/D module has six analog inputs, which aremultiplexed into one sample and hold. The output of thesample and hold is the input of the converter, which generatesthe result via successive approximation. The analogsupply voltage is connected to AV DD of ladder resistanceof A/D module.The A/D module has three registers which are the controlregister ADCM and A/D result register ADCRH and AD-CRL. The ADCRH[7:6] is also used as ADC clock sourceselection bits. The ADCM register, shown in Figure 15-2,controls the operation of the A/D converter module. Theport pins can be configured as analog inputs or digital I/O.To use analog inputs, each port should be assigned analoginput port by setting R2IO direction register as input modeand setting ADS[3:0] to select the corresponding channel.The self bias check reference provides fixed voltage (typical1.185V, tolerance to be defined), which can be the inputof ADC when setting ADS[3:0] to “1111b”. Thisfeature can be used to check the voltage of VDD pin. TheBIR_ENB and AD_REFB of BIRR register should be setto “0” for using self bias check reference.The processing of conversion is start when the start bitADST is set to “1”. After one cycle, it is cleared by hardware.The register ADCRH and ADCRL contain the result(10bit) of the A/D conversion. If the ADC is set to 8-bitmode (ADC8 bit of ADCRH is “1b”), ADCRL containsthe result of the A/D conversion. When the conversion iscompleted, the result is loaded into the ADCR, the A/Dconversion status bit ADF is set to “1”, and the A/D interruptflag ADIF is set. The block diagram of the A/D moduleis shown in Figure 15-1. The A/D status bit ADF isautomatically set when A/D conversion is completed,cleared when A/D conversion is in process. The conversionneeds 13 clock period of ADC clock (f PS ). It is recommendedto use ADC clock of at least 1us period.Note: The ADC value of self bias check reference(Vbias_ref ) is can be used to check the VDD voltage.When V bias_ref is 1.185V and VDD is 5.12V, the ADC valueis “0EDh”. If VDD is changed and ADC value is “13Ch”, theVDD voltage is 3.84V.the ADC value is changed to “13Ch”. The VDD voltage canbe calculated by following formula.VDD voltage = V bias_ref x 1024 ÷ ADC ValueADENV DDResistor Ladder CircuitAN0AN1AN2AN3AN4MUXSample & HoldSuccessiveApproximationCircuitADCIFADCINTERRUPTAN5ADC8 0 1Self BiasCheck Reference(ADS[3:0] = 1111b,BIR_ENB 1 = 0,AD_REFB 1 = 0)ADS[3:0] (ADCM[5:2])10-bit Mode9 8ADCR 10-bit ADCR (10-bit)8-bit Mode9 8 3 210-bit ADCR001. Self Bias check reference can operate normally whenBIR_ENB(BIRR.7) and AD_REFB(BIRR.5) bit is setto “0” (enable)ADCRH ADCRL (8-bit)1 0ADC Result RegisterADCRH ADCRL (8-bit)1 0ADC Result RegisterFigure 15-1 A/D Converter Block Diagram & Registers64 December 3, 2012 Ver 1.21

MC80F7708ADCM (A/D Converter Mode Register)ADENR/WADEN (A/D Converter Enable bit)1 : Enable0 : DisableADST (A/D Start bit)1 : A/D Conversion is startedAfter 1 cycle, cleared to “0”0 : Bit force to zeroADF (A/D Status bit)0 : A/D Conversion is in process1 : A/D Conversion is completedR/W R/W R/W RBit : 7 6 5 4 3 2 1 0ADCK ADS3 ADS2 ADS1 ADS0 ADST ADFADCK (A/D Converter Clock source bit)0 : A/D Converter Clock source = f PS /11 : A/D Converter Clock source = f PS /2ADS[3:0] (A/D Converter Input Selection)0000 : Channel 0 (R20/AN0)0001 : Channel 1 (R21/AN1)0010 : Channel 2 (R22/AN2)0011 : Channel 3 (R23/AN3)0100 : Channel 4 (R24/AN4)0101 : Channel 5 (R25/AN5)0110 : Reserved0111 : Reserved1000 : Reserved1001 : Reserved1010 : Reserved1011 : Reserved1100 : Reserved1101 : Reserved1110 : Reserved1111 : Self Bias Check ReferenceADDRESS : 0E2 HRESET VALUE : -0-00001 BNote : R24/AN4 and R25/AN5 are not supported in MC80F7708K.ADCRH (A/D Converter Result High Register)W W W R R R R RBit : 7 6 5 4 3 2 1 0PSSEL1 PSSEL0 ADC8 - - - ADR9 ADR8ADDRESS : 0E4 HRESET VALUE : UndefinedPSSEL[1:0] (A/D Converter PS Clock selection bit)00 : A/D Converter PS Clock (f PS ) = f XIN /401 : A/D Converter PS Clock (f PS ) = f XIN /810 : A/D Converter PS Clock (f PS ) = f XIN /1611 : A/D Converter PS Clock (f PS ) = f XIN /32ADC8 (A/D Convertr Mode bit)0 : 10-bit Mode1 : 8-bit ModeADCRL (A/D Converter Result Low Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0ADDRESS : 0E3 HRESET VALUE : UndefinedFigure 15-2 A/D Converter Mode & Result RegistersDecember 3, 2012 Ver 1.21 65

MC80F7708ENABLE A/D CONVERTERA/D Converter Cautions(1) Input range of AN0 to AN5The input voltages of AN0 to AN7 should be within thespecification range. In particular, if a voltage above AV DDor below V SS is input (even if within the absolute maximumrating range), the conversion value for that channelcan not be determinated. The conversion values of the otherchannels may also be affected.(2) Noise counter measuresIn order to maintain 8-bit resolution, any attention must bepaid to noise on pins AV DD and AN0 to AN7. Since the effectincreases in proportion to the output impedance of theanalog input source, it is recommended that a capacitor isconnected externally as shown below in order to reducenoise.A/D INPUT CHANNEL SELECTA/D START (ADST = 1)AnalogInput100~1000pFAN0~AN5NOPADF = 1YESREAD ADCRL/ADCRHFigure 15-3 A/D Converter Operation FlowNOFigure 15-4 Analog Input Pin Connecting Capacitor(3) Pins AN0/R20 to AN5/R25The analog input pins AN0 to AN5 also function as input/output port (PORT R2) pins. When A/D conversion is performedwith any of pins AN0 to AN57 selected, be sure notto execute a PORT input instruction while conversion is inprogress, as this may reduce the conversion resolution.Also, if digital pulses are applied to a pin adjacent to thepin in the process of A/D conversion, the expected A/Dconversion value may not be obtainable due to couplingnoise. Therefore, avoid applying pulses to pins adjacent tothe pin undergoing A/D conversion.(4) AV DD pin input impedanceA series resistor string of approximately 10KΩ is connectedbetween the AV DD pin and the V SS pin.Therefore, if the output impedance of the reference voltagesource is high, this will result in parallel connection to theseries resistor string between the AV DD pin and the V SSpin, and there will be a large reference voltage error.66 December 3, 2012 Ver 1.21

MC80F770816. BUZZER OUTPUT FUNCTIONThe buzzer driver consists of 6-bit binary counter, thebuzzer driver register BUZR and the clock selector. It generatessquare-wave which is very wide range frequency(500 Hz~125 kHz at f MAIN = 4MHz) by user programmablecounter.Pin R04/BUZO is assigned for output port of Buzzer driverby setting the bit BUZO of R0 Function Register(R0FUNC)to “1”.The 6-bit buzzer counter is cleared and start the countingby writing signal to the register BUZR. It is increased from00 H until it matches with BUR[5:0].Also, it is cleared by counter overflow and count up to outputthe square wave pulse of duty 50%.The bit 0 to 5 of BUZR determines output frequency forbuzzer driving. BUZR[5:0] is initialized to 3F H after reset.Note that BUZR is a write-only register. Frequency calculationis following as shown below.f BUZ =f--------------------------------------------------------------------------------------------------XIN2 × DivideRatio × ( BUZR[ 5:0] + 1)The bits BUCK1, BUCK0 of BUZR select the sourceclock from prescaler output.f BUZ : Buzzer frequencyf XIN : Oscillator frequencyDivide Ratio: Prescaler divide ratio by BUCK[1:0]BUZR[5:0]: Lower 6-bit value of BUZR. Buzzer control data.BUZR (Buzzer Driver Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0BUCK1 BCUK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0BUCK (Buzzer Clock Source)00: f MAIN ÷2 301: f MAIN ÷2 410: f MAIN ÷2 511: f MAIN ÷2 6BUR[5:0] (Buzzer Control Data)ADDRESS : 0CE HRESET VALUE : FF HBit manipulation is not available.Port Selection Register 0PSR0INT1E INT0E - BUZO RX0I TX0O EC0E -BUZO (Buzzer Output)0 : R04 Port (turn off buzzer)1 : BUZO port (turn on buzzer)ADDRESS : 0AA HRESET VALUE : 00-0000- BSCMR[1:0]2÷ 8X IN0X1X÷ 16÷ 32MUXCOUNTER (6-bit)÷ 64÷ 2BUCKCOMPARATORF/FR04/BUZO PINBUZR[5:0] (6-bit)BUZO[R0FUNC.4]Figure 16-1 Buzzer DriverExample: 2.5kHz output at 4MHz.LDM R0FUNC,#XXX1_XXXXBLDM BUZR,#1001_1000BX means don’t careDecember 3, 2012 Ver 1.21 67

MC80F770868 December 3, 2012 Ver 1.21Buzzer Output FrequencyWhen main-frequency is 4MHz, buzzer frequency isshown as below.Table 16-1 Buzzer Output FrequencyBUZR[5:0]Frequency Output (kHz)BUZR[7:6]BUZR[5:0]Frequency Output (kHz)BUZR[7:6]00 01 10 11 00 01 10 110001020304050607250.000125.00083.33362.50050.00041.66735.71431.250125.00062.50041.66731.25025.00020.83317.85715.62562.50031.25020.83315.62512.50010.4178.9297.81331.25015.62510.4177.8136.2505.2084.4643.90620212223242526277.5767.3537.1436.9446.7576.5796.4106.2503.7883.6763.5713.4723.3783.2893.2053.1251.8941.8381.7861.7361.6891.6451.6031.5630.9470.9190.8930.8680.8450.8220.8010.78108090A0B0C0D0E0F27.77825.00022.72720.83319.23117.85716.66715.62513.88912.50011.36410.4179.6158.9298.3337.8136.9446.2505.6825.2084.8084.4644.1673.9063.4723.1252.8412.6042.4042.2322.0831.95328292A2B2C2D2E2F6.0985.9525.8145.6825.5565.4355.3195.2083.0492.9762.9072.8412.7782.7172.6602.6041.5241.4881.4531.4201.3891.3591.3301.3020.7620.7440.7270.7100.6940.6790.6650.651101112131415161714.70613.88913.15812.50011.90511.36410.87010.4177.3536.9446.5796.2505.9525.6825.4355.2083.6763.4723.2893.1252.9762.8412.7172.6041.8381.7361.6451.5631.4881.4201.3591.30230313233343536375.1025.0004.9024.8084.7174.6304.5454.4642.5512.5002.4512.4042.3582.3152.2732.2321.2761.2501.2251.2021.1791.1571.1361.1160.6380.6250.6130.6010.5900.5790.5680.55818191A1B1C1D1E1F10.0009.6159.2598.9298.6218.3338.0657.8135.0004.8084.6304.4644.3104.1674.0323.9062.5002.4042.3152.2322.1552.0832.0161.9531.2501.2021.1571.1161.0781.0421.0080.97738393A3B3C3D3E3F4.3864.3104.2374.1674.0984.0323.9683.9062.1932.1552.1192.0832.0492.0161.9841.9531.0961.0781.0591.0421.0251.0080.9920.9770.5480.5390.5300.5210.5120.5040.4960.488

MC80F770817. INTERRUPTSThe MC80F7708 interrupt circuits consist of Interrupt enableregister (IENH, IENM, IENL), Interrupt request flagregister(IRQH, IRQM, IRQL), Interrupt flag register(IN-TFH, INTFL), Interrupt Edge Selection Register (IEDS),priority circuit and Master enable flag (“I” flag of PSW).The interrupts are controlled by the interrupt master enableflag I-flag (bit 2 of PSW), the interrupt enable register andthe interrupt request flag register except Power-on resetand software BRK interrupt. The configuration of interruptcircuit is shown in Figure 17-1 and interrupt priority isshown in Table 17-1 .Table 17-1 Vector TableReset/Interrupt Symbol Priority Vector Addr.Hardware ResetExternal Int. 0External Int. 1External Int. 2External Int. 3UART_RX0UART_TX0Timer 0 Int.Timer 1 Int.Timer 2 Int.Timer 3 Int.A/D Int.BIT Int.Watch Dog timer int.Watch timer int.RESETINTR0INTR1INTR2INTR3RX0TX0T0T1T2T3ADCBITWDTWT01234567891011121314FFFEHFFFAHFFF8HFFF6HFFF4HFFF2HFFF2HFFEEHFFECHFFEAHFFE8HFFE4HFFE2HFFE0HFFE0HEach bit of interrupt request flag registers(IRQH, IRQM,IRQL) in Figure 17-1 is set when corresponding interruptcondition is met. The interrupt request flags that actuallygenerate external interrupts are bit INT0F, INT1F andINT2F in Register IRQH and INT3F in Register IRQL.The External Interrupts INT0, INT1, INT2 and INT3 caneach be transition-activated (1-to-0, 0-to-1 and both transition).The RX0 and TX0 of UART0 Interrupts are generatedby RX0IF and TX0IF which are set by finishing thereception and transmission of data.The Timer 0,1,2 and Timer 3 Interrupts are generated byT0IF,T1IF,T2IF and T3IF, which are set by a match intheir respective timer/counter register. The AD converterInterrupt is generated by ADCIF which is set by finishingthe analog to digital conversion.The Basic Interval Timer Interrupt is generated by BITIFwhich is set by overflow of the Basic Interval Timer Register(BITR). The Watch dog Interrupt is generated byWDTIF which set by a match in Watch dog timer register(when the bit WDTON is set to “0”). The Watch Timer Interruptis generated by WTIF which is set periodically accordingto the established time interval.When an interrupt is generated, the bit of interrupt requestflag register(IRQH, IRQM, IRQL) that generated it maynot cleared itself during interrupt acceptance processing.After interrupt acceptance, it should be cleard in interruptservice routine.Each bit of Interrupt flag register(INTFH, INTFL) is setwhen corresponding interrupt flag bit as well as interruptenable bit are set. The bits of interrupt flag register are nevercleared by the hardware although the service routine isvectored to. Therefore, the interrupt flag register can beused to distinguish a right interrupt source from two availableones in a vector address. For example, RX0 and TX0which have the same vector address(FFF2 H ) may be distinguishedby INTFH register.Interrupt enable registers are shown in Figure 17-2. Theseregisters are composed of interrupt enable bits of each interruptsource, these bits determine whether an interruptwill be accepted or not. When enable bit is “0”, a correspondinginterrupt source is prohibited. Note that PSWcontains also a master enable bit, I-flag, which disables allinterrupts at once. When an interrupt is occurred, the I-flagis cleared and disable any further interrupt, the return addressand PSW are pushed into the stack and the PC is vectoredto.In an interrupt service routine, any other interrupt may beserviced. The source(s) of these interrupts can be determinedby polling the interrupt request flag bits. Then, theinterrupt request flag bit(s) must be cleared by software beforere-enabling interrupts to avoid recursive interrupts.The Interrupt Request flags are able to be read and written.December 3, 2012 Ver 1.21 69

MC80F7708IRQHInternal bus lineIENHInterrupt EnableRegister (Higher byte)I-flag is in PSW, it is cleared by “DI”, set by“EI” instruction.When it goes interrupt service,I-flag is cleared by hardware, thus any otherinterrupts are inhibited. When interrupt service iscompleted by “RETI” instruction, I-flag is set to“1” by hardware.Ext. Int. 0Ext. Int. 1Ext. Int. 2Ext. Int. 3IEDSINT0IFINT1IFINT2IF654Release STOPRX0TX0RX0IFTX0IFIRQM32Internal bus lineIENMINTFH(Middle byte)Priority ControlI FlagInterrupt MasterEnable FlagInterruptVectorAddressGeneratorTo CPUTimer 0Timer 1T0IFT1IF76Timer 2T2IF5Timer 3T3IF4A/D converterADCIF0INTFLBasic interval TimerBITIF6Watch Dog TimerWatch TimerWDTIFWTIF54INT3IF3IRQLIENLInterrupt EnableRegister (Lower byte)Internal bus lineFigure 17-1 Block Diagram of Interrupt70 December 3, 2012 Ver 1.21

MC80F7708IENH (Interrupt Enable High Register)R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0- INT0E INT1E INT2E RX0E TX0E - -ADDRESS : 0F6 HRESET VALUE : -00-00-- BIENM (Interrupt Enable Middle Register)R/W R/W R/W R/WR/W R/WBit : 7 6 5 4 3 2 1 0T0E T1E T2E T3E - - - ADCIENL (Interrupt Enable Low Register)R/W R/W R/WBit : 7 6 5 4 3 2 1 0- BITE WDTE WTE INT3E - - -Enables or disables the interrupt individuallyIRQH (Interrupt Request Flag High Register)R/W R/W R/WR/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0- INT0IF INT1IF - RX0IF TX0IF - -IRQM (Interrupt Request Flag Middle Register)R/W R/W R/W R/WR/W R/WBit : 7 6 5 4 3 2 1 0T0IF T1IF T2IF T3IF - - - ADCIFIRQL (Interrupt Request Flag Low Register)R/W R/W R/WBit : 7 6 5 4 3 2 1 0- BITIF WDTIF WTIF INT3IF - - -ADDRESS : 0F7 HRESET VALUE : 0000---0 BADDRESS : 0F8 HRESET VALUE : -000---- B0 : Disable1 : EnableADDRESS : 0F9 HRESET VALUE : -00-00-- BADDRESS : 0FA HRESET VALUE : 0000---0 BADDRESS : 0FB HRESET VALUE : -000---- B0 : Interrupt not occurred1 : Interrupt RequestINTFH (Interrupt Flag Register Low)R/W R/WR/W R/W R/WBit : 7 6 5 4 3 2 1 0- - - - IFRX0 IFTX0 - -IFRX0(RX0 Interrupt Flag)0 : No Generation1 : GenerationIFTX0(TX0 Interrupt Flag)0 : No Generation1 : GenerationADDRESS : 0F4 HRESET VALUE : 00----00 BINTFL (Interrupt Flag Register Low)R/W R/WR/W R/W R/WBit : 7 6 5 4 3 2 1 0- - - - - - WTF WDTFWTF(WT Interrupt Flag)0 : No Generation1 : GenerationWDTF(WDT Interrupt Flag)0 : No Generation1 : GenerationADDRESS : 0F5 HRESET VALUE : 00----00 BFigure 17-2 Interrupt Enable Registers and Interrupt Request RegistersDecember 3, 2012 Ver 1.21 71

MC80F770817.1 Interrupt SequenceAn interrupt request is held until the interrupt is acceptedor the interrupt latch is cleared to “0” by a reset or an instruction.Interrupt acceptance sequence requires 8 f OSC (2μs at f MAIN =4MHz) after the completion of the current instructionexecution. The interrupt service task is terminatedupon execution of an interrupt return instruction[RETI].Interrupt acceptance1. The interrupt master enable flag (I-flag) is cleared to“0” to temporarily disable the acceptance of any followingmaskable interrupts. When a non-maskable interruptis accepted, the acceptance of any followinginterrupts is temporarily disabled.2. Interrupt request flag for the interrupt source accepted iscleared to “0”.3. The contents of the program counter (return address)and the program status word are saved (pushed) onto thestack area. The stack pointer decreases 3 times.4. The entry address of the interrupt service program isread from the vector table address and the entry addressis loaded to the program counter.5. The instruction stored at the entry address of the interruptservice program is executed.System clockInstruction FetchAddress Bus PC SP SP-1 SP-2 V.L. V.H. New PCData Bus Not used PCH PCL PSW V.L. ADL ADHOP codeInternal ReadInternal WriteInterrupt Processing StepInterrupt Service RoutineV.L. and V.H. are vector addresses.ADL and ADH are start addresses of interrupt service routine as vector contents.Figure 17-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction0FFE2 H0FFE3 HBasic Interval TimerVector Table Address012 H0E3 HEntry Address0E312 H 0E H0E313 H 2E HCorrespondence between vector table address for BIT interruptand the entry address of the interrupt service program.An interrupt request is not accepted until the I-flag is set to“1” even if a requested interrupt has higher priority thanthat of the current interrupt being serviced.When nested interrupt service is required, the I-flag shouldbe set to “1” by “EI” instruction in the interrupt serviceprogram. In this case, acceptable interrupt sources are selectivelyenabled by the individual interrupt enable flags.Saving/Restoring General-purpose RegisterDuring interrupt acceptance processing, the programcounter and the program status word are automaticallysaved on the stack, but accumulator and other registers arenot saved itself. If necessary, these registers should besaved by the software. Also, when multiple interrupt servicesare nested, it is necessary to avoid using the samedata memory area for saving registers.72 December 3, 2012 Ver 1.21

MC80F7708The following method is used to save/restore the generalpurposeregisters.Example: Register savingGeneral-purpose registers are saved or restored by usingpush and pop instructions.INTxx: PUSH APUSH XPUSH Yinterrupt processing;SAVE ACC.;SAVE X REG.;SAVE Y REG.main routineacceptance ofinterruptinterruptservice routinesavingregistersPOPPOPPOPRETIYXA;RESTORE Y REG.;RESTORE X REG.;RESTORE ACC.;RETURNinterrupt returnrestoringregisters17.2 BRK InterruptSoftware interrupt can be invoked by BRK instruction,which has the lowest priority order.Interrupt vector address of BRK is shared with the vectorof TCALL 0 (Refer to Program Memory Section). WhenBRK interrupt is generated, B-flag of PSW is set to distinguishBRK from TCALL 0.Each processing step is determined by B-flag as shown inFigure 17-4.BRK orTCALL0B-FLAG=1BRKINTERRUPTROUTINE=0TCALL0ROUTINERETIRETFigure 17-4 Execution of BRK/TCALL017.3 Multi InterruptIf two requests of different priority levels are received simultaneously,the request of higher priority level is serviced.If requests of the interrupt are received at the sametime simultaneously, an internal polling sequence determinesby hardware which request is serviced.However, multiple processing through software for specialfeatures is possible. Generally when an interrupt is accepted,the I-flag is cleared to disable any further interrupt. Butas user sets I-flag in interrupt routine, some further interruptcan be serviced even if certain interrupt is in progress.Example: Even though Timer1 interrupt is in progress,INT0 interrupt serviced without any suspend.TIMER1: PUSH APUSH XPUSH YLDM IENH,#40H ;Enable INT0 onlyLDM IENM,#0 ;Disable otherLDM IENL,#0 ;Disable otherEI;Enable Interrupt::::::LDM IENH,#0FFH ;Enable all interruptsLDM IENM,#0FFHLDM IENL,#0F0HPOP YPOP XPOP ARETIDecember 3, 2012 Ver 1.21 73

MC80F7708.Main ProgramserviceTIMER 1serviceenable INT0disable otherEIINT0serviceOccurTIMER1 interruptOccurINT0enable INT0enable otherIn this example, the INT0 interrupt can be serviced without anypending, even TIMER1 is in progress.Because of re-setting the interrupt enable registers IENH,IENM,IENLand master enable "EI" in the TIMER1 routine.Figure 17-5 Execution of Multi Interrupt74 December 3, 2012 Ver 1.21

MC80F770817.4 External InterruptThe external interrupt on INT0, INT1, INT2 and INT3 pinsare edge triggered depending on the edge selection registerIEDS (address 0FC H ) as shown in Figure 17-6.The edge detection of external interrupt has three transitionactivated mode: rising edge, falling edge, and both edge.INT0INT1INT2INT3edge selection[0FC H ]IEDSINT0IFINT1IFINT2IFINT3IFINT0 INTERRUPTINT1 INTERRUPTINT2 INTERRUPTINT3 INTERRUPTIEDS (Ext. Interrupt Edge Selection Register)ADDRESS : 0FC HRESET VALUE : 00000000 BR/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0IED3H IED3L IED2H IED2L IED1H IED1L IED0H IED0LFigure 17-6 External Interrupt Block DiagramExample: To use as an INT0::;**** Set port as an input port R0LDM R0IO,#1011_1111B;;**** Set port as an interrupt portLDM PSR0,#0100_0000B;;**** Set Falling-edge DetectionLDM IEDS,#0000_0001B:::Response TimeThe INT0, INT1,INT2 and INT3 edge are latched intoINT0F, INT1F, INT2F and INT3F at every machine cycle.The values are not actually polled by the circuitry until thenext machine cycle. If a request is active and conditions areright for it to be acknowledged, a hardware subroutine callto the requested service routine will be the next instructionto be executed. The DIV itself takes twelve cycles. Thus, amaximum of twelve complete machine cycles elapse betweenactivation of an external interrupt request and thebeginning of execution of the first instruction of the serviceroutine.Interrupt response timings are shown in Figure 17-7.INT1INT0Edge Selection Register00 : Reserved01 : Falling (1-to-0 transition)10 : Rising (0-to-1 transition)11 : Both (Rising & Falling)max. 12 f OSC8 f OSCInterruptgoesactiveInterruptlatchedInterruptprocessingInterruptroutineFigure 17-7 Interrupt Response Timing DiagramDecember 3, 2012 Ver 1.21 75

MC80F770818. LCD DRIVERThe MC80F7708 has the circuit that directly drives the liquidcrystal display (LCD) and its control circuit. The segment/commondriver directly drives the LCD panel, andthe LCD controller generates the segment/common signalsaccording to the RAM which stores display data. VCL3 ~VCL0 voltage are made by the internal bias resistor circuit.The MC80F7708 has the segement output port 16 pins(SEG0 ~ SEG15) and Common output port 8 pins (COM0~ COM7). If the LCDD0 bit of LCR is set to “1”, COM4 ~COM7 is used as SEG19 ~ SEG16.The Figure 18-1 shows the configuration of the LCD driver.SEG0INTERNAL BUS LINEWTMR[2:0]000001010011100MUXDisplay Memory(20bytes)f SUBf MAIN ÷2 8f MAIN ÷2 7f MAINf MAIN ÷2 1Display Data Select ControlDisplay Data Buffer registerSegment/Common DriverPrescaler÷ 32÷ 64÷ 128 MUX÷ 256Select clockLCDControl RegisterLCR[0F1H]clockLCDTiming ControlLCDENSelect DutySEG15SEG16/COM7SEG17/COM6SEG18/COM5SEG19/COM4LCD DriverPower CircuitFigure 18-1 LCD Driver Block Diagram76 December 3, 2012 Ver 1.21

MC80F770818.1 Control of LCD Driver CircuitThe LCD driver is controlled by the LCD Control Register(LCR). The LCR[1:0] determines the frequency of COMsignal scanning of each segment output. RESET clears theLCD control register LCR values to logic zero. The LCDSEG or COM ports are selected by setting correspondingbits of R5PSR, R6PSR or R7PSR to “0”.The LCD display can continue to operate during SLEEPand STOP modes if sub-frequency clock is used as LCDclock source.LCR(LCD Control Register)R/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0SCKD1 LCDEN 0 1 LCDD0 LCK1 LCK0SCKD (Sub Clock Disable)0: Sub Clock Oscillation (SXIN, SXOUT)1: Sub Clock Disable (R45, R46)LCDEN (LCD Display Enable Bit)0: LCD Display Disable1: LCD Display Enable* Unused bit of LCR should be set asBit6 : “1”Bit4 : “0”Bit3 : “1”LCDD0 (LCD Duty Selection)0: 1/8 Duty, 1/4 Bias1: 1/4 Duty, 1/3 BiasADDRESS : 0B2 HRESET VALUE : 000-0000BLCK (LCD Clock source selection)00: f S ÷ 32 (Frame Frequency 1024Hz When fs is 32.768kHz)01: f S ÷ 64 (Frame Frequency 512Hz When fs is 32.768kHz)10: f S ÷ 128 (Frame Frequency 256Hz When fs is 32.768kHz)11: f S ÷ 256 (Frame Frequency 128Hz When fs is 32.768kHz)* f S : f SUB (Sub clock) or f MAIN ÷ 2 7 or f MAIN ÷ 2 8 or f MAIN ÷ 2 or f MAIN(It can be selected by setting WTCK[2:0] of WTMR register.)R5 / LCD Port Selection RegisterR/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0R5PSR R5PSR7 R5PSR6 R5PSR5 R5PSR4 R5PSR3 R5PSR2 R5PSR1 R5PSR0R6 / LCD Port Selection RegisterR/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0R6PSR R6PSR7 R6PSR6 R6PSR5 R6PSR4 R6PSR3 R6PSR2 R6PSR1 R6PSR0ADDRESS : 0AC HRESET VALUE : 1111_1111B(Seg7 ~ Seg0)ADDRESS : 0AD HRESET VALUE : 1111_1111B(Seg15 ~ Seg8)R/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0R7PSRR7 / LCD Port Selection RegisterR7PSR7R7PSR6R5PSR~R7PSR0 : Seg or COM Selection1 : Port SelectionR7PSR5 R7PSR4 R7PSR3 R7PSR2 R7PSR1 R7PSR0ADDRESS : 0AE HRESET VALUE : 1111_1111B(COM0~COM3, Seg19/COM4 ~ Seg16/COM7)WTMR (Watch Timer Mode Register)R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0WTEN LOADEN - WTIN1 WTIN0 WTCK2 WTCK1 WTCK0ADDRESS: 0EA HINITIAL VALUE:00--_0000 BWTEN (Watch Timer Enable Bit)0: Watch Timer Disable1: Watch Timer EnableWTIN[1:0] (Watch Timer Interrupt Interval Selection)00: f wck / 2 11 [16Hz]*01: f wck / 2 13 [4Hz]*10: f wck / 2 14 [2Hz]*11: f wck / 2 14 x (7bit WT value+1) [2Hz x (7bit WT value+1)]*LOADEN (7bit reload Counter Write Enable Bit)0: Watch Dog Timer Write Enable1: Watch Timer Write EnableWTCK[2:0] (Watch Timer and LCD Clock Source Selection) : f wck000: Sub. Clock (f SUB )001: Main Clock (f MAIN ÷2 8 )010: Main Clock (f MAIN ÷2 7 )011: Main Clock (f MAIN )111: Main Clock (f MAIN ÷2)Figure 18-2 LCD Control RegisterDecember 3, 2012 Ver 1.21 77

MC80F7708Note: If the SCKD is set to “1”, the SXIN and SXOUT pinis used as normal I/O pin R45, R46.Note: When the Sub clock is used as internal bias sourceclock, stabilization time is needed. Normally, the stabilizationtime is need more than 500ms.Note: When selecting Sub clock as the LCD clock source,the WTCK[2:0] bit of WTMR(Watch Timer Mode Register)should be set to “000” as well as SCKD bit of LCR be set to“0”.Note: Bit 6, Bit 4, Bit 3 of LCR should be set to “1”, “0”, “1”respectively.Selecting Frame FrequencyFrame frequency is set to the base frequency as shown inthe following Table 18-1. The f S is selected to f SUB (subclock) which is 32.768kHz.LCR[1:0]00011011LCD clockf SUB ÷ 32f SUB ÷ 64f SUB ÷ 128f SUB ÷ 256Frame Frequency (Hz)Duty = 1/4 Duty = 1/81286432166432168Table 18-1 Setting of LCD Frame FrequencyThe matters to be attended to use LCD driverIn reset state, LCD source clock is sub clock. So, when thepower is supplied, the LCD display would be flickered beforethe oscillation of sub clock is stabilized. It is recommendedto use LCD display on after the stabilization timeof sub clock is considered enough.78 December 3, 2012 Ver 1.21

MC80F770818.2 LCD BIAS ControlThe MC80F7708 has internal Bias Circuit for driving LCDpanel. It alse has the contrast controller of 16 step.The LCD Bias control register and internal Bias circuit isas shown in the Figure 18-3.The SYS_BIR[1:0] and BIF of LBCR register is used forcontrolling BIR. Refer to “24. Butil In Reset (BIR)”Note: The self bias check reference can be applied to contrastadjustment with VDD voltage variation. Because theVDD voltage can be calculated by reading the ADC valueof self bias check reference. Writing appropriate value toCTR[3:0] with VDD level, LCD contrast variation with VDDcan be reduced.LBCR(LCD Bias Control Register)R/W R/W R/W R/W R/W R/W R/W R/WBit : 7 6 5 4 3 2 1 0CTR_SCTR_DS3 CTR_DS2 CTR_DS1 CTR_DS0 SYS_BIR1 SYS_BIR0CTR_S (Voltage Source selection)0: Direct Voltage1: Contrast Controller voltageSYS_BIR (Mode selection of BIR Result)00: Reset mode10: Freeze modeBIF (BIR Flag)0: BIR No Detect1: BIR Detect* BIR : Buit In ResetBlock Diagram of LCD BIASBIRADDRESS : 0B3 HRESET VALUE : 01111000BCTR_DS (Contrast Controller Level Selection)0000: VCL3 = VDD / 20001: VCL3 = VDD * ( 16 / 30 )0010: VCL3 = VDD * ( 17 / 30 )0011: VCL3 = VDD * ( 18 / 30 )0100: VCL3 = VDD * ( 19 / 30 )0101: VCL3 = VDD * ( 20 / 30 )0110: VCL3 = VDD * ( 21 / 30 )0111: VCL3 = VDD * ( 22 / 30 )1000: VCL3 = VDD * ( 23 / 30 )1001: VCL3 = VDD * ( 24 / 30 )1010: VCL3 = VDD * ( 25 / 30 )1011: VCL3 = VDD * ( 26 / 30 )1100: VCL3 = VDD * ( 27 / 30 )1101: VCL3 = VDD * ( 28 / 30 )1110: VCL3 = VDD * ( 29 / 30 )1111: VCL3 = VDDV DDLCDENCTR_DS0CTR_DS1CTR_DS2CTR_DS3ContrastcontrollerCTR_SLCDD0Voltage Selector150K150K150K150KVCL3VCL2VCL1VCL0V SSFigure 18-3 LCD Bias ControlDecember 3, 2012 Ver 1.21 79

MC80F770818.3 LCD Display MemoryDisplay data are stored to the display data area (page 4) inthe data memory.The display datas which stored to the display data area (address0460 H -0473 H ) are read automatically and sent to theLCD driver by the hardware. The LCD driver generates thesegment signals and common signals in accordance withthe display data and drive method. Therefore, display patternscan be changed by only overwriting the contents ofthe display data area with a program. The table look up instructionis mainly used for this overwriting.Figure 18-4 shows the correspondence between the displaydata area and the SEG/COM pins. The LCD lights whenthe display data is “1” and turn off when “0”.SEG19SEG18SEG17SEG16SEG15SEG14SEG13SEG12SEG11SEG10SEG9Bit0 1 2 3 4 5 6 70473 H0472 H0471 H0470 H046F H046E H046D H046C H046B H046A H0469 HThe SEG data for display is controlled by RPR (RAM PagingRegister).SEG8SEG70468 H0467 HSEG60466 HSEG5SEG40465 H0464 HSEG30463 HSEG2SEG10462 H0461 HSEG00460 HCOM0COM1COM2COM3COM4COM5COM6COM7Figure 18-4 LCD Display Memory80 December 3, 2012 Ver 1.21

MC80F770818.4 Control Method of LCD DriverInitial SettingFlow chart of initial setting is shown in Figure 18-5.Example: Driving of LCDSelect Frame FrequencyLDM LCR,#4DH ;f F =64Hz, 1/4 duty(f SUB = 32.768kHz):LDM RPR,#4;Select LCD Memory(4 page)SETGClearLCD DisplayMemoryTurn on LCDLDX #60HC_LCD1: LDA #0 ;RAM Clear;(0460H->0473H)STA {X}+CMPX #074HBNE C_LCD1CLRG:SET1 LCR.5;Enable display:.COM0COM1Setting of LCD drive methodInitialize of display memoryEnable displayFigure 18-5 Initial Setting of LCD DriverDisplay DataNormally, display data are kept permanently in the programmemory and then stored at the display data area bythe table look-up instruction. This can be explained usingcharacter display with 1/4 duty LCD as an example as wellas any LCD panel. The COM and SEG connections to theLCD and display data are the same as those shown is Figure18-6. Following is showing the programming examplefor displaying character.Example: display “2”SEG0SEG1COM2COM3bit 7 6 5 4 3 2 1 0461 H * * * * 1 1 1 0460 H * * * * 0 0 1 1Note: * are don’t care.Figure 18-6 Example of Connection COM & SEGNote: When power on RESET, sub oscillation start up timeis required. Enable LCD display after sub oscillation is stabilized,or LCD may occur flicker at power on time shortly.December 3, 2012 Ver 1.21 81

MC80F7708Write into theLCD MemoryGOLCD::CLRGLDX#

MC80F770818.5 Duty and Bias Selection of LCD Driver4 kinds of driving methods can be selected by LCDD[1:0] (bits 3and 2 of LCD control register) and connection of BIAS pin externally.Figure 18-8 shows typical driving waveforms for LCD.).VCL2VCL1VCL0GND-VCL0-VCL1-VCL2one frameData “1”Data “0”VCL3VCL2VCL1VCL0GND-VCL0-VCL1-VCL2-VCL3one frameData “1”Data “0”(a) 1/4 Duty, 1/3 Bias(b) 1/8 Duty, 1/4 BiasFigure 18-8 LCD Drive Waveform (Voltage COM-SEG Pins)December 3, 2012 Ver 1.21 83

MC80F770819. UNIVERSAL ASYNCHRONOUS SERIAL INTERFACEThe Asynchronous serial interface(UART) enables full-duplexoperation wherein one byte of data after the start bit is transmittedand received. The on-chip baud rate generator dedicated toUART enables communications using a wide range of selectablebaud rates.The UART driver consists of TXSR0, RXBR0, ASIMR0 andBRGCR0 register. Clock asynchronous serial I/O mode (UART)can be selected by ASIMR register. Figure 19-1 shows a block diagramof the serial interface (UART).Internal Data BusReceive BufferRegister(RXR)ASIMR0TXM RXM PS00 PS01 - SL0 ISRM0 -RxReceive BufferRegister(RXBR0)PE0 FE0 OVE0ASISR0Transmit ShiftRegister(TXSR0)TxReceiveController(Parity Check)RXIF(Rx interrupt)TransmitController(Parity Addition)TXIF(Tx interrupt)ACKBaud RateGeneratorf MAIN ÷2 tof MAIN ÷2 7Figure 19-1 UART Block Diagram84 December 3, 2012 Ver 1.21

MC80F7708RECEIVERXEACKTX_CLK1 / 2(Divider)5-bit countermatchMUXfx÷2fx÷2 2fx÷2 3fx÷2 4fx÷2 5fx÷2 6fx÷2 7DecoderRX_CLK1 / 2(Divider)matchBRGCR- TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL05-bit counterTXESENDData BusFigure 19-2 Baud Rate Generator Block Diagram19.1 Asynchronous Serial Interface ConfigurationThe asychronous serial interface (UART) consists of the followinghardware.ItemRegisterControlregisterConfigurationTransmit shift register (TXSR0)Receive buffer register (RXBR0)Asynchronous serial interface mode register(ASIMR0)Baudrate generator control register(BRGCR0)Table 19-1 Serial Interface ConfigurationTransmit Shift Register (TXSR0)This is the register for setting transmit data. Data written toTXSR0 is transmitted as serial data. When the data length is setas 7 bit, bit 0 to 6 of the data written to TXSR0 are transferred astransmit data. Writing data to TXSR0 starts the transmit operation.TXSR0 can be written by an 8 bit memory manipulation instruction.It cannot be read.Note: Do not write to TXSR0 during a transmit operation.The same address is assigned to TXSR0 and the receivebuffer register (RXBR0). A read operation reads valuesfrom RXBR0.Receive Buffer Register (RXBR0)This register is used to hold received data. When one byte of datais received, one byte of new received data is transferred from thereceive shift register. When the data length is set as 7 bits, receiveddata is sent to bits 0 to 6 of RXBR0. In this case, the MSBof RXBR0 always becomes 0. RXBR0 can be read by an 8 bitmemory manipulation instruction. It cannot be written.Note: The same address is assigned to RXBR0 and thetansmit shift register (TXSR0). During a write operation,values are written to TXSR0.Asynchronous serial interface mode control register(ASIMR0)This is an 8 bit register that controls asynchronous serial interface(UART)’s serial transfer operation. ASIMR0 is set by a 1 bit or 8bit memory manipulation instruction.Baud rate generator control register (BRGCR0)This register sets the serial clock for asynchronous serial interface.BRGCR0 is set by an 8 bit memory manipulation instruction.December 3, 2012 Ver 1.21 85

MC80F7708R/W R/W R/W R/W - R/W R/W -7 6 5 4 3 2 1 0ADDRESS: 0B8 HTX0M RX0M PS01 PS00 BTCL - SL0 ISRM0 INITIAL VALUE: 0000 -00- BASIMR0 -TX0M RX0M(Operation mode)00: Operation stop01: UART mode (Receive only)10: UART mode (Transmit only)11: UART mode (Transmit and receive)PS0 [1:0] (Parity Bit Specification)00: No Parity01: Zero Parity always added during transmission.No Parity detection during reception(Parity errors do not occur)10: Odd Parity11: Even ParityReceive Completion Interrrupt Control When Error Occurs0: Receive completion interrupt request is issuedwhen an error occured1: Receive completion interrupt request is not issuedwhen an error occuredStop Bit Length for Specification for Transmit Data0: 1 bit1: 2 bitCaution : Do not switch the operation mode until the current serial transmit/receiveoperation has stopped.R R R7 6 5 4 3 2 1 0ADDRESS: 0B9 H- - - - BTCL - PE0 FE0 INITIAL VALUE: ------000 BASISR0 OVE0Parity Error Flag0: No parity error1: Parity error (Received data parity not matched)Frame Error Flag0: No Frame error1: Framing error (Note1) (stop bit not detected)Overrun Error Flag0: No Overrun Error (Note2)1: Next receive operation was completed before data was readfrom receive buffer register (RXBR0)Note :1. Even if a stop bit length is set to 2 bits by setting bit2(SL0) in ASIMR0,stop bit detection during a recive operation only applies to a stop bit length of 1bit.2. Be sure to read the contents of the receive buffer register(RXBR0)when an overrun error has occurred.Until the contents of RXBR0 are read, futher overrun errors will occur when receiving data.Figure 19-1 Asynchronous Serial Interface Mode & Status Register86 December 3, 2012 Ver 1.21

MC80F7708BRGCR0R/W R/W R/W R/W R/W R/W R/W R7 6 5 4 3 2 1 0- TPS2 TPS1 TPS0 BTCL MDL3 MDL2 MDL1 MDL0ADDRESS: 0BA HINITIAL VALUE: -001 0000 BInput clock Selection for Baud Rate Generator (k)0000: f SCK ÷16 (k=0)0001: f SCK ÷17 (k=1)0010: f SCK ÷18 (k=2)0011: f SCK ÷19 (k=3)0100: f SCK ÷20 (k=4)0101: f SCK ÷21 (k=5)0110: f SCK ÷22 (k=6)0111: f SCK ÷23 (k=7)1000: f SCK ÷24 (k=8)1001: f SCK ÷25 (k=9)1010: f SCK ÷26 (k=10)1011: f SCK ÷27 (k=11)1100: f SCK ÷28 (k=12)1101: f SCK ÷29 (k=13)1110: f SCK ÷30 (k=14)1111: Setting ProhibitedSource Clock Selection for 5-bit Counter (= f SCK ) (n)000: R52/ACK001: f MAIN ÷2 (n=1)010: f MAIN ÷2 2 (n=2)011: f MAIN ÷2 3 (n=3)100: f MAIN ÷2 4 (n=4)101: f MAIN ÷2 5 (n=5)110: f MAIN ÷2 6 (n=6)111: f MAIN ÷2 7 (n=7)Cautions :Remarks :1. Writing to BRGCR during a communication operation may cause abnormal outputfrom the baud rate generatior and disable further communication operations.Therefore, do not write to BRGCR during a communication operation.1. f SCK : Source clock for 5-bit counter2. f MAIN : Main Oscillation Frequency3. n: Value set via TPS0 to TPS24. k: Value set via MDL0 to MDL35. The baud rate generated from the main system clock is determined according tothe following formula.Baud Rate =f MAIN2 n+1 (k + 16)RXBR0R R R R R R R R7 6 5 4 3 2 1 0BTCLADDRESS: 0BB HINITIAL VALUE: 0000 0000 BUART Receiving Data at Receiving ModeTXSR0W W W W W W W W7 6 5 4 3 2 1 0BTCLADDRESS: 0BB HINITIAL VALUE: 1111 1111 BUART Sending Data at Sending ModeFigure 19-2 Baud Rate Generator Control Register, Receive Buffer Register, Transmit shift RegisterDecember 3, 2012 Ver 1.21 87

MC80F770819.2 Relationship between main clock and baud rateThe transmit/receive clock that is used to generate the baud rateis obtained by dividing the main system clock. Transmit/Receiveclock generation for baud rate is made by using main systemclock which is divided.The baud rate generated from the main system clock is determinedaccording to the following formulaBaudRate =------------------------------------fx2 n + 1 ( K + 16)- fx : main system clock oscillation frequency- n : value set via TPS0 to TPS1(1 ≤ n ≤ 7)- k : value set via MDL0 to MDL3 (0 ≤ n ≤14)Baud Rate(bps)f X = 11.0592M f X = 8.00M f X = 7.3728M f X = 6.00M f X = 5.00M f X = 4.1943BRGCRErr(%)BRGCRErr(%)BRGCRErr(%)BRGCRErr(%)BRGCRTable 19-2 Relationship Between Main Clock and Baud RateErr(%)BRGCR600 - - - - - - - - - - 7BH 1.141,200 - - 7AH 0.16 78H 0.00 73H 2.79 70H 1.73 6BH 1.142,400 72H 0.00 6AH 0.16 68H 0.00 63H 2.79 60H 1.73 5BH 1.144,800 62H 0.00 5AH 0.16 58H 0.00 53H 2.79 50H 1.73 4BH 1.149,600 52H 0.00 4AH 0.16 48H 0.00 43H 2.79 40H 1.73 3BH 1.1419,200 42H 0.00 3AH 0.16 38H 0.00 33H 2.79 30H 1.73 2BH 1.1431,250 36H 0.52 30H 0.00 2DH 1.70 28H 0.00 24H 0.00 21H -1.3038,400 32H 0.00 2AH 0.16 28H 0.00 23H 2.79 20H 1.73 1BH 1.1476,800 22H 0.00 1AH 0.16 18H 0.00 13H 2.79 10H 1.73 - -115,200 18H 0.00 11H 2.12 10H 0.00 - - - - - -Err(%)88 December 3, 2012 Ver 1.21

MC80F770820. OPERATION MODEThe system clock controller starts or stops the main frequencyclock oscillator, which is controlled by systemclock mode register (SCMR). Figure 20-1 shows the operatingmode transition diagram.System clock control is performed by the system clockmode register (SCMR). During reset, this register is initializedto “0” so that the main-clock operating mode is selected.Main Active modeThis mode is fast-frequency operating mode. The CPU andthe peripheral hardwares are operated on the high-frequencyclock. At reset release, this mode is invoked.SLEEP modeIn this mode, the CPU clock stops while peripherals andthe oscillation source continue to operate normally.STOP modeIn this mode, the system operations are all stopped, holdingthe internal states valid immediately before the stop at thelow power consumption level.Main : OscillationSub : OscillationSystem Clock : MainMain : Stop or OscillationSub : OscillationSystem Clock : StopMain ActiveMode* Note2 / * Note3* Note1Stop / SleepMode* Note1 : 1) stop mode admissionLDM SSCR, #5AHSTOP2) sleep mode admissionLDM SSCR, #0FH- Sub clock cannot be stopped by STOP instruction.* Note2 : Stop released byReset, Key ScanWatch Timer interrupt,Timer interrupt (event counter),and External interrupt* Note3 : Sleep released byReset or All interruptsFigure 20-1 Operating Mode20.1 Operation Mode SwitchingShifting from the Normal operation to the SLEEPmodeBy writing “0F H ” into SSCR which will be explained in"21.1 SLEEP Mode" on page 90, the CPU clock stops andthe SLEEP mode is invoked. The CPU stops while otherperipherals are operate normally.The way of release from this mode is RESET and all availableinterrupts.For more detail, See "21.1 SLEEP Mode" on page 90Shifting from the Normal operation to the STOPmodeBy writing “5A H ” into SSCR and then executing STOP instruction,the main-frequency clock oscillation stops andthe STOP mode is invoked. But sub-frequency clock oscillationis operated continuously.After the STOP operation is released by reset, the operationmode is changed to Main active mode.The methods of release are RESET, Key scan interrupt,Watch Timer interrupt, Timer/Event counter1 (EC0 pin)and External Interrupt.For more details, see "21.2 STOP Mode" on page 91.Note: In the STOP and SLEEP operating modes, the powerconsumption by the oscillator and the internal hardwareis reduced. However, the power for the pin interface (dependingon external circuitry and program) is not directlyassociated with the low-power consumption operation. Thismust be considered in system design as well as interfacecircuit design.December 3, 2012 Ver 1.21 89

MC80F770821. POWER DOWN OPERATIONMC80F7708 have 2 power down mode. In power downmode, power consumption is reduced considerably in Batteryoperation that Battery life can be extended a lot.21.1 SLEEP ModeIn this mode, the internal oscillation circuits remain active.Oscillation continues and peripherals are operate normallybut CPU stops. The status of all Peripherals in this mode isshown in Table 21-1. Sleep mode is entered by writing“0F H ” into SSCR (address 0E9 H ).It is released by RESET or all interrupt. To be released byinterrupt, interrupt should be enabled before Sleep mode.Sleep mode is entered by writing “0F H ” into Stop andSleep Control Register(SSCR), and STOP mode is enteredby writing “5A H ” into SSCR and then executing STOP instruction.Stop and Sleep Control RegisterSSCRADDRESS : 0E9 HRESET VALUE : 00 HW W W W W W W W• to enable STOP Mode : 5A H• to enter SLEEP Mode : 0F Hnote1. To get into STOP mode, SSCR must be enabled just beforeSTOP instruction. At STOP mode SSCR register value iscleared automatically.Figure 21-1 SLEEP Mode RegisterOscillator(X IN )Internal CPU Clock~~InterruptSet bit 0 of SMRReleaseNormal Operation Stand-by Mode Normal OperationFigure 21-2 Sleep Mode Release Timing by External Interrupt90 December 3, 2012 Ver 1.21

MC80F7708.Oscillator(X IN )Internal CPU ClockRESETSet bit 0 of SMR~ ~ ~ ~ReleaseBIT Counter 0 1 2 FE FF 0 1 2Clear & Start~~~~ ~Normal Operation Stand-by Mode t ST = 62.5msNormal Operationat 4.19MHz by hardware1t ST = x 256f MAIN ÷1024Figure 21-3 SLEEP Mode Release Timing by RESET pin21.2 STOP ModeFor applications where power consumption is a criticalfactor, this device provides STOP mode for reducing powerconsumption.Start The Stop OperationThe STOP mode can be entered by STOP instruction duringprogram execution. In Stop mode, the on-chip mainfrequencyoscillator, system clock, and peripheral clockare stopped (Watch timer clock is oscillating continuously:.With the clock frozen, all functions are stopped, but theon-chip RAM and Control registers are held. The port pinsoutput the values held by their respective port data registerand the port direction registers. The status of peripheralsduring Stop mode is shown below.Peripheral STOP Mode Sleep ModeCPU All CPU operations are disabled All CPU operations are disabledRAM Retain RetainLCD driver Operates continuously Operates continuouslyBasic Interval Timer Halted Operates continuouslyTimer/Event counter 0Halted (Only when the Event counter modeis enabled, Timer 0 operates normally)Timer/Event counter 0 operates continuouslyWatch Timer Operates continuously Operates continuouslyMain-oscillation Stop (X IN =L, X OUT =L) Oscillation 1Sub-oscillation Oscillation OscillationI/O ports Retain RetainControl Registers Retain RetainRelease methodby RESET, Watch Timer interrupt,Timer interrupt (EC0), and External interruptby RESET, All interrupts1. Refer to the Table 10-2Table 21-1 Peripheral Operation during Power Down ModeDecember 3, 2012 Ver 1.21 91

MC80F7708OperatingClock sourceMainOperating ModeMainSleep ModeNote: Since the X IN pin is connected internally to GND toavoid current leakage due to the crystal oscillator in STOPmode, do not use STOP instruction when an external clockis used as the main system clock.In the Stop mode of operation, V DD can be reduced to minimizepower consumption. Be careful, however, that V DDis not reduced before the Stop mode is invoked, and thatV DD is restored to its normal operating level before theStop mode is terminated.The reset should not be activated before V DD is restored toits normal operating level, and must be held active longenough to allow the oscillator to restart and stabilize.And after STOP instruction, at least two or more NOP instructionshould be written as shown in example below.Example):LDM CKCTLR,#0000_1111BSTOPNOPNOP:Stop ModeMain Clock Oscillation Oscillation StopSub Clock Oscillation Oscillation OscillationSystem Clock Active Stop StopPeri. Clock Active Active Stop 11. Except watch timer(sub clock) and LCD driver(sub clock)Table 21-2 Clock Operation of STOP and SLEEP modeThe Interval Timer Register CKCTLR should be initializedby software in order that oscillation stabilization timeshould be longer than 20ms before STOP mode.Release the STOP modeThe exit from STOP mode is using hardware reset or externalinterrupt, watch timer ortimer interrupt (EC0).To release STOP mode, corresponding interrupt should beenabled before STOP mode.Specially as a clock source of Timer/Event counter, EC0pin can release it by Timer/Event counter Interrupt request.Reset redefines all the control registers but does not changethe on-chip RAM. External interrupts allow both on-chipRAM and Control registers to retain their values.Start-up is performed to acquire the time for stabilizing oscillation.During the start-up, the internal operations are allstopped.Oscillator(X IN pin)~~~Internal ClockExternal Interrupt~~STOP InstructionExecuted~~~BIT Counter n n+1 n+2 n+30~1 FE FF 0 1 2ClearNormal Operation Stop Operation Normal Operationt ST > 20msby software~ ~Before executing Stop instruction, Basic Interval Timer must be setproperly by software to get stabilization time which is longer than 20ms.Figure 21-4 STOP Mode Release Timing by External Interrupt92 December 3, 2012 Ver 1.21

MC80F7708Oscillator(X IN pin)~~~Internal ClockRESETSTOP InstructionExecuted~BIT Counter n n+1 n+2 n+3 n+40Normal Operation~ ~~Stop OperationClear~ ~~ ~1 FE FF 0 1 2t ST > 62.5msNormal Operationat 4.19MHz by hardware1t ST = x 256f MAIN ÷1024Figure 21-5 STOP Mode Release Timing by RESETDecember 3, 2012 Ver 1.21 93

MC80F7708Minimizing Current ConsumptionThe Stop mode is designed to reduce power consumption.To minimize current drawn during Stop mode, the usershould turn-off output drivers that are sourcing or sinkingcurrent, if it is practical.Note: In the STOP operation, the power dissipation associatedwith the oscillator and the internal hardware is lowered;however, the power dissipation associated with thepin interface (depending on the external circuitry and program)is not directly determined by the hardware operationof the STOP feature. This point should be little current flowswhen the input level is stable at the power voltage level(V DD /V SS ); however, when the input level becomes higherthan the power voltage level (by approximately 0.3V), a currentbegins to flow. Therefore, if cutting off the output transistorat an I/O port puts the pin signal into the highimpedancestate, a current flow across the ports input transistor,requiring it to fix the level by pull-up or other means.It should be set properly that current flow through portdoesn't exist.First consider the setting to input mode. Be sure that thereis no current flow after considering its relationship withexternal circuit. In input mode, the pin impedance viewingfrom external MCU is very high that the current doesn’tflow.But input voltage level should be V SS or V DD . Be carefulthat if unspecified voltage, i.e. if uniformed voltage level(not V SS or V DD ) is applied to input pin, there can be littlecurrent (max. 1mA at around 2V) flow.If it is not appropriate to set as an input mode, then set tooutput mode considering there is no current flow. Settingto High or Low is decided considering its relationship withexternal circuit. For example, if there is external pull-up resistorthen it is set to output mode, i.e. to High, and if thereis external pull-down resistor, it is set to low.INPUT PINV DDiXGNDWeak pull-up current flowsinternalpull-upV DDV DDOV DDOPENOINPUT PINiOPENVery weak current flowsXi=0i=0V DDOOWhen port is configured as an input, input level shouldbe closed to 0V or V DD to avoid power consumption.GNDFigure 21-6 Application Example of Unused Input PortOUTPUT PINONOFFONOFF iGNDXONOFFOOIn the left case, much current flows from port to GND.OPENV DDOUTPUT PINV DDV DDLLONOFFOFF iON i=0GNDGNDXOIn the left case, Tr. base current flows from port to GND.To avoid power consumption, there should be low outputto the port.Figure 21-7 Application Example of Unused Output Port94 December 3, 2012 Ver 1.21

MC80F770822. OSCILLATOR CIRCUITThe MC80F7708 have three oscillation circuits internally.X IN and X OUT are input and output for main frequency andSX IN and SX OUT are input and output for sub frequency,respectively, inverting amplifier which can be configuredfor being used as an on-chip oscillator, as shown in Figure22-1.ExampleCrystal OscillatorCeramic ResonatorC1,C2 = 10~30pFC1,C2 = 10~30pF* The example load capacitor value(C1, C2, C3, C4) is common value but maynot be appropriate for some crystal or ceramic resonator.C1C3X OUTSX OUTC24.19MHzX INC432.768kHzSX INV SSV SSCrystal or Ceramic OscillatorExampleC3,C4 = 10 ~ 30pFExternal ClockOpenX OUTX INNo need exteranl componentfor oscillation.(X IN /X OUT pin can be usedas normal I/O pin R43/R42or R43/f sys ÷4)X OUT /R42X IN /R43V SSExternal OscillatorInternal 8MHz/4MHz/2MHzOscillation circuit is designed to be used either with a ceramicresonator or crystal oscillator. Since each crystal andceramic resonator have their own characteristics, the usershould consult the crystal manufacturer for appropriatevalues of external components.Figure 22-1 Oscillation CircuitIn addition, see Figure 22-2 for the layout of the crystal.Note: Minimize the wiring length. Do not allow the wiring tointersect with other signal conductors. Do not allow the wiringto come near changing high current. Set the potential ofthe grounding position of the oscillator capacitor to that ofVSS. Do not ground it to any ground pattern where high currentis present. Do not fetch signals from the oscillator.X OUTX INFigure 22-2 Layout of Oscillator PCB circuitDecember 3, 2012 Ver 1.21 95

MC80F770823. RESETThe MC80F7708 have has four reset generation sources;external reset input, power on reset (POR), built in reset(BIR) and watch-dog timer reset. Table 23-1 shows onchiphardware initialization by reset action.On-chip Hardware Initial Value On-chip Hardware Initial ValueProgram counter (PC) (FFFF H ) - (FFFE H ) Operation mode Main-frequency clockRAM page register (RPR) 0 Peripheral clock OnG-flag (G) 0 Control registers Refer to Table 8-1 on page 28Table 23-1 Initializing Internal Status by Reset ActionRESETNoise CancellerPOR(Power-On Reset)BIR(Built In Reset)SQInternalRESETWDT(WDT Timeout Reset)OverflowRClearBITFigure 23-1 RESET Block Diagram23.1 External Reset InputThe reset input is the RESET pin, which is the input to aSchmitt Trigger. A reset accomplished by holding the RE-SET pin to low for at least 8 oscillator periods, within theoperating voltage range and oscillation stable, it is applied,and the internal state is initialized. After reset, 65.5ms (at4MHz) and 7 oscillator periods are required to start executionas shown in Figure 23-3.Internal User RAM is not affected by reset. When V DD isturned on, the RAM content is indeterminate. Therefore,this RAM should be initialized before read or tested it.When the RESET pin input goes to high, the reset operationis released and the program execution starts at the vectoraddress stored at FFFE H - FFFF H .A connection for normal power-on-reset is shown in Figure23-2.V DDReset ICGNDGND10kΩRESETDD+10uF−VMCUFigure 23-2 Normal Power-on-Reset Circuit96 December 3, 2012 Ver 1.21

MC80F77081 2 3 4 5 6 7System ClockRESETADDRESSBUSDATABUS~ ~ ~ ~ ~ ~? ? ? ? FFFE FFFF Start? ? ? ? FE ADL ADH OPStabilization Timet ST = 65.5mS at 4MHzRESET Process Step1t ST = x 256f MAIN ÷1024MAIN PROGRAMFigure 23-3 Timing Diagram of RESET23.2 Power On ResetThe on-chip POR circuit holds down the device in RESETuntil V DD has reached a high enough level for proper operation.It will eliminate external components such as resetIC or external resistor and capacitor for external reset circuit.In addition that the RESET pin can be used to normalinput port R47 by setting “POR” and “R47EN” bit of theConfiguration option area(20FFH) in Flash programming.When the device starts normal operation, its operatingparmeters (voltage, frequency, temperature...etc) must bemet.Note: When “POR” option is checked and “R47EN” optionis not checked, RESET/R47 pin acts as external Reset inputpin. In this case, the external reset circuit should be connectedto RESET pin. If external reset is not needed, notonly “POR”, but also “R47EN” option should be checked.23.3 Built In ResetRefer to “24. Butil In Reset (BIR)”23.4 Watchdog Timer ResetRefer to “14. WATCH DOG TIMER”December 3, 2012 Ver 1.21 97

MC80F770824. Butil In Reset (BIR)The MC80F7708 has an on-chip BIR(Built In Reset) circuitryto immunize against power noise. The BIR controlregister BIRR can enable or disable the built in reset circuitry.The Block diagram of BIR is shown in the Figure24-1.BIRR (Built In ResetControl Register)MSBLSBR/W R/W R/W R/W R/W R/W R/W R/WBIR_ENB NC_SEL AD_REFB TRM1 TRM0 BIS2 BIS1 BIS0ADDRESS: 0E5 HINITIAL VALUE: 0110_0000 BBIR_ENB (BIR disable)0: BIR Enable1: BIR DisableNC_SEL (Noise Canceller selection)0: 15ns noise canceller operation1: 32us noise canceller operation TRM[1:0] (Detection Level Trim selection)00: DefaultAD_REFB (Disable self-bias check reference)01: Detection Level down (0.17V(TBD))0: Enable self-bias check reference voltage operation10: Detection Level down (0.34V(TBD))1: Disable self-bias check reference voltage operation11: Detection Level up (0.34V(TBD))BIS[2:0] (BIR Detection Level)000: 2V (typical)001: 2.4V (typical)010: 2.5V (typical)011: 2.7V (typical)100: 2.9V (typical)101: 3.2V (typical)110: 3.6V (typical)LBCR (LCD BiasControl Register)MSBLSBR/W R/W R/W R/W R/W R/W R/W R/WCTR_S CTR_DS3 CTR_DS2 CTR_DS1 CTR_DS0 SYS_BIR1 SYS_BIR0 BIFADDRESS : 0B3 HRESET VALUE : 01111000BSYS_BIR (Mode selection of BIR Result)00: Reset mode10: Freeze modeBIF (BIR Flag)0: BIR No Detect1: BIR DetectBIR_ENBTRM0TRM1ResistorArrayLow-LevelVoltageSelectorcomparatorPS7 1MUXSub_CLK 015ns NoiseCanceller32us NoiseCancellerNoiseCancellerSelectorNC_SELOperationmodeSelectorSYS_BIR0Internal ResetSignalFreeze ModeSignalBIR_ENBBIS0BIS1BIS2LCR[7]AD_REFBSYS_BIR1ReferenceVoltageSource+_Self BiasCheck ReferenceFigure 24-1 Block Diagram of BIR (Built-In Reset)98 December 3, 2012 Ver 1.21

MC80F7708The BIR of MC80F7708 has 8 detection level which canbe selected by BIS[2:0] and each level can be trimmed byTRM[1:0].The NC_SEL bit of BIRR is used for selecting BIR noisecanceller. For example, if the NC_SEL bit of BIRR is setto “1” and VDD voltage falls below the BIR detection levelduring 20us, BIR does not generates internal reset signalor freeze mode signal because the 32us noise canceller eleminateslow level detection signal less than 32us.BIR result can be selected by SYS_BIR[1:0] of LBCR register.When SYS_BIR[1:0] is set to “00”, BIR generates resetsingnal. If SYS_BIR[1:0] is set to “10”, it generatesfreeze mode signal and CPU freeze until the VDD voltagereturns to regular level.The self bias check reference, which can be used for calculatingVDD voltage, can be activated by setting theAD_REFB bit to “0” and BIR_ENB bit to “0”. It is usedfor checking VDD voltage.BIF is set to “1” when BIR occurs. It can be used to distinguishreset caused by BIR and other.When the POR is used, the BIR detection level should beset to the level less than POR level. If the POR level is2.4V, BIR level 2V and 2.4V can not operate.RESET VECTORBIF =1NORAM ClearInitialize RAM DataInitialize All PortsInitialize RegistersFunctionExecutionYESBIF = 0Skip theinitial routineFigure 24-2 Example Flow of Reset flow by BIRDecember 3, 2012 Ver 1.21 99

MC80F770825. Osillation Noise ProtectorThe Oscillation Noise Protector (ONP) is used to supplystable internal system clock by excluding the noise whichcould be entered into oscillator and recovery the oscillationfail. This function could be enabled or disabled by the“ONP” bit of the Device configuration area (20FF H ) forthe MC80F7708.The ONP function is like below.- Recovery the oscillation wave crushed or loss causedby high frequency noise.- Change system clock to the internal oscillation clockwhen the high frequency noise is continuing.- Change system clock to the internal oscillation clockwhen the X IN /X OUT is shorted or opened, the mainoscillation is stopped except by stop instruction andthe low frequency noise is entered.XINHF NoiseObserverHF NoiseCanceller1Mux0 SOFPXIN_NFInternalOSCen0CLKChanger1 SINT_CLKF INTERNALONPb = 0LF_on = 1IN_CLK = 0ONPOFPHigh Frq. NoiseLF NoiseObserverenPS10INT_CLK 8 periods(250ns × 8 =2us)CLK_CHGeno/fOFPCK(8-Bit counter)ONPIN8MCLK(XO)IN4MCLK(XO)IN2MCLK(XO)PS10(INT_CLK/512) 256 periods(250ns × 512 × 256 =33 ms)~XINXIN_NFNoise Cancel~Low Frq. Noise orOscillation Fail~~INT_CLK resetINT_CLK~~~ ~ ~OFP_ENCHG_ENDCLK_CHGf INTERNALClock Change Start(XIN to INT_CLK)~~ ~~Clock Change End(INT_CLK to XIN))Figure 25-1 Block Diagram of ONP & OFP and Respective Wave Forms100 December 3, 2012 Ver 1.21

MC80F7708The oscillation fail processor (OFP) can change the clocksource from external to internal oscillator when the oscillationfail occured. This function could be enabled or disabledby the “OFP” bit of the Device Configuration Area(MASK option for MC80F7708).And this function can recover the external clock sourcewhen the external clock is recovered to normal state.The “IN8MCLK”, “IN4MCLK”, “IN2MCLK”,“IN8MCLKXO”, “IN4MCLKXO”, “IN2MCLKXO” optionof the Device Configuration Area enables the functionto operate the device by using the internal oscillator clockin ONP block as system clock. There is no need to connectthe x-tal, resonator, RC and R externally. After selectingthe this option, the period of internal oscillator clock couldbe checked by X OUT outputting clock divided the internaloscillator clock by 4.December 3, 2012 Ver 1.21 101

MC80F770826. FLASH PROGRAMMING SPEC.26.1 FLASH Configuration ByteExcept the user program memory, there is configurationbyte(address 20FF H ) for the selection of program lock,ONP, OPF, oscillation configuration and reset configuration.The configuration byte of FLASH is shown as Figure26-1. It could be served when user use the FLASH programmer.Note: The Configuration Option may not be read exactlywhen VDD rising time is very slow. It is recommended toadjust the VDD rising time faster than 40ms/V (200ms from0V to 5V).Configuration Option Bits7 6 5 4 3 2 1 0ONP OFP LOCK POR R35EN CLK2 CLK1 CLK0ADDRESS: 20FF HINITIAL VALUE: 00 HOscillation confuguration000 : IN4MCLK (Internal 4MHz Oscillation & R42/R43 Enable)001 : IN2MCLK (Internal 2MHz Oscillation & R42/R43 Enable)010 : IN8MCLK (Internal 8MHz Oscillation & R42/R43 Enable)011 : X-tal (Crystal or Resonator Oscillation)100 : IN4MCLKXO (internal 4MHz Oscillation & R42 Enable& XOUT = f SYS ÷ 4)101 : IN2MCLKXO (internal 2MHz Oscillation & R42 Enable& XOUT = f SYS ÷ 4)110 : IN8MCLK (internal 8MHz Oscillation & R42 Enable& XOUT = f SYS ÷ 4)111 : ProhibitedRESET/R47 Port configuration0 : R47 Port Disable (Use RESET)1 : R47 Port Enable (Disable RESET)POR Use0 : Disable POR Reset1 : Enable POR ResetSecurity Bit0 : Enable reading User Code1 : Disable reading User CodeOFP use0 : Disable OFP (Clock Changer)1 : Enable OFP (Clock Changer)ONP disable0 : Enable ONP (Enable OFP, Internal 8MHz/4MHz/2MHz oscillation)1 : Disable ONP (Disable OFP, Internal 8MHZ4MHz/2MHz oscillation)Figure 26-1 The FLASH Configuration Byte26.2 FLASH ProgrammingThe MC80F7708 is a MTP microcontroller. Its internal usermemory is constructed with FLASH ROM..Blank FLASH’s internal memory is filled by 00 H , not FF H .Note: In any case, you have to use the *.OTP file for programming,not the *.HEX file. After assemble, both OTPand HEX file are generated by automatically. The HEX fileis used during program emulation on the emulator.How to ProgramTo program the FLASH or MTP devices, user can use ABOVown programmer.ABOV own programmer listManufacturer: ABOV Semiconductor Programmer:Choice-SigmaStandAlone-Gang4PGM-plusThe Choice-Sigma is a ABOV Universal Single Programmer for102 December 3, 2012 Ver 1.21

MC80F7708all of ABOV FLASH/OTP devices, also the StandAlone-Gang4can program four FLASH/OTPs at once for ABOV device.Ask to ABOV sales part for purchasing or more detail.Programming Procedure1. Select device MC80F7708.2. Load the *.OTP file from the PC. The file is composedof Motorola-S1 format.3. Set the programming address range as below table.AddressSet ValueBuffer start addressE000 HBuffer end addressFFFF HDevice start addressE000 H4. Mount the socket adapter on the programmer.5. Start program/verify.December 3, 2012 Ver 1.21 103

MC80F770827. EMULATOR EVA. BOARD SETTINGCHOICE-Dr. EVA80F77 B/D Rev1.0 S/N_________Ext.-OSCX1RESETSW1SLEEP32.768kHzX2STOPRUNPOWERVR2VR11 2 3 4 5SW4ONU3J_USER_CCONNECTASW2CONNECTCADCPWRRESET(Only Pin) N.CRESETR47/R47XOUT(Only Pin) N.CXOUTR42/R42SXINR45/R45SXOUT R46/R46MDS12 3 456 7 8ONE_VCCT_VCCT_RSTRESETT_XOUTXOUTSXinSXOUTHMSMC80077_EVAABOVU2CONNECTBV_USERSW3USERPOWER_SEL.J_USER_B J_USERAJ_USER_B J_USER_AREMOUTVCL3AVCCSEG43SEG42VCL2SEG41SEG40VCL1SEG39SEG38RESET/R47SEG37SEG36SXIN/R45SEG35SEG34XIN/R43SEG33SEG32INT2/R41SEG31SEG30SDA/R17SEG29SEG28EC2/R15R87/SEG37SEG26/R86SI/R13R85/SEG25SEG24/R84SCK/R11R83/SEG23SEG22/R82INT1/R07R81/SEG21SEG20/R80EC1/R03R77/COM0COM1/R76RX1/R03R75/COM2COM3/R74EC0/R01R73/SEG19/COM4COM5/SEG18/R72AN7/R27R71/SEG17/COM6COM7SEG16/R70AN5/R25R67/SEG15SEG14/R66AN3/R23R65/SEG13SEG12/R64AN1/R21R63/SEG11SEG10/R62KS7/R37R61/SEG9SEG8/R60KS5/R35R57/SEG7SEG6/R56KS3/R33R55/SEG5SEG4/R54KS1/R31R53/SEG3SEG2/R52/ACKT_/RSTTX0/R51/SEG1SEG0/R50/RX0GNDAVCCVLCDCVCL0SXOUT/R46INT3/R44XOUT/R42R40SCL/R16T4O/PWM2/R14SOUT/R12T2O/PWM1/R10INT0/R06BUZZ/R04TX1/R02T0O/PWM0/R00AN6/R26AN4/R24AN2/R22AN0/R20KS6/R36KS4/R34KS2/R32KS0/R30T_XOUTGND* J_USEC_C is reserved for further use, Unused in MC80F7708.104 December 3, 2012 Ver 1.21

MC80F770828. IN-SYSTEM PROGRAMMING28.1 Getting Started / InstallationThe In-System Programming (ISP) is performed withoutremoving the microcontroller from the system. The In-System Programming(ISP) facility consists of a series ofinternal hardware resources coupled with internal firmwarethrough the serial port. The In-System Programming(ISP) facility has made in-circuit programming in an embeddedapplication possible with a minimum of additionalexpense in components and circuit board area. The followingsection details the procedure for accomplishing the installationprocedure.1. Power off a target system.2. Configure a target system as ISP mode.Refer to “28.3 Hardware Conditions to Enter the ISP Mode”3. Attach a ISP B/D into a target system.4. Connect the serial (RS-232C) cable between a ISPboard and available serial port of your PC.5. Power on a target system.6. Run the ABOV ISP software.Download the ISP S/W from www.abov.co.kr.Unzip the download file and run ISP_800.exe7. Select a COM port and a device in the ISP S/W.Figure 28-1 ISP softwareDecember 3, 2012 Ver 1.21 105

MC80F770828.2 Basic ISP S/W InformationThe Figure 28-1 is the ISP software based on Windows TM .This software is only supporting devices with UART.Main feature is automatically to search baudrates in rangeFunctionTable 28-2. In case of not detecting its baudrates an usermanually have to select specific baudrates.DescriptionLoad HEX FileSave HEX FileBlank CheckProgramReadVerifyEraseOption SelectionOption WriteAUTOEdit BufferFill BufferGotoDetected SystemOSC.Start ______End ______ChecksumCOM PortSelected OSC.Select DeviceLoad the data from the selected file storage into the memory buffer.Save the current data in your memory buffer to a disk storage by using the Intel Motorola HEXformat.Verify whether or not a device is in an erased or unprogrammed state.This button enables you to place new data from the memory buffer into the target device.Read the data in the target MCU into the buffer for examination. The checksum will be displayedon the checksum box.Assures that data in the device matches data in the memory buffer. If your device is secured, averification error is detected.Erase the data in your target MCU before programming it.Set the configuration data of target MCU. The security locking is set with this button.Progam the configuration data of target MCU. The security locking is performed with this button.Following sequence is performed ; 1.Erase 2.Program 3.Verify 4.Option WriteModify the data in the selected address in your buffer memoryFill the selected area with a data.Display the selected page.Display user system clock which is detected in Auto baud rate mode.Starting addressEnd addressDisplay the checksum(Hexdecimal) after reading the target device.Select a serial port.Specify your target oscillator value with discarding below point in ACK mode only.Select target device.Table 28-1 ISP Function Description106 December 3, 2012 Ver 1.21

MC80F770828.3 Hardware Conditions to Enter the ISP ModeThe boot loader can be executed by holding ALE high, RE-SET/V PP as +9V, and ACLK0(optional) with OSC.1.8432MHz. The ISP function uses following pins: TxD0,RxD0, ALEB, ACLK and RESET/V PP ..User target reset circuitryRESET/V PPX-TAL2MHz~12MHzRx DataTx DataACLK0V DD (+5V)+9V(ISP_V PP )123R01/ALE 2V DDV SSX OUTX INRESET/V PPR50 / RX0R51 / TX0R52 / ACK456789101112131415161718192021MC80F7708K424140393837363534333231302928272625242322ISP_V PPTx Data 1Rx Data 1ACLK 4 (No)V SSISP_V PP47KΩ 3 (optional)V DD (+5V)ISP board1. If other signals affect UART communiction in ISP mode, disconnect these pins by using a jumper or a switch.2. The ALE can be shared with other function. Toggle the port between ISP and user mode.3. The pull down resister is optional. If user set to ISP Mode without connection ISP board, the Vpp/Reset Port is in floating state.The pull down resistor is for blocking this undefined state.Do not power on a application B/D in ISP mode without connecting a ISP board.4. Refer to the section 29.4 explaining the auto baudrate.Auto baudrate mode is not supported at MC80F7708December 3, 2012 Ver 1.21 107

MC80F770828.4 Sequence to enter ISP mode/user modeSequence to enter ISP mode from user mode.X INV DDResetISP modemin.10us 64ms@4MHz2 ~ 12MHz1. Power off a target system.2. Configure a target system as ISP mode.3. Attach a ISP B/D into a target system.4. Run the ISP S/W and Select Device.5. Power on a target system.V PPALElogic highSequence to enter user mode from ISP mode.Figure 28-2 Timing diagram to enter the ISP mode1. Close the ISP S/W..2. Power off a target system.3. Configure a target system as user mode4. Detach a ISP B/D from a target system.5. Power on.28.5 Difference between auto baud rate and ACK modeAuto Baud Rate Mode(No Use)The ISP S/W detects user system clock and MCU configure abaud rate automatically. This mode does not need to connect theACK pin of target MCU to ISP B/D. But the MC80F7708 doesnot support this mode.ACK modeIf the ISP S/W can not detect user system clock, users have to entera user system clock. This mode is only used when failed to detectuser system clock automatically.Note: Need to connect the ACK pin to ISP B/D.The mode supported with devices is shown in Table 28-2 .Auto Baud RatemodeACK modeMC80F0204 - OMC80F0224 O OMC80F0448 O OMC80F7708 - OTable 28-2 Supported modes according to devices108 December 3, 2012 Ver 1.21

MC80F770828.6 Reference ISP Circuit Diagram and ABOV Supplied ISP BoardThe ISP software and hardware circuit diagram are providedat www.abov.co.kr.To get a ISP B/D, contact to sales department. The followingcircuit diagram is for reference use.CON1Female DB9From PC162738495V DD (+5V)147V DD (+5V)T1OUTT2OUTMAX232T1INT2IN11101kΩV DD (+5V)2N2907V DD (+5V)1312R1IN R1OUTRxD8R2IN R2OUT9J2RESET/V2PP 1+1V+ C1+VTxD+SS V SS MCU_TxD 21uF 163 1uF3VCC C1-22ΩMCU_RxD 4DTR+ 64V-C2+5+1uFACLK_CLK 61551uFGND22ΩGND C2-V SS V SSV SS V SSNote1)8.2kΩ100pF10kΩ100Ω10uF/35V100pF+V SSV SSTo MCUV DDV SSJ3+10uF/16V0.1uF22ΩX1Vcc Out22Ω* V DD : +4.5 ~ +5.5V* V PP : V DD + 4VV SS0.1uFGndOSC1.8432MHzExternal V DDV SSV SSThe ragne of V DD must be from 4.5 to 5.5V and ISP function is not supported under 2MHz system clock.If the user supplied V DD is out of range, the external power is needed instead of the target system V DD .For the ISP operation, power consumption required is minimum 30mA.Note1) This block is only for ACK mode. If the auto baud rate is enabled, this circuit is not needed.Figure 28-3 Reference ISP Circuit DiagramFigure 28-4 ISP board supplied by ABOVDecember 3, 2012 Ver 1.21 109

MC80F7708110 December 3, 2012 Ver 1.21

MC80F7708APPENDIXDecember 3, 2012 Ver 1.21i

MC80F7708A. INSTRUCTIONA.1 Terminology ListTerminologyDescriptionAAccumulatorXX - registerYY - registerPSWProgram Status Word#imm8-bit Immediate datadpDirect Page Offset Address!absAbsolute Address[ ] Indirect expression{ } Register Indirect expression{ }+ Register Indirect expression, after that, Register auto-increment.bitBit PositionA.bitBit Position of Accumulatordp.bitBit Position of Direct Page MemoryM.bit Bit Position of Memory Data (000 H ~0FFF H )relRelative Addressing DataupageU-page (0FF00 H ~0FFFF H ) Offset Addressn Table CALL Number (0~15)+ Additionxy−Subtraction0Bit Position1Bit Position× Multiplication/ Division( ) Contents Expression∧AND∨OR⊕Exclusive OR~ NOT←Assignment / Transfer / Shift Left→Shift Right↔Exchange= Equal≠Not EqualUpper Nibble Expression in OpcodeUpper Nibble Expression in Opcodeii December 3, 2012 Ver 1.21

MC80F7708December 3, 2012 Ver 1.21iiiA.2 Instruction MapLOWHIGH0000000000010100010020001103001000400101050011006001110701000080100109010100A010110B011000C011010D011100E011110F000 -SET1dp.bitBBSA.bit,relBBSdp.bit,relADC#immADCdpADCdp+XADC!absASLAASLdpTCALL0SETA1.bitBITdpPOPAPUSHABRK001 CLRC “ “ “SBC#immSBCdpSBCdp+XSBC!absROLAROLdpTCALL2CLRA1.bitCOMdpPOPXPUSHXBRArel010 CLRG “ “ “CMP#immCMPdpCMPdp+XCMP!absLSRALSRdpTCALL4NOT1M.bitTSTdpPOPYPUSHYPCALLUpage011 DI “ “ “OR#immORdpORdp+XOR!absRORARORdpTCALL6OR1OR1BCMPXdpPOPPSWPUSHPSWRET100 CLRV “ “ “AND#immANDdpANDdp+XAND!absINCAINCdpTCALL8AND1AND1BCMPYdpCBNEdp+XTXSPINCX101 SETC “ “ “EOR#immEORdpEORdp+XEOR!absDECADECdpTCALL10EOR1EOR1BDBNEdpXMAdp+XTSPXDECX110 SETG “ “ “LDA#immLDAdpLDAdp+XLDA!absTXALDYdpTCALL12LDCLDCBLDXdpLDXdp+YXCNDAS(N/A)111 EI “ “ “LDMdp,#immSTAdpSTAdp+XSTA!absTAXSTYdpTCALL14STCM.bitSTXdpSTXdp+YXAXSTOPLOWHIGH1000010100011110010121001113101001410101151011016101111711000181100119110101A110111B111001C111011D111101E111111F000BPLrelCLR1dp.bitBBCA.bit,relBBCdp.bit,relADC{X}ADC!abs+YADC[dp+X]ADC[dp]+YASL!absASLdp+XTCALL1JMP!absBIT!absADDWdpLDX#immJMP[!abs]001BVCrel“ “ “SBC{X}SBC!abs+YSBC[dp+X]SBC[dp]+YROL!absROLdp+XTCALL3CALL!absTEST!absSUBWdpLDY#immJMP[dp]010BCCrel“ “ “CMP{X}CMP!abs+YCMP[dp+X]CMP[dp]+YLSR!absLSRdp+XTCALL5MULTCLR1!absCMPWdpCMPX#immCALL[dp]011BNErel“ “ “OR{X}OR!abs+YOR[dp+X]OR[dp]+YROR!absRORdp+XTCALL7DBNEYCMPX!absLDYAdpCMPY#immRETI100BMIrel“ “ “AND{X}AND!abs+YAND[dp+X]AND[dp]+YINC!absINCdp+XTCALL9DIVCMPY!absINCWdpINCYTAY101BVSrel“ “ “EOR{X}EOR!abs+YEOR[dp+X]EOR[dp]+YDEC!absDECdp+XTCALL11XMA{X}XMAdpDECWdpDECYTYA110BCSrel“ “ “LDA{X}LDA!abs+YLDA[dp+X]LDA[dp]+YLDY!absLDYdp+XTCALL13LDA{X}+LDX!absSTYAdpXAYDAA(N/A)111BEQrel“ “ “STA{X}STA!abs+YSTA[dp+X]STA[dp]+YSTY!absSTYdp+XTCALL15STA{X}+STX!absCBNEdpXYXNOP

MC80F7708A.3 Instruction SetArithmetic / Logic OperationOP BYTE CYCLENO. MNEMONICCODE NO NO1 ADC #imm 04 2 22 ADC dp 05 2 33 ADC dp + X 06 2 44 ADC !abs 07 3 45 ADC !abs + Y 15 3 56 ADC [ dp + X ] 16 2 67 ADC [ dp ] + Y 17 2 68 ADC { X } 14 1 39 AND #imm 84 2 2Add with carry.A ← ( A ) + ( M ) + C10 AND dp 85 2 311 AND dp + X 86 2 41213AND !absAND !abs + Y87953345Logical ANDA ← ( A ) ∧ ( M )14 AND [ dp + X ] 96 2 615 AND [ dp ] + Y 97 2 616 AND { X } 94 1 317 ASL A 08 1 2 Arithmetic shift left18 ASL dp 09 2 419 ASL dp + X 19 2 520 ASL !abs 18 3 521 CMP #imm 44 2 222 CMP dp 45 2 323 CMP dp + X 46 2 424 CMP !abs 47 3 425 CMP !abs + Y 55 3 526 CMP [ dp + X ] 56 2 627 CMP [ dp ] + Y 57 2 628 CMP { X } 54 1 329 CMPX #imm 5E 2 230 CMPX dp 6C 2 331 CMPX !abs 7C 3 432 CMPY #imm 7E 2 2OPERATIONC 7 6 5 4 3 2 1Compare accumulator contents with memory contents( A ) - ( M )Compare X contents with memory contents( X ) - ( M )Compare Y contents with memory contents( Y ) - ( M )FLAGNVGBHIZCNV--H-ZCN-----Z-N-----ZCN-----ZCN-----ZC33 CMPY dp 8C 2 3N-----ZC34 CMPY !abs 9C 3 435 COM dp 2C 2 4 1’S Complement : ( dp ) ← ~( dp ) N-----Z-36 DAA DF 1 3 Decimal adjust for addition N-----ZC37 DAS CF 1 3 Decimal adjust for subtraction N-----ZC38 DEC A A8 1 239 DEC dp A9 2 440 DEC dp + X B9 2 5 Decrement41 DEC !abs B8 3 5 M ← ( M ) - 1N-----Z-42 DEC X AF 1 243 DEC Y BE 1 244 DIV 9B 1 12 Divide : YA / X Q: A, R: Y NV--H-Z-0“0”iv December 3, 2012 Ver 1.21

MC80F7708OP BYTE CYCLENO. MNEMONICCODE NO NO45 EOR #imm A4 2 246 EOR dp A5 2 347 EOR dp + X A6 2 448 EOR !abs A7 3 449 EOR !abs + Y B5 3 550 EOR [ dp + X ] B6 2 651 EOR [ dp ] + Y B7 2 652 EOR { X } B4 1 353 INC A 88 1 2Exclusive ORA ← ( A ) ⊕ ( M )N-----Z-65 OR dp 65 2 366 OR dp + X 66 2 46768OR !absOR !abs + Y67753345Logical ORA ← ( A ) ∨ ( M )69 OR [ dp + X ] 76 2 670 OR [ dp ] + Y 77 2 671 OR { X } 74 1 372 ROL A 28 1 2 Rotate left through carry73 ROL dp 29 2 4C 7 6 5 4 3 2 174 ROL dp + X 39 2 575 ROL !abs 38 3 576 ROR A 68 1 2 Rotate right through carry77 ROR dp 69 2 478 ROR dp + X 79 2 579 ROR !abs 78 3 580 SBC #imm 24 2 281 SBC dp 25 2 382 SBC dp + X 26 2 483 SBC !abs 27 3 484 SBC !abs + Y 35 3 585 SBC [ dp + X ] 36 2 686 SBC [ dp ] + Y 37 2 687 SBC { X } 34 1 388 TST dp 4C 2 389 XCN CE 1 57 6 5 4 3 2 1Subtract with carryA ← ( A ) - ( M ) - ~( C )OPERATION54 INC dp 89 2 455 INC dp + X 99 2 5 Increment56 INC !abs 98 3 5 M ← ( M ) + 1N-----Z-57 INC X 8F 1 258 INC Y 9E 1 259 LSR A 48 1 2 Logical shift right60 LSR dp 49 2 47 6 5 4 3 2 1 0 C61 LSR dp + X 59 2 5“0”N-----ZC62 LSR !abs 58 3 563 MUL 5B 1 9 Multiply : YA ← Y × A N-----Z-64 OR #imm 64 2 2N-----Z-N-----ZCN-----ZCNV--HZCExchange nibbles within the accumulatorA 7 ~A 4 ↔ A 3 ~A 000 CFLAGNVGBHIZCTest memory contents for negative or zero( dp ) - 00 HN-----Z-N-----Z-December 3, 2012 Ver 1.21v

MC80F7708Register / Memory OperationOP BYTE CYCLENO. MNEMONICCODE NO NO1 LDA #imm C4 2 22 LDA dp C5 2 33 LDA dp + X C6 2 44 LDA !abs C7 3 45 LDA !abs + Y D5 3 56 LDA [ dp + X ] D6 2 67 LDA [ dp ] + Y D7 2 68 LDA { X } D4 1 3Load accumulatorA ← ( M )OPERATIONFLAGNVGBHIZCN-----Z-9 LDA { X }+ DB 1 4 X- register auto-increment : A ← ( M ) , X ← X + 110 LDM dp,#imm E4 3 5 Load memory with immediate data : ( M ) ← imm --------11 LDX #imm 1E 2 212 LDX dp CC 2 3 Load X-register13 LDX dp + Y CD 2 4 X ← ( M )N-----Z-14 LDX !abs DC 3 415 LDY #imm 3E 2 216 LDY dp C9 2 3 Load Y-register17 LDY dp + X D9 2 4 Y ← ( M )N-----Z-18 LDY !abs D8 3 419 STA dp E5 2 420 STA dp + X E6 2 521 STA !abs E7 3 522 STA !abs + Y F5 3 6Store accumulator contents in memory23 STA [ dp + X ] F6 2 7( M ) ← A --------24 STA [ dp ] + Y F7 2 725 STA { X } F4 1 426 STA { X }+ FB 1 4 X- register auto-increment : ( M ) ← A, X ← X + 127 STX dp EC 2 428 STX dp + Y ED 2 5Store X-register contents in memory29 STX !abs FC 3 5( M ) ← X--------30 STY dp E9 2 431 STY dp + X F9 2 5Store Y-register contents in memory32 STY !abs F8 3 5( M ) ← Y--------33 TAX E8 1 2 Transfer accumulator contents to X-register : X ← A N-----Z-34 TAY 9F 1 2 Transfer accumulator contents to Y-register : Y ← A N-----Z-35 TSPX AE 1 2 Transfer stack-pointer contents to X-register : X ← sp N-----Z-36 TXA C8 1 2 Transfer X-register contents to accumulator: A ← X N-----Z-37 TXSP 8E 1 2 Transfer X-register contents to stack-pointer: sp ← X N-----Z-38 TYA BF 1 2 Transfer Y-register contents to accumulator: A ← Y N-----Z-39 XAX EE 1 4 Exchange X-register contents with accumulator :X ↔ A --------40 XAY DE 1 4 Exchange Y-register contents with accumulator :Y ↔ A --------41 XMA dp BC 2 5 Exchange memory contents with accumulator42 XMA dp+X AD 2 6 ( M ) ↔ AN-----Z-43 XMA {X} BB 1 544 XYX FE 1 4 Exchange X-register contents with Y-register : X ↔ Y --------vi December 3, 2012 Ver 1.21

MC80F770816-BIT OperationNO.MNEMONICOPCODEBYTENOCYCLENO1 ADDW dp 1D 2 516-Bits add without carryYA ← ( YA ) + ( dp +1 ) ( dp )OPERATIONFLAGNVGBHIZCNV--H-ZC2 CMPW dp 5D 2 4Compare YA contents with memory pair contents :(dp+1)(dp)(YA) −N-----ZC3 DECW dp BD 2 6Decrement memory pair( dp+1)( dp) ← ( dp+1) ( dp) - 1N-----Z-4 INCW dp 9D 2 6Increment memory pair( dp+1) ( dp) ← ( dp+1) ( dp ) + 1N-----Z-5 LDYA dp 7D 2 5Load YAYA ← ( dp +1 ) ( dp )N-----Z-6 STYA dp DD 2 5Store YA( dp +1 ) ( dp ) ← YA--------7 SUBW dp 3D 2 516-Bits substact without carryYA ← ( YA ) - ( dp +1) ( dp)NV--H-ZCBit Manipulation22 TCLR1 !abs 5C 3 623 TSET1 !abs 3C 3 6Test and clear bits with A :A - ( M ) , ( M ) ← ( M ) ∧ ~( A )Test and set bits with A :A - ( M ) , ( M ) ← ( M ) ∨ ( A )NO. MNEMONICOP BYTE CYCLEFLAGOPERATIONCODE NO NONVGBHIZC1 AND1 M.bit 8B 3 4 Bit AND C-flag : C ← ( C ) ∧ ( M .bit ) -------C2 AND1B M.bit 8B 3 4 Bit AND C-flag and NOT : C ← ( C ) ∧ ~( M .bit ) -------C3 BIT dp 0C 2 4 Bit test A with memory :4 BIT !abs 1C 3 5 Z ← ( A ) ∧ ( M ) , N ← ( M 7 ) , V ← ( M 6 )MM----Z-5 CLR1 dp.bit y1 2 4 Clear bit : ( M.bit ) ← “0” --------6 CLRA1 A.bit 2B 2 2 Clear A bit : ( A.bit )← “0” --------7 CLRC 20 1 2 Clear C-flag : C ← “0” -------08 CLRG 40 1 2 Clear G-flag : G ← “0” --0-----9 CLRV 80 1 2 Clear V-flag : V ← “0” -0--0---10 EOR1 M.bit AB 3 5 Bit exclusive-OR C-flag : C ← ( C ) ⊕ ( M .bit ) -------C11 EOR1B M.bit AB 3 5 Bit exclusive-OR C-flag and NOT : C ← ( C ) ⊕ ~(M .bit) -------C12 LDC M.bit CB 3 4 Load C-flag : C ← ( M .bit ) -------C13 LDCB M.bit CB 3 4 Load C-flag with NOT : C ← ~( M .bit ) -------C14 NOT1 M.bit 4B 3 5 Bit complement : ( M .bit ) ← ~( M .bit ) --------15 OR1 M.bit 6B 3 5 Bit OR C-flag : C ← ( C ) ∨ ( M .bit ) -------C16 OR1B M.bit 6B 3 5 Bit OR C-flag and NOT : C ← ( C ) ∨ ~( M .bit ) -------C17 SET1 dp.bit x1 2 4 Set bit : ( M.bit ) ← “1” --------18 SETA1 A.bit 0B 2 2 Set A bit : ( A.bit ) ← “1” --------19 SETC A0 1 2 Set C-flag : C ← “1” -------120 SETG C0 1 2 Set G-flag : G ← “1” --1-----21 STC M.bit EB 3 6 Store C-flag : ( M .bit ) ← C --------N-----Z-N-----Z-December 3, 2012 Ver 1.21vii

MC80F7708Branch / Jump OperationNO. MNEMONICOP BYTE CYCLECODE NO NOOPERATION1 BBC A.bit,rel y2 2 4/6 Branch if bit clear :2 BBC dp.bit,rel y3 3 5/7 if ( bit ) = 0 , then pc ← ( pc ) + rel3 BBS A.bit,rel x2 2 4/6 Branch if bit set :4 BBS dp.bit,rel x3 3 5/7 if ( bit ) = 1 , then pc ← ( pc ) + rel5 BCC rel 50 2 2/46 BCS rel D0 2 2/4Branch if carry bit clearif ( C ) = 0 , then pc ← ( pc ) + relBranch if carry bit setif ( C ) = 1 , then pc ← ( pc ) + rel7 BEQ rel F0 2 2/4Branch if equalif ( Z ) = 1 , then pc ← ( pc ) + rel8 BMI rel 90 2 2/4Branch if minusif ( N ) = 1 , then pc ← ( pc ) + rel9 BNE rel 70 2 2/4Branch if not equalif ( Z ) = 0 , then pc ← ( pc ) + rel10 BPL rel 10 2 2/4Branch if minusif ( N ) = 0 , then pc ← ( pc ) + rel11 BRA rel 2F 2 4Branch alwayspc ← ( pc ) + rel12 BVC rel 30 2 2/4Branch if overflow bit clearif (V) = 0 , then pc ← ( pc) + rel13 BVS rel B0 2 2/4Branch if overflow bit setif (V) = 1 , then pc ← ( pc ) + rel14 CALL !abs 3B 3 8 Subroutine call15 CALL [dp] 5F 2 8M( sp)←( pc H ), sp←sp - 1, M(sp)← (pc L ), sp ←sp - 1,if !abs, pc← abs ; if [dp], pc L ← ( dp ), pc H ← ( dp+1 ) .16 CBNE dp,rel FD 3 5/7 Compare and branch if not equal :17 CBNE dp+X,rel 8D 3 6/8 if ( A ) ≠ ( M ) , then pc ← ( pc ) + rel.18 DBNE dp,rel AC 3 5/7 Decrement and branch if not equal :19 DBNE Y,rel 7B 2 4/6 if ( M ) ≠ 0 , then pc ← ( pc ) + rel.20 JMP !abs 1B 3 321Unconditional jumpJMP [!abs] 1F 3 5pc ← jump address22 JMP [dp] 3F 2 423 PCALL upage 4F 2 624 TCALL n nA 1 8U-page callM(sp) ←( pc H ), sp ←sp - 1, M(sp) ← ( pc L ),sp ← sp - 1, pc L ← ( upage ), pc H ← ”0FF H ” .Table call : (sp) ←( pc H ), sp ← sp - 1,M(sp) ← ( pc L ),sp ← sp - 1,pc L ← (Table vector L), pc H ← (Table vector H)FLAGNVGBHIZC----------------------------------------------------------------------------------------------------------------------------------------viii December 3, 2012 Ver 1.21

MC80F7708Control Operation & Etc.NO.MNEMONICOPCODEBYTENOCYCLENOOPERATIONFLAGNVGBHIZC1 BRK 0F 1 8Software interrupt : B ← ”1”, M(sp) ← (pc H ), sp ←sp-1,M(s) ← (pc L ), sp ← sp - 1, M(sp) ← (PSW), sp ← sp -1, ---1-0--pc L ← ( 0FFDE H ) , pc H ← ( 0FFDF H ) .2 DI 60 1 3 Disable interrupts : I ← “0” -----0--3 EI E0 1 3 Enable interrupts : I ← “1” -----1--4 NOP FF 1 2 No operation --------5 POP A 0D 1 4sp ← sp + 1, A ← M( sp )6 POP X 2D 1 4 sp ← sp + 1, X ← M( sp )--------7 POP Y 4D 1 4 sp ← sp + 1, Y ← M( sp )8 POP PSW 6D 1 4 sp ← sp + 1, PSW ← M( sp )restored9 PUSH A 0E 1 4M( sp ) ← A , sp ← sp - 110 PUSH X 2E 1 4 M( sp ) ← X , sp ← sp - 111 PUSH Y 4E 1 4 M( sp ) ← Y , sp ← sp - 1--------12 PUSH PSW 6E 1 4 M( sp ) ← PSW , sp ← sp - 113 RET 6F 1 5Return from subroutinesp ← sp +1, pc L ← M( sp ), sp ← sp +1, pc H ← M( sp )--------14 RETI 7F 1 6Return from interruptsp ← sp +1, PSW ← M( sp ), sp ← sp + 1,pc L ← M( sp ), sp ← sp + 1, pc H ← M( sp )restored15 STOP EF 1 3 Stop mode ( halt CPU, stop oscillator ) --------December 3, 2012 Ver 1.21ix