MC80F7708 - abov.co.kr

MC80F770811. BASIC INTERVAL TIMERThe MC80F7708 have one 8-bit Basic Interval Timer thatis free-run and can not stop. Block diagram is shown inFigure 11-1.The Basic Interval Timer Register (BITR) is increased everyinternal count pulse which is divided by prescaler.Since prescaler has division ratio from 8 to 1024, the countrate is 1/8 to 1/1024 of the oscillator frequency. After reset,the BCK bits are all set, so the longest oscillation stabilizationtime is obtained.It also provides a Basic interval timer interrupt (BITF).The count overflow of BITR from FF H to 00 H causes theinterrupt to be generated. The Basic Interval Timer is controlledby the clock control register (CKCTLR) shown inFigure 11-2.Source clock can be selected by lower 3 bits of CKCTLR.When write “1” to bit BCL of CKCTLR, BITR register iscleared to “0” and restart to count up. The bit BCL becomes“0” automatically after one machine cycle by hardware.BITR and CKCTLR are located at same address, and address0E6 H is read as a BITR, and written to CKCTLR.f SUBf MAIN ÷2 3f MAIN ÷2 4f MAIN ÷2 5f MAIN ÷2f MAIN ÷2 7f MAIN ÷2 8f MAIN ÷2 9f MAIN ÷2 10MUXsourceclock8-bit up-counter1BITR0[0E6 H ]SELSUB clearoverflowBITIFBasic Interval Timer InterruptSelect Input clock 3BCKf MAIN : main-clock frequencyf SUB : sub-clock frequency [0E6 H ]Basic Interval Timerclock control registerCKCTLRBCLInternal bus lineFigure 11-1 Block Diagram of Basic Interval TimerBCK000001010011100101110111Source clockSCMR[1:0] = 00 or 01Interrupt (overflow) PeriodAt f MAIN = 4MHzf MAIN ÷2 30.512 msf MAIN ÷2 41.024f MAIN ÷2 52.048f MAIN ÷2 64.096f MAIN ÷2 78.192f MAIN ÷2 816.384f MAIN ÷2 932.768f MAIN ÷2 10 65.536Table 11-1 Basic Interval Timer Interrupt Time42 December 3, 2012 Ver 1.21