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MC80F7708 - abov.co.kr

MC80F7708 - abov.co.kr

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<strong>MC80F7708</strong>T0 (Timer0 Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0T07 T06 T05 T04 T03 T02 T01 T00ADDRESS: 0D1 HINITIAL VALUE:00HCDR0 (Timer0 Input Capture Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0CDR07 CDR06 CDR05 CDR04 CDR03 CDR02 CDR01 CDR00ADDRESS: 0D1 HINITIAL VALUE:00HIn Timer mode, this register is the value of Timer 0 <strong>co</strong>unter and in Capture mode, this register is the value of input capture.TDR0 (Timer 0 Data Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0TDR07 TDR06 TDR05 TDR04 TDR03 TDR02 TDR01 TDR00If the <strong>co</strong>unter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.T1 (Timer1 Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0T17 T16 T15 T14 T13 T12 T11 T10ADDRESS: 0D1 HINITIAL VALUE:FF HADDRESS: 0D4 HINITIAL VALUE:00HCDR1 (Timer1 Input Capture Register)R R R R R R R RBit : 7 6 5 4 3 2 1 0CDR17 CDR16 CDR15 CDR14 CDR13 CDR12 CDR11 CDR10ADDRESS: 0D4 HINITIAL VALUE:00 HIn Timer mode, this register is the value of Timer 1 <strong>co</strong>unter and in Capture mode, this register is the value of input capture.TDR1 (Timer1 Data Register)W W W W W W W WBit : 7 6 5 4 3 2 1 0TDR17 TDR16 TDR15 TDR14 TDR13 TDR12 TDR11 TDR10If the <strong>co</strong>unter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.ADDRESS: 0D3 HINITIAL VALUE:FF HFigure 12-2 Related Registers with Timer/Counter0, 146 December 3, 2012 Ver 1.21

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