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Discrete time model checking of Timed- Arc Petri nets

Discrete time model checking of Timed- Arc Petri nets

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Project DetailsThe tool TAPAAL is created for verification <strong>of</strong> real-<strong>time</strong> systems — that is we canexpress timing constraints with real values. However <strong>of</strong>ten we don’t need the fullpower <strong>of</strong> real values to do <strong>model</strong> <strong>checking</strong>. A folklore result says that given the rightconstraints we can use integer values instead <strong>of</strong> real values when preforming verification.This is <strong>of</strong>ten called discrete <strong>time</strong>.This project will explore one <strong>of</strong> both <strong>of</strong> the following directions. Implement a integer<strong>time</strong> <strong>model</strong> <strong>checking</strong> engine for TAPAAL and/or prove the correctness <strong>of</strong> this folkloreresult.A successful project will (among other) include:• A survey <strong>of</strong> recent development in the area <strong>of</strong> automated verification <strong>of</strong> real-<strong>time</strong>systems,• pro<strong>of</strong> <strong>of</strong> the correctness <strong>of</strong> discrete <strong>time</strong>,• experimental results comparing the discrete <strong>time</strong> approtch to TAPAAL currentverification engine.• a code contribution that can be used in TAPAAL.The project can be adjusted to more theoretical (theory and algorithms) or practicallevel (algorithms and tools) according your wishes.In case that interesting results are achieved you are expected to contribute in transformingthese results into a conference/workshop paper suitable for publication.For more information or questions contact Kenneth Yrke Joergensen and agree on an informal meeting.2


Evaluation <strong>of</strong> real-<strong>time</strong> <strong>model</strong> <strong>checking</strong>toolsIntroduction to formal verificationWhen creating a computer system we want to avoid creating bugs. The predominantmethod to avoid bugs in industry is by testing the s<strong>of</strong>tware. Model <strong>checking</strong> is a formalmethod that builds on a mathematical foundation for proving the absence or presences<strong>of</strong> bugs in a system. Model <strong>checking</strong> is performed by creating a <strong>model</strong> <strong>of</strong> the system ina formal description language. We can input this <strong>model</strong> into a <strong>model</strong> <strong>checking</strong> tool toverify properties about the system. Properties can be questions like: will this systemreach a deadlock, can we always avoid this particular bad situation and, if we allow<strong>time</strong> in our <strong>model</strong>, does event B happen exactly 10 <strong>time</strong> units before event A.You can read more about <strong>model</strong> <strong>checking</strong> at: http://en.wikipedia.org/wiki/Model_<strong>checking</strong>TAPAALTAPAAL is a verification tool for a <strong>model</strong> called <strong>Timed</strong>-<strong>Arc</strong> <strong>Petri</strong> <strong>nets</strong> (TAPN).TAPN is a interesting <strong>model</strong> because it can capture many features <strong>of</strong> real-<strong>time</strong> systemswhile still preserving intuitive understanding and simple notation. TAPAAL is develophere at Aalborg University in 2008/2009.The tool TAPAAL features a:• graphical tool for <strong>model</strong>ling <strong>of</strong> TAPN,• a graphical simulator <strong>of</strong> TAPN and• a automatic verifier for TAPNTAPAAL is today actively develop by a development team <strong>of</strong> 5 students and employeesat Aalborg University.You can read more about TAPAAL at www.tapaal.net1


Project DetailsFigure 1: Screenshot <strong>of</strong> the TAPAAL guiThis project will compare a number <strong>of</strong> different real-<strong>time</strong> <strong>model</strong> <strong>checking</strong> tools to comparedifferent parameters such as: tool usability, tool performance and <strong>model</strong>ing power,by <strong>model</strong>ling one or more algorithms (eg. mutual exclusions or networks algorithms)The result would be a survey describing the strengths and weaknesses <strong>of</strong> the differenttools, and possible propose and implement ideas for the development <strong>of</strong> TAPAAL.A successful project will (among other) include:• A survey <strong>of</strong> recent development in the area <strong>of</strong> automated verification <strong>of</strong> real-<strong>time</strong>systems,• <strong>model</strong>ling and verification <strong>of</strong> a algorithm in several state-<strong>of</strong>-the-art <strong>model</strong> <strong>checking</strong>tools,• a comparison <strong>of</strong> <strong>model</strong> <strong>checking</strong> tools summarising strengths and weaknesses <strong>of</strong>the different tools,• experimental results comparing the different <strong>model</strong> checkers and• a number <strong>of</strong> ideas for changes/features to TAPAAL and possibly the implementation<strong>of</strong> some <strong>of</strong> these into TAPAAL.The project can be adjusted to more theoretical (theory and algorithms) or practicallevel (algorithms and tools) according your wishes.In case that interesting results are achieved you are expected to contribute in transformingthese results into a conference/workshop paper suitable for publication.2


For more information or questions contact Kenneth Yrke Joergensen and agree on an informal meeting.3


Verifying stateful <strong>time</strong>d CSPusing UPPAALIntroduction to formal verificationWhen creating a computer system we want to avoid creating bugs. The predominantmethod to avoid bugs in industry is by testing the s<strong>of</strong>tware. Model <strong>checking</strong> is a formalmethod that builds on a mathematical foundation for proving the absence or presences<strong>of</strong> bugs in a system. Model <strong>checking</strong> is performed by creating a <strong>model</strong> <strong>of</strong> the system ina formal description language. We can input this <strong>model</strong> into a <strong>model</strong> <strong>checking</strong> tool toverify properties about the system. Properties can be questions like: will this systemreach a deadlock, can we always avoid this particular bad situation and, if we allow<strong>time</strong> in our <strong>model</strong>, does event B happen exactly 10 <strong>time</strong> units before event A.You can read more about <strong>model</strong> <strong>checking</strong> at: http://en.wikipedia.org/wiki/Model_<strong>checking</strong>Stateful <strong>Timed</strong> CSPIn 2009 Jun Sun et.al. introduced the notion <strong>of</strong> Stateful <strong>Timed</strong> CSP as a <strong>model</strong> for ahigh-level description computer systems that include timing constraints. The languageintroduces several high level therms such as deadline, <strong>time</strong> out, and <strong>time</strong>d interrupt,to eliminate human errors that can made when using low level description languages.The verification <strong>of</strong> Stateful <strong>Timed</strong> CSP has been implemented into the authors own<strong>model</strong> <strong>checking</strong> tool PAT.Figure 1: Example <strong>of</strong> the Stateful <strong>Timed</strong> CSP languageProject DetailsAlthough PAT is a fast developing real-<strong>time</strong> <strong>model</strong> checker, the <strong>model</strong> checker UPPAAL(developed partly in Aalborg) is still considered one <strong>of</strong> the best and fastest <strong>model</strong>checkers. The project would consist <strong>of</strong> adding support <strong>of</strong> ”Stateful <strong>Timed</strong> CSP” in1


UPPAAL by creating a tool to translate Stateful <strong>Timed</strong> CSP into networks <strong>of</strong> <strong>time</strong>dautomata that can be verified by UPPAAL. The goal would be to directly compare thetwo <strong>model</strong> <strong>checking</strong> tools.A successful project will (among other) include:• An algorithms translating from Stateful <strong>Timed</strong> CSP to networks <strong>of</strong> <strong>time</strong>d automata,• a prototype tool for translating (a subset <strong>of</strong>) Stateful <strong>Timed</strong> CSP into <strong>Timed</strong>Automata,• pro<strong>of</strong> <strong>of</strong> the correctness <strong>of</strong> the translation, and• experimental results comparing verification <strong>time</strong> between PAT and UPPAAL.The project can be adjusted to more theoretical (theory and algorithms) or practicallevel (algorithms and tools) according your wishes.In case that interesting results are achieved you are expected to contribute in transformingthese results into a conference/workshop paper suitable for publication.For more information or questions contact Kenneth Yrke Joergensen and agree on an informal meeting.2


New TAPAAL verification engineIntroduction to formal verificationWhen creating a computer system we want to avoid creating bugs. The predominantmethod to avoid bugs in industry is by testing the s<strong>of</strong>tware. Model <strong>checking</strong> is a formalmethod that builds on a mathematical foundation for proving the absence or presences<strong>of</strong> bugs in a system. Model <strong>checking</strong> is performed by creating a <strong>model</strong> <strong>of</strong> the system ina formal description language. We can input this <strong>model</strong> into a <strong>model</strong> <strong>checking</strong> tool toverify properties about the system. Properties can be questions like: will this systemreach a deadlock, can we always avoid this particular bad situation and, if we allow<strong>time</strong> in our <strong>model</strong>, does event B happen exactly 10 <strong>time</strong> units before event A.You can read more about <strong>model</strong> <strong>checking</strong> at: http://en.wikipedia.org/wiki/Model_<strong>checking</strong>TAPAALTAPAAL is a verification tool for a <strong>model</strong> called <strong>Timed</strong>-<strong>Arc</strong> <strong>Petri</strong> <strong>nets</strong> (TAPN).TAPN is a interesting <strong>model</strong> because it can capture many features <strong>of</strong> real-<strong>time</strong> systemswhile still preserving intuitive understanding and simple notation. TAPAAL is develophere at Aalborg University in 2008/2009.The tool TAPAAL features a:• graphical tool for <strong>model</strong>ling <strong>of</strong> TAPN,• a graphical simulator <strong>of</strong> TAPN and• a automatic verifier for TAPNTAPAAL is today actively develop by a development team <strong>of</strong> 5 students and employeesat Aalborg University.You can read more about TAPAAL at www.tapaal.netProject DetailsThe tool TAPAALs verification engine works by translating problems into somethinga verification engine can understand. At the moment the engine used in TAPAAL iscalled UPPAAL. However there exists many other tools that might be suitable as theverification engine for TAPAAL. TAPAAL architecture makes it easy to change theverification engine to try out other <strong>model</strong> checkers. The task world be to choose a tooland try it out as a new verification engine for TAPAAL.A successful project will (among other) include:1


• A survey <strong>of</strong> recent development in the area <strong>of</strong> automated verification <strong>of</strong> real-<strong>time</strong>systems,• A translation from TAPN to the chosen new engine and possibly pro<strong>of</strong> <strong>of</strong> correctness<strong>of</strong> the translation,• experimental results comparing the new and old verification engines for TAPAALand• a code contribution that can be used directly in TAPAAL.The project can be adjusted to more theoretical (theory and algorithms) or practicallevel (algorithms and tools) according your wishes.In case that interesting results are achieved you are expected to contribute in transformingthese results into a conference/workshop paper suitable for publication.For more information or questions contact Kenneth Yrke Joergensen and agree on an informal meeting.2

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