Discrete time model checking of Timed- Arc Petri nets

More documents

Recommendations

Info

Verifying stateful timed CSPusing UPPAALIntroduction to formal verificationWhen creating a computer system we want to avoid creating bugs. The predominantmethod to avoid bugs in industry is by testing the software. Model checking is a formalmethod that builds on a mathematical foundation for proving the absence or presencesof bugs in a system. Model checking is performed by creating a model of the system ina formal description language. We can input this model into a model checking tool toverify properties about the system. Properties can be questions like: will this systemreach a deadlock, can we always avoid this particular bad situation and, if we allowtime in our model, does event B happen exactly 10 time units before event A.You can read more about model checking at: http://en.wikipedia.org/wiki/Model_checkingStateful Timed CSPIn 2009 Jun Sun et.al. introduced the notion of Stateful Timed CSP as a model for ahigh-level description computer systems that include timing constraints. The languageintroduces several high level therms such as deadline, time out, and timed interrupt,to eliminate human errors that can made when using low level description languages.The verification of Stateful Timed CSP has been implemented into the authors ownmodel checking tool PAT.Figure 1: Example of the Stateful Timed CSP languageProject DetailsAlthough PAT is a fast developing real-time model checker, the model checker UPPAAL(developed partly in Aalborg) is still considered one of the best and fastest modelcheckers. The project would consist of adding support of ”Stateful Timed CSP” in1
UPPAAL by creating a tool to translate Stateful Timed CSP into networks of timedautomata that can be verified by UPPAAL. The goal would be to directly compare thetwo model checking tools.A successful project will (among other) include:• An algorithms translating from Stateful Timed CSP to networks of timed automata,• a prototype tool for translating (a subset of) Stateful Timed CSP into TimedAutomata,• proof of the correctness of the translation, and• experimental results comparing verification time between PAT and UPPAAL.The project can be adjusted to more theoretical (theory and algorithms) or practicallevel (algorithms and tools) according your wishes.In case that interesting results are achieved you are expected to contribute in transformingthese results into a conference/workshop paper suitable for publication.For more information or questions contact Kenneth Yrke Joergensen and agree on an informal meeting.2
Page 2 and 3: Project DetailsThe tool TAPAAL is c
Page 4 and 5: Project DetailsFigure 1: Screenshot
Page 8 and 9: New TAPAAL verification engineIntro

Discrete time model checking of Timed- Arc Petri nets

Create successful ePaper yourself

Delete template?

Save as template?