Compal confidential - Data Sheet Gadget

54321Strap Pin TableCFG[2:0] FSB Freq select010 = FSB 800MHz011 = FSB 667MHzOthers = ReservedDCBFor Crestline:2.4kohmFor Calero: 1.5Kohm17ENABLT+3VS17 LCD_CLK17 LCD_DATA17 ENAVDD+3VS2R5516161616161617171717171717171717171717171717BKLT_CTRLENABLTR53 1 2 10K_0402_5%R54 1 2 10K_0402_5%LCD_CLKLCD_DATAENAVDDLVDSB0-LVDSB1-LVDSB2-LVDSAC-LVDSAC+LVDSBC-LVDSBC+LVDSAC-LVDSAC+LVDSBC-LVDSBC+LVDSA0-LVDSA1-LVDSA2-LVDSA0+LVDSA1+LVDSA2+LVDSB0+LVDSB1+LVDSB2+TV_COMPSTV_LUMATV_CRMAR56CRT_BCRT_GCRT_R16 3VDDCCL16 3VDDCDA16 CRT_HSYNC16 CRT_VSYNC12.4K_0402_1%2.2K_0402_5%1 2LVDSA0-LVDSA1-LVDSA2-LVDSA0+LVDSA1+LVDSA2+LVDSB0-LVDSB1-LVDSB2-LVDSB0+LVDSB1+LVDSB2+TV_COMPSTV_LUMATV_CRMACRT_BCRT_GCRT_R3VDDCCL3VDDCDACRT_HSYNCCRT_VSYNC1.3K_0402_1%12R57U3CJ40L_BKLT_CTRLH39L_BKLT_ENE39L_CTRL_CLKE40L_CTRL_DATAC37L_DDC_CLKD35L_DDC_DATAK40L_VDD_ENL41LVDS_IBGL43LVDS_VBGN41LVDS_VREFHN40LVDS_VREFLD46LVDSA_CLK#C45LVDSA_CLKD44LVDSB_CLK#E42LVDSB_CLKG51LVDSA_DATA#_0E51LVDSA_DATA#_1F49LVDSA_DATA#_2G50LVDSA_DATA_0E50LVDSA_DATA_1F48LVDSA_DATA_2G44LVDSB_DATA#_0B47LVDSB_DATA#_1B45LVDSB_DATA#_2E44LVDSB_DATA_0A47LVDSB_DATA_1A45LVDSB_DATA_2E27TVA_DACG27TVB_DACK27TVC_DACF27TVA_RTNJ27TVB_RTNL27TVC_RTNM35TV_DCONSEL_0P33TV_DCONSEL_1H32CRT_BLUEG32CRT_BLUE#K29CRT_GREENJ29CRT_GREEN#F29CRT_REDE29CRT_RED#K33CRT_DDC_CLKG35CRT_DDC_DATAF33CRT_HSYNCC32CRT_TVO_IREFE33CRT_VSYNCCRESTLINE_1p0LVDSPCI-EXPRESS GRAPHICSTV VGAPEG_COMPIPEG_COMPOPEG_RX#_0PEG_RX#_1PEG_RX#_2PEG_RX#_3PEG_RX#_4PEG_RX#_5PEG_RX#_6PEG_RX#_7PEG_RX#_8PEG_RX#_9PEG_RX#_10PEG_RX#_11PEG_RX#_12PEG_RX#_13PEG_RX#_14PEG_RX#_15PEG_RX_0PEG_RX_1PEG_RX_2PEG_RX_3PEG_RX_4PEG_RX_5PEG_RX_6PEG_RX_7PEG_RX_8PEG_RX_9PEG_RX_10PEG_RX_11PEG_RX_12PEG_RX_13PEG_RX_14PEG_RX_15PEG_TX#_0PEG_TX#_1PEG_TX#_2PEG_TX#_3PEG_TX#_4PEG_TX#_5PEG_TX#_6PEG_TX#_7PEG_TX#_8PEG_TX#_9PEG_TX#_10PEG_TX#_11PEG_TX#_12PEG_TX#_13PEG_TX#_14PEG_TX#_15PEG_TX_0PEG_TX_1PEG_TX_2PEG_TX_3PEG_TX_4PEG_TX_5PEG_TX_6PEG_TX_7PEG_TX_8PEG_TX_9PEG_TX_10PEG_TX_11PEG_TX_12PEG_TX_13PEG_TX_14PEG_TX_15N43M43J51L51N47T45T50U40Y44Y40AB51W49AD44AD40AG46AH49AG45AG41J50L50M47U44T49T41W45W41AB50Y48AC45AC41AH47AG49AH45AG42N45U39U47N51R50T42Y43W46W38AD39AC46AC49AC42AH39AE49AH44M45T38T46N50R51U43W42Y47Y39AC38AD47AC50AD43AG39AE50AH43PEGCOMPR5224.9_0402_1%1 2PEGCOMP trace widthand spacing is 20/25 mils.+VCCPCFG5 (DMI select)CFG6CFG7 (CPU Strap)CFG8 (Low power PCIE)CFG9(PCIE Graphics Lane Reversal)CFG[11:10]CFG[13:12] (XOR/ALLZ)CFG[15:14]CFG16 (FSB Dynamic ODT)CFG[18:17]SDVO_CTRLDATACFG19 (DMI Lane Reversal)CFG20 (PCIE/SDVO concurrent)CFG[17:3] have internal pull upCFG[19:18] have internal pull down0 = DMI x 21 = DMI x 4Reserved0 = Reserved1 = Mobile CPU0 = Normal mode1 = Low Power mode0 = Reverse Lane1 = Normal OperationReserved00 = Reserved01 = XOR Mode Enabled10 = All Z Mode Enabled11 = Normal Operation(Default)Reserved0 = Disabled1 = Enabled*****Reserved0 = No SDVO Device Present1 = SDVO Device Present0 = Normal Operation(Lane number in Order)1 = Reverse Lane0 = Only PCIE or SDVO is operational.1 = PCIE/SDVO are operating simu.****DCBFor Crestline:1.3kohmFor Calero: 255ohmAAhttp://hobi-elektronika.net54Security ClassificationCompal Secret DataIssued Date2007/03/26 Deciphered Date2006/03/10THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.32TitleCompal Electronics, Inc.CRESTLINE((3/6)-VGA/LVDS/TVSize Document Number RevCustom LA-3732P 1.0Date: Monday, July 09, 2007Sheet 9 of 421