A New low power Technology for Power Reduction in SRAM's using ...

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ISSN 2249-6343International Journal of Computer Technology and Electronics Engineering (IJCTEE)Volume 2, Issue 3, June 20128T SRAM layoutCharacteristic waveform for Virtual GroundingEmbedded SRAMCharacteristic waveform for 8T SRAMOur Proposed design combined with 8T & Virtualgrounding conceptVirtual Grounding Embedded SRAMOur Proposed layout combined with 8T & Virtualgrounding conceptVirtual Grounding Embedded SRAM layoutCharacteristic waveform for our proposed layoutcombined with 8T & Virtual grounding concept.143
ISSN 2249-6343International Journal of Computer Technology and Electronics Engineering (IJCTEE)Volume 2, Issue 3, June 2012V. CONCLUSIONOur proposed design shows that much less powerthan the existing ones. 1.76uw at the standard Our Proposedlayout combined with 8T & Virtual grounding concept50nm technology. And it is having much reduced area thanthe conventional SRAM designs. Thus this design can beused for future SRAM core memories.[10] Wang, X., Roy, S., and Asenov, A., Impact of Strainon the Performance of high-k/metal replacement gateMOSFETs, in Proc. 10th Ultimate Integration onSilicon (ULIS 2009). 2009.AUTHOR‟S PROFILE:-P.Sreenivasulu 1 Asst. professor Dept of E.C.E,Dr.S.G.I.T, , Markapur,Prakasam(Dist),India 1VI. REFERENCES[1] Kevin, Z., Embedded Memories for Nano-Scale VLSIs.2009: Springer Publishing Company, Incorporated. 400.[2] Brown, A.R., Roy, G., and Asenov, A., Poly-Si-Gate-Related Variability in Decananometer MOSFETs WithConventional Architecture. Electron Devices, IEEETransactions on, 2007. 54(11): p. 3056-3063.G.V.K.varaprasad swamy2 Final M Tech Student(DECS), Dept of E.C.E,S.G.I.T, Markapur,Prakasam(Dist)IndiaM.V.Narrasimha reddy 3 Final M Tech Student (DECSDept of E.C.E,S.G.I.T, Markapur 2 , Prakasam(Dist) India[3] Bo, Z., et al. A Sub-200mV 6T SRAM in 0.13um CMOS.in Solid-State Circuits Conference, 2007. ISSCC 2007.Digest of Technical Papers. IEEE International. 2007.[4] Cheng, B., Roy, S., Roy, G., Brown, A., and Asenov, A.Impact of Random Dopant Fluctuation on Bulk CMOS6-T SRAM Scaling. in Solid-State Device ResearchConference, 2006. ESSDERC 2006. Proceeding of the36th European. 2006.[5] Jawar Singh, D.K.P., Simon Hollis, and Saraju P.Mohanty, A single ended 6T SRAM cell design for ultralow-voltageapplications. IEICE Electronics Express,2008. 5(18): p. 750-755.[6] Mizuno, H. and T. Nagano, Driving source-line cellarchitecture for sub-1-V high-speed low-powerapplications. Solid-State Circuits, IEEE Journal of,1996. 31(4): p. 552-557.[7] Takeda, K., et al., A read-static-noise-margin-freeSRAM cell for low-VDD and high-speed applications.Solid-State Circuits, IEEE Journal of, 2006. 41(1): p.113-121.[8] Chang, L., et al., An 8T-SRAM for VariabilityToleranceand Low-Voltage Operation in High-PerformanceCaches. Solid-State Circuits, IEEE Journal of, 2008.43(4): p. 956-963.[9] Tae-Hyoung, K., et al. A High-Density SubthresholdSRAM with Data-Independent Bitline Leakage andVirtual Ground Replica Scheme. in Solid-State CircuitsConference, 2007. ISSCC 2007. Digest of TechnicalPapers. IEEE International. 2007.144
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