Tiled Matrix Multiplication lecture 21 jan 2013.pdf

More documents

Recommendations

Info

Breaking Md and Nd into Tiles• Break up the innerproduct loop of eachthread into phases• At the beginning of eachphase, load the Md andNd elements thateveryone needs duringthe phase into sharedmemory• Everyone access the Mdand Nd elements from theshared memory duringthe phaseNd 1,0 Nd 0,0Nd 0,1 Nd 1,1Nd 0,2 Nd 1,2Nd 0,3 Nd 1,3Md 0,0 Md 1,0 Md 2,0 Md 3,0 Pd 0,0 Pd 1,0 Pd 2,0 Pd 3,0Md 0,1 Md 1,1 Md 2,1 Md 3,1 Pd 0,1 Pd 1,1 Pd 2,1 Pd 3,1Pd 0,2 Pd 1,2 Pd 2,2 Pd 3,2Pd 0,3 Pd 1,3 Pd 2,3 Pd 3,34
Each phase of a Thread Block uses onetile from Md and one from NdPhase 1 Phase 2Step 4 Step 5 Step 6T 0,0 Md 0,0↓Mds 0,0Nd 0,0 PValue 0,0 +=↓ Mds 0,0 *Nds 0,0 +NdsMds 1,0 *Nds 0,10,0Md 2,0↓Mds 0,0Nd 0,2 PValue 0,0 +=↓ Mds 0,0 *Nds 0,0 +NdsMds 1,0 *Nds 0,10,0T 1,0 Md 1,0↓Mds 1,0Nd 1,0 PValue 1,0 += Md 3,0↓ Mds 0,0 *Nds 1,0 + ↓NdsMds 1,0 *Nds 1,1 1,0Mds 1,0Nd 1,2↓Nds 1,0PValue 1,0 +=Mds 0,0 *Nds 1,0 +Mds 1,0 *Nds 1,1T 0,1 Md 0,1 Nd 0,1 PdValue 0,1 += Md 2,1 Nd 0,3↓ ↓ Mds 0,1 *Nds 0,0 + ↓ ↓Mds 0,1 NdsMds 1,1 *Nds 0,1 0,1 Mds 0 , 1T 1,1 Md 1,1 Nd 1,1 PdValue 1,1 += Md 3,1↓ ↓ Mds 0,1 *Nds 1,0 + ↓Mds 1,1 NdsMds 1,1 *Nds 1,1 1,1Mds 1,1Nds 0,1Nd 1,3↓Nds 1,1PdValue 0,1 +=Mds 0,1 *Nds 0,0 +Mds 1,1 *Nds 0,1PdValue 1,1 +=Mds 0,1 *Nds 1,0 +Mds 1,1 *Nds 1,1time5
Page 1 and 2: TILE_WIDTHETILE_WIDTHTILE_WIDTHTile
Page 3: Every Md and Nd Element is usedexac
Page 7 and 8: CUDA Code - Kernel ExecutionConfigu
Page 9 and 10: TILE_WIDTHETILE_WIDTHTILE_WIDTHTile
Page 11 and 12: Tiling Size Effectstile do n lytile

Tiled Matrix Multiplication lecture 21 jan 2013.pdf

Create successful ePaper yourself

Delete template?

Save as template?