A Detailed Model for a Thyristor Based Static Transfer Switch

1A Detailed Model for a Thyristor Based StaticTransfer SwitchM.N. Moschakis, N.D. Hatziargyriou, Senior Member, IEEEAbstract--Industrial customers often suffer from supply voltageinterruptions and sags due to the increase in the utilization ofsensitive equipment in the process automation and control. Aneffective way to improve power quality and reliability of sensitivecustomers is to use a Static Transfer Switch. This device enables avery fast change in the supply of the customer to an alternatefeeder providing adequate power conditioning for several powerquality problems, such as voltage sags, swells and interruptions.In this paper, an analytical model of STS is proposed and itsperformance is verified using the ElectroMagnetic Transients forDC(EMTDC) simulation package. Simulations using this modelare performed in order to handle voltage sags based on realmeasurements on an actual industrial customer’s supply voltage.Different phase angles and magnitudes of the two alternate sourcepre-fault voltages and different fault instances are considered.Index Terms—Bus transfer, power conditioning, powerquality, power system simulation, sensitive loads, static transferswitch, voltage sags.I. INTRODUCTIONhe increasing sensitivity of consumer equipment, haveT given rise to growing interest concerning the “quality" ofthe electric power. Voltage sags of even low magnitude andshort duration can cause financial losses to industrialcustomers due to process down-time, lost production, idlework forces and other factors[1]. There is a growing need,therefore, for power conditioning devices that will act very fastresulting in mild voltage sags of minimum durationexperienced by the load. Many devices based on PowerElectronics Technology have been proposed and applied inmany cases where mitigation of voltage sags is needed. TheStatic Transfer Switch(STS), the Dynamic VoltageRestorer(DVR), the Distribution STAtic COMpensator(DSTATCOM), the Static Var Compensator(SVC) and theSolid State Tap Changer(SSTC) are the most used devices.One of the most effective solutions from the aforementionedis the Static Transfer Switch(STS). If an alternate feeder existsor can be provided to the critical load at reasonable cost, STScan transfer quickly enough the voltage supply to an alternatesource and sensitive load experiences only a shallow sag ofA Detailed Model for a Thyristor Based Static Transfer switch.M. N. Moschakis is with the Department of Electrical and ComputerEngineering, National Technical University of Athens, Athens, Greece,(e-mail: mosxakis@power.ece.ntua.gr).N. D. Hatziargyriou is with the Department of Electrical and ComputerEngineering, National Technical University of Athens, Athens, Greece,(e-mail: nh@power.ece.ntua.gr).short duration. Obviously, STS is not effective in the event ofa utility complete outage and cannot provide powerconditioning, if both feeders sag in voltage simultaneously, asmight be the case for a fault near the point where the twofeeders join[2].The voltage sag magnitude(VSM) and duration(VSD) at theload terminals, depend directly on the STS control scheme.Hence, voltage detection and transfer need to be as fast aspossible. Furthermore, transfer and gating logic must assurethat in no case paralleling of the sources will occur, whichwould cause severe damage to thyristor switches. Detectionand transfer schemes have already been proposed andexperimentally tested[4] under the assumption of almost zerodifference in phase angle and magnitude between preferredand alternate source pre-fault voltages. The effect of fault typeand severity, the effect of regenerative loads on the transfertime(TT), and the maximum transfer time, have also beendiscussed[5]-[7], under the same assumptions.In actual practice, however, two feeders can have a quitelarge difference in voltage phase angles and a small differencein magnitudes. In this paper, a voltage detection method and atransfer strategy are proposed taking into account thesedifferences. STS performance at the terminals of an actualindustrial customer in Greece suffering from voltage sags, isevaluated by simulations in EMTDC[11]. Real measurementsat the load supply voltage terminals are used to verify theperformance of the STS model. In every case studied,minimum, maximum and average values of detectiontime(DT), TT, VSM and VSD, are calculated.II. STS STRUCTUREA. Power circuit of the STSThe three-phase model of a STS is shown in Figure 1. Itconsists of two thyristor blocks at the P(referred) andA(lternate) source, which connect the load to the two alternatesources. Each thyristor block is composed of three thyristormodules corresponding to the three phases of the system. Ineach thyristor module, two sets of thyristor switches areconnected in opposite directions, e.g. PP1/PN1 and AP1/AN1,to allow the load current to flow in both positive and negativedirections. Mechanical bypass switches Pb and Ab are used inparallel with the thyristor blocks A and P, respectively tosupply the load, even if the thyristor switches are out ofoperation. Isolator switches M1p / M1a and M2p / M2a arealso used to isolate the thyristor blocks from the rest of the

2system for maintenance of thyristor modules and testpurposes[4].Fig. 1. Static transfer switchB. Control circuit of the STSThe control circuit of the proposed STS is shown in Figure2. It consists of two parts: the voltage detection circuit and thecommutation-gating circuit. The control circuit takes as inputthe voltage magnitudes of the two feeders and performs a loadtransferwhen needed. When a deviation from the pre-set limitson the preferred source is detected, a transfer signal isgenerated. Index 1shows that transfer to the alternate source iseffected, while index 0 shows transfer to the preferred source.When the conditions for a safe commutation at each phaseseparately are fulfilled, load is completely transferred to thealternate source, until the voltage on the preferred source isrestored. For the transfer to the preferred source, current zerocrossingis only detected. The outputs of the control circuit arethe pulses for the preferred and alternate source thyristorswitches[4].B1. Voltage detection strategyThe proposed voltage detection circuit is presented inFigure 3. It is very simple and easy to implement and has beenproved to be very accurate and fast, even in the case of ashallow sag.The instant phase voltages are digitally sampled(samplingfrequency=10 kHz) and the rms value is calculated by squaringand integrating the produced signal using the circuit shown inFigure 3a. A second order transfer functions is used to enable afast response of the calculated rms voltage to any voltagefluctuations, as shown in Figure 3b. By taking the minimum ofthe three rms phase voltages, the response becomes evenfaster. Next, the deviation from the preset referencevoltage(e.g. 1.0 pu) is compared to a tolerance limit(here it hasbeen set to 10%[11]). When the voltage on the preferredsource is within tolerance, control logic turns on thecorresponding thyristors. Power then can flow from thepreferred source to the load. If voltage deviates from thetolerance limit, the control logic checks the voltage of thealternate source. If the alternate source voltage is withintolerance limits, the load is transferred to the alternate source,otherwise, it does not issue any changes in the feeding sourceof the load. When the voltage on the preferred source returnsto acceptable values, load is transferred back to the preferredsource after a time delay(a few cycles are enough) to ensurethat preferred source phase voltages are perfectly restored.Fig. 3a. Rms meterFig. 3b. Voltage detection circuit configurationFig. 2. Control circuit configuration of the STS

3B.2 Commutation and gating strategyA fast and safe commutation of the preferred sourcethyristor switches for every phase, depends directly on therelative position and magnitude of three variables when avoltage sag is detected:1. Preferred source instant phase voltage (e.g. Va_p(t) )2. Alternate source instant phase voltage (e.g. Va_a(t) )3. Preferred source instant line current (e.g. Ia_p(t) )Subsequently, transfer time is directly related to thefollowing parameters:• The phase angle difference between the pre-fault phasevoltages of the two alternate sources. This may bebetween 0 and 40 0 depending on the line impedance andthe active and reactive power transferred to the load.• The pre-fault voltage magnitude of the alternate source.• The load power factor, which determines the position ofthe current with respect to the voltage on the preferredsource[7].• The severity of the fault which determines the value of theinstant voltage on the preferred source when a transfersignal is initiated[7].• The phase angle jump the fault introduces.• The post-fault phase voltages, thus the type of the fault[7].• The instant at which the fault occurs[7].Hence, the commutation from one source to another requiressome critical conditions to be fulfilled(Figure 2), in order toenable fast transferring to alternate source and to avoid falseswitching off of thyristor switches. This would lead to a crosscurrent flowing through an outgoing(incoming) thyristor ofone phase of the alternate source and through anincoming(outgoing) thyristor of a corresponding phase of thepreferred source, which will feed the fault current[6].Furthermore, turn-off time of thyristor switches is not constantbut depends on manufacturer’s specifications, voltage level,natural conditions(e.g. temperature), reapplied dv/dt, reapplieddi/dt and gate bias during the turn-off interval[8]. This meansthat a reverse voltage must be kept for a certain amount of timein order to assure successful commutation of thyristorswitches.Therefore, a transfer strategy which will take into accountthe relative position and magnitude of corresponding instantphase voltages of the two alternate sources and correspondinginstant line current on the preferred source, is needed.Transferring does not always occur simultaneously for everyphase. Each phase has to wait for one of the followingconditions to become true in order to initiate transferring:I. A) The three aforementioned variables are of the same signandB) The instantaneous difference in absolute voltagemagnitude(e.g. |Va_p(t)| - |Va_a(t)|) is larger than a certainlimit ΔV1 min , in order to give thyristor switch, whichconducts at that moment, enough time to turn off. Anexample where condition A initiates transferring on phase -a is depicted in Figure 4a. Fault occurs at t=0.028 s, transfersignal is generated(voltage sag is detected) at t=0.032 s andtransferring(only for phase - a) is initiated at t=0.0325 s.Thyristor PP1 is forced to turn off by turning on thyristorAP1(figure 1). It can be seen that Deblock Signal(dblk_altsrc_a), which enables firing pulses of alternatephase –a thyristor switches, is delayed for a short time inorder to assure that voltage difference is within the presetlimit. Furthermore, as expected, the two instant phasevoltages become equal when alternate source phase –athyristor AP1 is fired, until thyristor PP1 is completelyturned-off. In this particular case, a smaller difference ininstantaneous voltages ( |Va_p(t)| - |Va_a(t)| ) might havebeen able to lead to a safe commutation of thyristor switch.However, in a different case (Figure 4b), this smallerdifference would lead to a high cross current becausethyristor switch PP1 would not have enough time to turnoff. Fault occurs at t=0.028 s and transfer signal as well astransferring are initiated at t= 0.0295 s. Thyristor PP1 isforced to turn off by turning on thyristor AP1(figure 1), butgiven time is not enough. Eventually, PP1 does not turn offand when AN1 is turned on, a large current(about 3 timeslarger than in normal operation) flows from the alternatesource through AN1 and PP1 feeding the fault locatedupwards the load on the preferred source. Hence, a certainvalue in voltage difference needs to be applied in everycase to assure safe transferring.II. A) If condition I-A is true but I-B is not, transfer logicdelays until line current(e.g. Ia_p(t) ) crosses zero, andB) If ( |Va_p(t)| - |Va_a(t)| ) > 0 applies, initiatestransferring (Figure 5). Fault occurs at t=0.022 s, transfersignal is generated at t=0.0277 s and transferring isinitiated at t=0.0296 s.III. A) If II_B does not apply when line current(e.g. Ia_p(t) )crosses zero but the three variables are of the same signtransferring is issued when:B) ( |Va_p(t)| - |Va_a(t)| ) > 0 for the first time(Figure 6).Fault occurs at t=0.032 s, transfer signal is generated att=0.0337 s and transferring is initiated at t=0.0372 s.IV. A) Another important case is the one shown in Figure 7.Va_a(t) and Ia_p(t)) are of the same sign and Va_p(t) ofopposite sign, when a transfer signal is issued. In this casetransferring can be initiated to reduce transfer time, when:B) |Va_p(t) - Va_a(t)| is larger than a preset value ΔV2 min ,to assure successful commutation of thyristor PP1. Faultoccurs at t=0.027 s detected at t=0.0293 s. At that time,Va_p(t) takes values of opposite sign with respect toVa_a(t) and Ia_p(t) values. Furthermore, |Va_p(t) - Va_a(t)|is larger than the preset value ΔV2 min , so transferring canbe initiated. Obviously, if transferring was not issued at thetime shown in Figure 7, it could be done to satisfy condition

III approximately 3 ms later, as shown by the intersection ofthe voltage waveforms at t=0.032 s.Va_pVa_a+20+10kV +0-10-200.01 0.015 0.02 0.025 0.03 0.035 0.04Ia_pIa_a+0.4+0.2kA +0-0.2-0.40.01 0.015 0.02 0.025 0.03 0.035 0.04Fault Transfer Signal dblk_altrsrc_a+1.5+1+0.5+0kVkAVa_pVa_a+20+10+0-10-200.015 0.02 0.025 0.03 0.035 0.04 0.045Ia_pIa_a+0.4+0.2+0-0.2-0.40.015 0.02 0.025 0.03 0.035 0.04 0.045FaultTransfer Signaldblk_altrsrc_a+1.5+1+0.5+0-0.5 0.015 0.02 0.025 0.03 0.035 0.04 0.045Time (sec)4-0.5 0.01 0.015 0.02 0.025 0.03 0.035 0.04Time (sec)Fig. 4a. Instant phase voltages and line currents of phase –a (for bothalternate sources), where condition I initiates transferring.+20+10kV+0Va_pVa_a-10-200.015Ia_p0.025 0.035 Ia_a0.045 0.055+1+0.5kA+0-0.5-1 0.015Transfer Signal0.025 0.035 dblk_altrsrc_a 0.045 0.055+1.5+1+0.5+00.50.015 0.025 0.035 0.045 0.055Time (sec)Fig. 4b. Instant phase voltages and line currents of phase -a wherecommutation fails.+20Va_pVa_a+10kV +0-10-200.015 0.02 0.025 0.03 0.035 0.04 0.045+0.4Ia_pIa_a+0.2kA +0-0.2-0.40.015 0.02 0.025 0.03 0.035 0.04 0.045+1.5Fault Transfer Signal dblk_altrsrc_a+1+0.5+0-0.50.015 0.02 0.025 0.03 0.035 0.04 0.045Time (sec)Fig. 5. Instant phase voltages and line currents of phase -a for a voltage sagwhere condition II initiates transferring.Fig. 6. Instant phase voltages and line currents of phase -a for a voltage sagwhere condition III initiates transferring.Va_pVa_a+20+10kV +0-10-200.015 0.02 0.025 0.03 0.035 0.04 0.045Ia_pIa_a+0.4+0.2kA +0-0.2-0.40.015 0.02 0.025 0.03 0.035 0.04 0.045FaultTransfer Signaldblk_altrsrc_a+1.5+1+0.5+0-0.50.015 0.02 0.025 0.03 0.035 0.04 0.045Time (sec)Fig. 7. Instant phase voltages and line currents of phase –a for a voltage sagwhere condition IV initiates transferring.When voltage on the preferred source returns to itsacceptable limits, another transfer is needed. To ensure that allthree phase voltages are completely restored, a short delay of80 ms was introduced. When the transfer signal finallybecomes zero, all thyristors of alternate source side of the STSare switched off immediately and thyristors of preferred sourceside are switched on at the first zero current.III. STUDY CASEA. Power system configuration and measured eventsTo evaluate the performance of the proposed STS, an actualcase of a sensitive load(a papermill) was studied. Theinstallation of this consumer contains protection systems thattrip immediately after even shallow sags with only a shortduration. To investigate the frequency and characteristics ofvoltage sags experienced by this load, measurements ofvoltage sags were taken at the load terminals. Thesemeasurements are used to validate in a more realistic way theproposed model of the STS. Three characteristic sags arepresented in Table I.

6+20+10kV +0Va_pVa_a+1.2+1RMS voltage with STSRMS voltage without STS-10-20 0 Ia_p0.01 0.02 Ia_a0.03 0.04+0.4+0.2kA +0-0.2-0.4 0Vb_p+20+10kV+0-10-20 0Ib_p+0.4+0.2kA+0-0.2-0.4 0Vc_p+20+10kV+0-10-20+0.4+0.2kA+0-0.2-0.4 00 Ic_p0.01 0.02 0.03 0.04Vb_a0.01 0.02 0.03 0.04Ib_a0.01 0.02 0.03 0.04Vc_a0.01 0.02 Ic_a0.03 0.040.01 0.02 0.03 0.04Time (sec)Fig. 10b. Instant phase voltages and line currents in all phases of the twoalternate sources during the commutation(Event 1).+1.5+ 1+0.5+ 0Transfer SignalC o m p lete T ra n sfe r to A lt. S o urce-0 .5 0 0.01 0.02 0.03 0.04Time (sec)Fig. 10c. Signals indicating initiation of transfer procedure and completedtransferring to the alternate source(Event 1).As it can be seen in Figure 10b, it was condition III that wasfulfilled and led to successful commutation in all three phases.It is the nature of the fault and the phase angle jump it leads to,together with the angle difference between the two feeders’voltage, that makes condition III to be the most likelycondition to initiate commutation, no matter what are thevoltage magnitudes of the two feeders just before the fault andthe time at which fault occurred.• Event 2The simulation results for the event 2, are shown onFigures 11a, b, and c. The event occurred at t fault = 20 ms,detected at t det = 22.8 ms and transfer was completed at t trnsfr =24 ms. The resulting sag magnitude was 71.52% and itsduration was 12.06 ms. Voltage on the alternate feeder was setto lag the voltage on the preferred feeder by 40 0 just before theevent occurred, and their magnitudes were: V = 1.0 pu andbefaV = 1.0 pu .befppu+0.8+0.6+0.4+0.2+00 0.05 0.1 0.15 0.2 0.25 0.3Time (sec)Fig. 11a. Rms voltages with and without STS(Event 2).Va_pVa_a+20+10kV+0-10-20 0.01 0.02 0.03 0.04Ia_pIa_a+0.4+0.2kA+0-0.2-0.40.02 0.03 0.040.01Vb_pVb_a+20+10kV +0-10-20 0.010.02 0.03 0.04Ib_pIb_a+0.4+0.2kA +0-0.2-0.4 0.01 0.02 0.03 0.04Vc_pVc_a+20+10kV +0-10-20Ic_pIc_a0.01 0.02 0.03 0.04+0.4+0.2kA+0-0.2-0.4Time (sec)0.01 0.02 0.03 0.04Fig. 11b. Instant phase voltages and line currents in all phases of the twoalternate sources during the commutation(Event 2).+1.5+1+0.5+0Transfer SignalComplete Transfer to Alt. Source-0.50 0.01 0.02 0.03 0.04 0.05 0.06Time (sec)Fig. 11c. Signals indicating initiation of transfer procedure and completedtransferring to the alternate source(Event 2).In these simulations, different conditions initiatedcommutation at each phase. On phase –a it was condition III,on phase –b it was condition I and on phase –c it wascondition IV.• Event 3The simulation results for the event 3, are presented onFigures 12a, b, and c. The event occurred at t fault = 12 ms,detected at t det = 13.96 ms and transfer was completed at t trnsfr= 23.26 ms. The resulting sag magnitude was 83.73% and itsduration was 10.48 ms. Voltage on the alternate feeder was setto lag the voltage on the preferred feeder by 20 0 just before theevent occurred, and their magnitudes were: V = 1.0 pu andbefaV = 1.0 pu .befp

7+1.2+1+0.8pu +0.6+0.4+0.2+0+20+10kV+0-10RMS voltage with STSRMS voltage without STS0 0.05 0.1 0.15 0.2Time (sec)Fig. 12a. Rms voltages with and without STS(Event 3).Va_p-200.01Ia_p0.015 0.02 0.025Ia_a0.03 0.035 0.04+0.4+0.2kA +0-0.2-0.40.01Vb_p0.015 0.02 0.025Vb_a0.03 0.035 0.04+20+10kV +0-10-200.01 Ib_p 0.015 0.02 0.025Ib_a0.03 0.035 0.04+0.4+0.2kA +0-0.2-0.40.01 0.015 0.02 0.025 0.03 0.035 0.04Vc_pVc_a+20+10kV +0kA-10-200.01 0.015 0.02 0.025 0.03 0.035 0.04Ic_pIc_a+0.4+0.2+0-0.2-0.40.01 0.015 0.02 0.025 0.03 0.035 0.04Time (sec)Fig. 12b. Instant phase voltages and line currents in all phases of the twoalternate sources during the commutation(Event 3).Va_avalues (load power factor is considered constant and equal to0.9) are:1. Instant at which fault occurred. The half-period of instantvoltage(preferred source phase –a instant voltage wasused as a reference) was divided into 20 equal intervals of0.5 ms( 9 degrees), at which the fault was applied.2. Pre-fault rms voltage on the alternate feeder V abef .Voltage magnitude on preferred source was set to 1.0 pufor all runs and voltage magnitude on alternate source was1.0 or 0.95 pu.3. Phase angle difference in the two sources voltage. Φ p wasset to 0 0 and Φ a was set to take a value between –40 0 and40 0 with a step of 10 0 .Results based on all the combinations of the aboveparameters (378 runs per event) are presented in Table II. Theminimum, maximum and average values are shown. TransferTime is the time between the detection time and completetransferring(all three phases of the preferred source haveturned off and all phases of alternate source have turned on)while Total-load Transfer Time(TLTT) represents the sum ofthe Detection Time and Transfer Time. To assure thatcommutation did not fail in any of those runs, maximum valueof the three instant line currents of preferred source ismeasured for every run. A comparison between results inTable II and voltage tolerance limits of various industrialequipment shown in Table III[10], clearly shows that problemsshould not be anticipated by the sag magnitude and durationexperienced by the load, when this STS is used. It should benoted here that detection time is expected to be a few μs longerin a real system, so VSM and VSD are expected to be a bitlower and longer respectively.TABLE IISUMMARIZATION OF RESULTS BASED ON 378 RUNS PER EVENT+1.5Transfer SignalC om plete Transfer to Alt. Source+1+0.5+0-0.50.01 0.015 0.02 0.025 0.03 0.035 0.04Time (sec)Fig. 12c. Signals indicating initiation of transfer procedure and completedtransferring to the alternate source(Event 3).Figure 12b shows that condition II is responsible forcommutation at each phase. It can be concluded that either oneor a combination of the four conditions is likely to initiatetransferring for a particular event.TABLE III.VOLTAGE TOLERANCE LIMITS OF VARIOUS EQUIPMENTPRESENTLY IN USE ACCORDING TO IEEE STD. 1346.IV. INVESTIGATION ON THE STS PERFORMANCEAn investigation regarding the minimum, maximum andaverage values of DT, TT, VSM and VSD, for each event, wasconducted by performing multiple runs in the EMTDC. Theparameters which affect STS performance and their possible

8V. CONCLUSIONIn this paper, a detailed model of a Static Transfer Switch ispresented. A fast voltage detection strategy and a noveltransfer-gating scheme are proposed. All the conditions thatinfluence DT and TT and, consequently, VSM and VSDexperienced by the load, are described in detail. It is indicatedthat to evaluate STS performance, all possible combinations ofpre-fault conditions, fault type and instant should be studied.For these combinations, minimum, maximum and averagevalues of VSM and VSD need to be calculated. In the paper,measurements of three unbalanced voltage sags at theterminals of a sensitive load are used to demonstrate theperformance of the proposed STS model. It is shown that theresulting VSM and VSD for these particular events, cannotgenerate any problems to customers’ devices, according toequipment voltage tolerance limits described at IEEE Std.1346.VIII. BIOGRAPHIESM. N. Moschakis was born in 1974. He received the Diploma in ElectricalEngineering from the National Technical University of Athens (NTUA), Greece,in 1998. Currently he is a Ph.D student in NTUA. His scientific interests mainlyconcern Custom Power Device Modeling and Evaluation, and Voltage SagStochastic Assessment.N. D. Hatziargyriou is Professor at Power Division of the ElectricalEngineering Department of NTUA. His research interests include PowerSystem Transient Analysis and Modeling. He is member of CIGRE SC38 andcurrently Chairman of the IEEE Greek Power Chapter.VI. REFERENCES[1] G. Reed, M. Takeda, I. Iyoda, S. Murakami, T. Aritsuka, K. Tokuhara,“Improved Power Quality Solutions Using Advanced Solid-StateSwitching and Static Compensation Technologies”, in Proc. 1999 IEEEPower Engineering Society Winter Meeting,, vol. 2, pp. 1132-1137.[2] J. Burke, D. Griffith, D. Ward, “Power Quality-Two DifferentPerspectives”, IEEE Trans. Power Delivery, vol. 5, No.3, July 1990.[3] J. Jippling, W. Carter, “Application and Experience with a 15 kV StaticTransfer Switch”, ”, IEEE Trans. Power Delivery, vol. 14, pp. 1477-1481, October 1999.[4] H. Mokhtari, S. Dewan, M. Iravani., “Performance Evaluation ofThyristor Based Static Transfer Switch”, IEEE Trans. Power Delivery,vol. 15, pp. 960-966, July 2000.[5] H. Mokhtari, S. Dewan, M. Iravani., “Effect of Regenerative Load on aStatic Transfer Switch Performance”, IEEE Trans. Power Delivery, vol.16, pp. 619-624, October 2001.[6] H. Mokhtari, S. Dewan, M. Iravani., “Benchmark Systems for DigitalComputer Simulation of a Static Transfer Switch”, IEEE Trans. PowerDelivery, vol. 16, pp. 724-731, October 2001.[7] H. Mokhtari, S. Dewan, M. Iravani., “Analysis of a Static TransferSwitch with respect to Transfer Time”, IEEE Trans. Power Delivery,vol. 17, pp. 190-199, January 2002.[8] B. Bose, Power Electronics and Ac Drives, Prentice Hall, 1986, p. 6.[9] M. Bollen, Understanding Power Quality Problems: Voltage Sags andInterruptions, IEEE Press Series on Power Engineering, P.M. AndersonSeries Editor, 2000, p. 255.[10] Voltage characteristics of electricity supplied by public electricitydistribution networks, European Standard EN 50160, November 1994.[11] PSCAD/EMTDC Power Systems Simulation Software Manual,Manitoba HVDC Research Center, MB, Canada, 1997.VII. ACKNOWLEDGMENTThis paper presents results from the project “Power QualityAnalysis and Improvement of the Greek ElectricityDistribution Networks”. The authors gratefully acknowledgethe financial support of the Public Power Corporation ofGreece and the contributions of Professors N. Vovos and G.Giannakopoulos of University of Patras.