ANSI_SCTE 137-1 2010.pdf

7.2.6 DTI Client Test Port ............................................................................................................................ 377.2.7 DTI Client Test Port Clock .................................................................................................................. 377.2.8 Alternative EQAM DTI Testing ........................................................................................................... 407.2.9 DTI Status LEDs .................................................................................................................................. 407.3 DTI DISTRIBUTION FALLBACK STRATEGIES ................................................................................................. 41ANNEX A RANGING WANDER QUALIFICATION FILTER ..................................................................... 43A.1 CHIP TIMING JITTER FOR SYNCHRONOUS OPERATION .................................................................................. 43ANNEX B DTI-MIB (NORMATIVE) ................................................................................................................ 45APPENDIX I DTI SERVER FUNCTIONAL DESCRIPTION ..................................................................... 65I.1 SERVER DTI SIGNAL PROCESSING ................................................................................................................ 65APPENDIX II DTI CLIENT FUNCTIONAL DESCRIPTION ...................................................................... 67II.1 DTI CLIENT PHY ......................................................................................................................................... 68II.2 DTI CLIENT FRAME PROCESSOR .................................................................................................................. 69II.3 DTI CLIENT CLOCK PROCESSOR .................................................................................................................. 70APPENDIX III DTI JITTER BUDGET ............................................................................................................. 72III.1 MODEL DESCRIPTION ................................................................................................................................... 72III.2 ANALYSIS ..................................................................................................................................................... 73III.2.1 Transmit Jitter Specification ................................................................................................................ 73III.2.2 Receive Jitter Analysis ......................................................................................................................... 73III.2.3 Receive Frame Jitter Analysis ............................................................................................................. 74III.2.4 10.24 MHz Output Jitter ...................................................................................................................... 74APPENDIX IV SYMBOL CLOCK SYNCHRONIZATION ............................................................................ 75APPENDIX V DTI HIGH SPEED CLOCK CONSIDERATIONS ................................................................ 76APPENDIX VI M-CMTS SYSTEM ISSUES REGARDING USE OF DTI CONVEYED TIMEBASE BYAN M-CMTS ENTITY INCORPORATING A DTI CLIENT ............................................................................. 78VI.1 EXAMPLE ISSUES ...................................................................................................................................... 78VI.2 SOLUTION ................................................................................................................................................. 79iv