ICM205B VGA/QVGA CMOS image sensor with digital YUV output ...
ICM205B VGA/QVGA CMOS image sensor with digital YUV output ...
ICM205B VGA/QVGA CMOS image sensor with digital YUV output ...
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Pixel Clock Duty Cycle<br />
<strong>ICM205B</strong>: <strong>VGA</strong> <strong>CMOS</strong> <strong>sensor</strong> <strong>with</strong> <strong>digital</strong> <strong>YUV</strong> <strong>output</strong><br />
Engineering Specification V1.1, July. 2002<br />
In different frame rate mode (controlled by PART_CONTROL[6:3]), the duty cycle (high time / clock<br />
period) of the PCLK signal is described in the following table:<br />
Frame Rate Duty Cycle<br />
30 50.0%<br />
15 50.0%<br />
10 66.6%<br />
6 60.0%<br />
5 50.0%<br />
3 50.0%<br />
2 53.3%<br />
1 50.0%<br />
©2000, 2001, 2002 IC Media Corporation & IC Media 47<br />
Technology Corp. 2002/8/7<br />
web site: http://www.ic-media.com/<br />
web site: http://www.ic-media.com.tw/ page 47
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